CN107872358B - Automatic simulation test method for HDLC protocol - Google Patents
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Abstract
The invention discloses an automatic simulation test method aiming at an HDLC protocol, which comprises the following steps: the device comprises a test frame data generation module (1), a frame format translation module (2), a C language-based HDLC protocol gold model establishment module (3), an excitation and result database module (4), an index detection module (5) and a test result display module (6). The test data generation module (1) generates test frame data, the test data is translated into frame format data conforming to an HDLC protocol through the frame format translation module (2), the index detection module (5) simultaneously detects and reads output data of the module to be tested and the golden model, comparison is carried out, and a comparison result is displayed and output through the test result display module (6). The invention solves the problems of longer test verification time and lower coverage rate of the HDLC module, can automatically complete detection of various design indexes, and achieves the aim of quickly and accurately positioning hardware design.
Description
Technical Field
The invention relates to a simulation test method, in particular to an automatic simulation test method aiming at an HDLC protocol.
Background
In the field of military electronic component board-level communication, an HDLC (high-level data link control) protocol is a common communication protocol, a plurality of electronic devices comprise HDLC communication modules, and the quality of the HDLC module is directly related to the quality of the devices, so that the test and verification work aiming at the HDLC module is very important.
Because each model task modifies the HDLC protocol more or less, and because of the consideration of confidentiality, each unit independently develops the HDLC communication module aiming at each model task, so that the HDLC communication modules of a plurality of versions exist simultaneously, the difference among some versions is very small, and the comprehensive test of each version is still needed.
At present, the traditional military HDLC module test work is only subjected to a few software simulation verifications, coverage tests are mostly carried out on an FPGA, and the design quality of a communication module is directly tested by butting with an actual device. But due to various limitations of FPGA devices, the debugging efficiency is not high, and the rapid and accurate positioning can not be realized. The traditional index detection method is still manual observation, testers need to check each condition one by one, and a large amount of manpower and material resources need to be consumed. The disadvantages of the conventional testing method are more prominent when the design version is upgraded, and testers need to perform repeated tests after each version is modified.
For the development flow of military product SOC chips, the traditional FPGA test mode has greater limitation, and most designs still need to be verified through simulation because the FPGA cannot completely simulate the SOC circuit behaviors.
Disclosure of Invention
The invention aims to provide an automatic simulation test method for an HDLC (high-level data link control) protocol, which solves the problems of low efficiency, low coverage and poor positioning of the traditional HDLC communication module test process.
The automatic simulation test method for the HDLC protocol comprises the following specific steps:
first step, an automatic simulation test system for HDLC protocol is built
An automated simulation test system for an HDLC protocol, comprising: the device comprises a test frame data generation module, a frame format translation module, a C language-based HDLC protocol gold model establishment module, an excitation and result database module, an index detection module and a test result display module.
The function of the test frame data generation module is as follows: generating required frame data and adjusting the frame data format according to the test result;
the frame format translation module has the functions of: translating the test data into frame format data conforming to an HDLC protocol;
the function of the HDLC protocol gold model building module based on the C language is as follows: constructing a gold model;
the excitation and result database module functions as follows: providing test excitation data and storing a test result;
the index detection module has the functions of: detecting required indexes;
the test result display module has the functions of: a coverage test was performed.
The second step test frame data generation module generates the required frame data
The test frame data generating module generates required frame data according to the requirements of designers, and simultaneously adjusts the format of the frame data according to the test result so as to achieve high test coverage rate.
Thirdly, the frame format translation module carries out format translation of data
The frame format translation module is realized by C language or Verilog language, and takes parameter information of clock period, data pulse width and CRC check mode into consideration, and translates the parallel test data into serial frame format data conforming to HDLC protocol.
Fourthly, constructing a golden model by an HDLC protocol golden model building module based on C language
The HDLC protocol gold model building module based on the C language constructs a TLM design prototype with accurate period and accurate bits, and can completely simulate all external behaviors of the hardware HDLC module. The abstract level of the gold model is TLM level, the data of an excitation database needs to be read, and serial data processing is completed according to the clock signal beat, and the operation result comprises the following steps: and storing the physical waveform part and the data part into a result database.
Fifthly, the excitation and result database module stores data information
The excitation and result database module establishes an excitation database and a result database and stores data information, and the storage format comprises the following steps: waveform data and memory data. The waveform data refers to a storage result of physical waveforms of the signals according to a time sequence, and time sequence information and shape information of the signals are stored; the memory data refers to specific information of the data in the memory, and comprises HDLC protocol frame content, frame data length and CRC check results. The specific data format is realized by self-defining according to the design environment.
The sixth step is that the index detection module detects the required index
The index detection module detects indexes concerned by a series of military equipment, and comprises the following steps: data correctness detection, frame format correctness detection, response delay detection, and pulse width detection. The data correctness detection is carried out, and output data of the module to be detected and the golden model are read and compared; and the frame format correctness detection, the response delay detection and the pulse width detection only aim at the module to be detected to output data. Compare in traditional automatic test platform only detect data correctness, can cover all indexes that need artifical the detection completely, can provide accurate test violation time point simultaneously, conveniently fix a position the problem fast.
Seventhly, the test result display module performs coverage rate test
And the test result display module carries out coverage rate test, adopts a verification mode with feedback, and automatically increases the number of test excitations according to the test result and the coverage rate target required to be reached by the tester until the coverage rate target is reached. The test excitation generation mode is a semi-random generation mode, and random excitation generation under specific constraint ensures the randomness of excitation and can achieve the purpose of rapid convergence of coverage rate.
Thus, an automated simulation test for the HDLC protocol is completed.
According to the invention, by summarizing the test requirements of military HDLC communication modules, a set of automatic test method suitable for most HDLC communication modules is provided, repeated test work of testers is reduced to the maximum extent on the premise of improving test coverage, bugs existing in the design can be found at the initial stage of the design, the iteration times of the design and the test are reduced, and the development and application speed of the HDLC communication modules is accelerated. The implementation language of the golden model is C language, and good confidentiality and platform adaptability can be provided. Compared with an MATLAB model and a SystemVerilog model, the method has the advantages of high running speed, high abstract level and high confidentiality. The current situation that a military HDLC behavior model is lack of and is not uniform at present can be solved, and meanwhile, the security is high for military protocols and algorithms. The method can complete testing work of several days in one hour by using the traditional method, and has higher testing coverage rate.
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Fig. 1 is a schematic structural diagram of an automated simulation test method for an HDLC protocol.
1. The test frame data generation module 2, the frame format translation module 3, the HDLC protocol gold model establishment module 4 based on the C language, the excitation and result database module 5, the index detection module 6 and the test result display module.
Detailed Description
The automatic simulation test method for the HDLC protocol comprises the following specific steps:
first step, an automatic simulation test system for HDLC protocol is built
An automated simulation test system for an HDLC protocol, comprising: the device comprises a test frame data generation module 1, a frame format translation module 2, a C language-based HDLC protocol gold model establishment module 3, an excitation and result database module 4, an index detection module 5 and a test result display module 6.
The function of the test frame data generation module 1 is: generating required frame data and adjusting the frame data format according to the test result;
the frame format translation module 2 functions as: translating the test data into frame format data conforming to an HDLC protocol;
the function of the HDLC protocol golden model building module 3 based on the C language is as follows: constructing a gold model;
the excitation and result database module 4 functions as: providing test excitation data and storing a test result;
the function of the index detection module 5 is: detecting required indexes;
the test result display module 6 has the functions of: a coverage test was performed.
The second step test frame data generation module 1 generates the required frame data
The test frame data generating module 1 generates required frame data according to the requirements of designers, and simultaneously adjusts the format of the frame data according to the test result so as to achieve high test coverage rate.
The third step is that the frame format translation module 2 carries out format translation of data
The frame format translation module 2 is realized by C language or Verilog language, and takes parameter information of clock period, data pulse width and CRC check mode into consideration, and translates the parallel test data into serial frame format data conforming to HDLC protocol.
Fourthly, establishing a golden model by an HDLC protocol golden model establishing module 3 based on C language
The HDLC protocol gold model building module 3 based on the C language constructs a TLM design prototype with accurate period and accurate bit, and can completely simulate all external behaviors of a hardware HDLC module. The abstract level of the gold model is TLM level, the data of an excitation database needs to be read, and serial data processing is completed according to the clock signal beat, and the operation result comprises the following steps: and storing the physical waveform part and the data part into a result database.
The fifth step is that the excitation and result database module 4 stores data information
The excitation and result database module 4 establishes an excitation database and a result database, and stores data information, wherein the storage format comprises the following steps: waveform data and memory data. The waveform data refers to a storage result of physical waveforms of the signals according to a time sequence, and time sequence information and shape information of the signals are stored; the memory data refers to specific information of the data in the memory, and comprises HDLC protocol frame content, frame data length and CRC check results. The specific data format is realized by self-defining according to the design environment.
The sixth step, index detection module 5, detects the required index
The index detection module 5 detects indexes concerned by a series of military equipment, including: data correctness detection, frame format correctness detection, response delay detection, and pulse width detection. The data correctness detection is carried out, and output data of the module to be detected and the golden model are read and compared; and the frame format correctness detection, the response delay detection and the pulse width detection only aim at the module to be detected to output data. Compare in traditional automatic test platform only detect data correctness, can cover all indexes that need artifical the detection completely, can provide accurate test violation time point simultaneously, conveniently fix a position the problem fast.
The seventh step is that the test result display module 6 carries out coverage rate test
And the test result display module 6 is used for carrying out coverage rate test, and automatically increasing the number of test excitations according to the test result and the coverage rate target required to be reached by the tester by adopting a verification mode with feedback until the coverage rate target is reached. The test excitation generation mode is a semi-random generation mode, and random excitation generation under specific constraint ensures the randomness of excitation and can achieve the purpose of rapid convergence of coverage rate.
Thus, an automated simulation test for the HDLC protocol is completed.
Claims (1)
1. An automatic simulation test method for an HDLC protocol is characterized by comprising the following specific steps:
first step, an automatic simulation test system for HDLC protocol is built
An automated simulation test system for an HDLC protocol, comprising: the system comprises a test frame data generation module (1), a frame format translation module (2), a C language-based HDLC protocol gold model establishment module (3), an excitation and result database module (4), an index detection module (5) and a test result display module (6);
the function of the test frame data generation module (1) is as follows: generating required frame data and adjusting the frame data format according to the test result;
the frame format translation module (2) has the functions of: translating the test data into frame format data conforming to an HDLC protocol;
the HDLC protocol golden model building module (3) based on the C language has the functions of: constructing a gold model;
the excitation and result database module (4) has the functions of: providing test excitation data and storing a test result;
the index detection module (5) has the functions of: detecting required indexes;
the test result display module (6) has the functions of: carrying out a coverage rate test;
the output end of the test frame data generation module (1) is connected with the input end of the frame format translation module (2), the output end of the frame format translation module (2) is connected with the input end of the excitation and result database module (4), two output ends of the excitation and result database module (4) are respectively connected with the input ends of the HDLC protocol golden model building module (3) based on the C language and the module to be tested, the output ends of the HDLC protocol golden model building module (3) based on the C language and the module to be tested are respectively connected with the input end of the index detection module (5), and the output end of the index detection module (5) is connected with the input end of the test result display module (6);
the second step test frame data generation module (1) generates the required frame data
The test frame data generating module (1) generates required frame data according to the requirements of designers, and simultaneously adjusts the format of the frame data according to the test result to achieve high test coverage rate;
thirdly, the frame format translation module (2) translates the format of the data
The frame format translation module (2) is realized by C language or Verilog language, parameter information of clock period, data pulse width and CRC check mode is considered, and parallel test data is translated into serial frame format data which accords with HDLC protocol;
fourthly, constructing a gold model by an HDLC protocol gold model establishing module (3) based on the C language
The HDLC protocol gold model building module (3) based on the C language constructs a TLM design prototype with accurate period and accurate bit, and can completely simulate all external behaviors of a hardware HDLC module; the abstract level of the gold model is TLM level, the data of an excitation database needs to be read, and serial data processing is completed according to the clock signal beat, and the operation result comprises the following steps: the physical waveform part and the data part are stored in a result database;
fifthly, the excitation and result database module (4) stores data information
The excitation and result database module (4) establishes an excitation database and a result database, and stores data information in a storage format comprising: waveform data and memory data; the waveform data refers to a storage result of physical waveforms of the signals according to a time sequence, and time sequence information and shape information of the signals are stored; the memory data refers to specific information of data in the memory, and comprises HDLC protocol frame content, frame data length and CRC (cyclic redundancy check) check results; the specific data format is realized by self-defining according to the design environment;
the sixth step is that an index detection module (5) carries out required index detection
The index detection module (5) detects indexes concerned by a series of military equipment, and comprises the following steps: data correctness detection, frame format correctness detection, response delay detection and pulse width detection; the data correctness detection is carried out, and output data of the module to be detected and the golden model are read and compared; the frame format correctness detection, the response delay detection and the pulse width detection only aim at the module to be detected to output data; compared with the traditional automatic test platform which only detects the correctness of data, the method can completely cover all indexes needing manual detection, and meanwhile, accurate violation time can be provided, so that the problem can be conveniently and quickly positioned;
the seventh step is that the test result display module (6) carries out coverage rate test
The test result display module (6) carries out coverage rate test, adopts a verification mode with feedback, and automatically increases the number of test excitations according to the test result and the coverage rate target required to be reached by a tester until the coverage rate target is reached; the test excitation generation mode is a semi-random generation mode, and random excitation generation under specific constraint ensures the randomness of excitation and can achieve the purpose of rapid convergence of coverage rate;
thus, an automated simulation test for the HDLC protocol is completed.
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