CN111859832B - Chip simulation verification method and device and related equipment - Google Patents
Chip simulation verification method and device and related equipment Download PDFInfo
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- CN111859832B CN111859832B CN202010686252.XA CN202010686252A CN111859832B CN 111859832 B CN111859832 B CN 111859832B CN 202010686252 A CN202010686252 A CN 202010686252A CN 111859832 B CN111859832 B CN 111859832B
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Abstract
The application discloses a chip simulation verification method, which comprises the steps that a resource management center receives registration requests sent by all functional modules in a chip to be tested; acquiring information of each functional module according to the registration request, and registering each functional module according to the information of the functional module; receiving query requests sent by the functional modules; feeding back target function module information to the function modules according to the query request so as to enable each function module to establish connection with a target function module according to the target function module information and generate a topological network; performing simulation verification on each functional module based on the topological network; the chip simulation verification method can effectively shorten the chip development period and improve the chip development efficiency. The application also discloses a chip simulation verification device, equipment and a computer readable storage medium, which have the beneficial effects.
Description
Technical Field
The present application relates to the field of hardware technologies, and in particular, to a method for verifying chip simulation, and further, to a device, an apparatus, and a computer-readable storage medium for verifying chip simulation.
Background
As the functional complexity of the chip increases, any defect in the chip design will cause the design failure of the whole chip, and therefore, before the chip is taped, the system function of the chip must be verified, wherein the software and hardware collaborative verification technology is more and more emphasized. The software and hardware cooperative verification refers to running software through a system model to check errors in hardware design, defects in software and errors in software/hardware interfaces before the physical prototype production of hardware, and the main purpose of the software and hardware cooperative verification is to verify the correctness of system-level chip software/hardware design and develop verification application software before chip production.
At present, software and hardware collaborative verification is performed in an FPGA (Field-Programmable Gate Array) prototype verification stage, an FPGA is used for simulating and simulating a real hardware behavior, and system software runs on a platform for FPGA simulation. However, before the FPGA prototype verification, a plurality of key steps such as hardware design, front-end verification, synthesis and the like need to be performed, then the hardware design needs to be transplanted into the FPGA platform, and the correctness of the transplantation is verified, and thus, the early preparation workload is large, the price cost is high, moreover, the FPGA prototype verification is in the later stage of the whole chip development stage, if a design problem is found at this time, the previous work needs to be performed again, and extra time waste is caused.
Therefore, how to more effectively shorten the chip development cycle and improve the chip development efficiency is a problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The method can effectively shorten the development period of the chip and improve the development efficiency of the chip; another object of the present application is to provide a chip simulation verification apparatus, a device and a computer-readable storage medium, which also have the above-mentioned advantages.
In a first aspect, the present application provides a method for verifying chip simulation, including:
the resource management center receives registration requests sent by all functional modules in the chip to be tested;
obtaining information of each functional module according to the registration request, and registering each functional module according to the information of the functional module;
receiving query requests sent by the functional modules;
feeding back target function module information to the function modules according to the query request so as to enable each function module to establish connection with a target function module according to the target function module information and generate a topological network;
and performing simulation verification on each functional module based on the topological network.
Preferably, the registering each of the function modules according to the function module information includes:
storing the information of each functional module to a resource linked list; the function module information includes IP information, port information, and resource data of the function module.
Preferably, the feeding back target function module information to the function module according to the query request includes:
determining target resource data according to the query request;
determining IP information and port information of the target function module according to the target resource data;
and feeding back the IP information and the port information of the target function module to the function module.
Preferably, after registering each of the functional modules according to the functional module information, the method further includes:
and feeding back a registration result to each functional module so that each functional module sends the query request to the resource management center according to the registration result.
Preferably, the simulation verification of each functional module based on the topological network includes:
the functional module sends a resource access request to the target functional module to determine whether request response information fed back by the target functional module is received; the resource access request is a data read request and/or a data write request.
Preferably, the sending, by the function module, the resource access request to the target function module includes:
and the functional module sends a resource access request to the target functional module through a TCP protocol.
Preferably, the chip simulation verification method further includes:
and when the resource data in the target function module are changed, sending the resource change information to the function module.
In a second aspect, the present application further discloses a chip simulation verification apparatus, including:
a registration request receiving unit, which is used for the resource management center to receive the registration request sent by each functional module in the chip to be tested;
a function module registration unit, configured to obtain information of each function module according to the registration request, and register each function module according to the information of the function module;
a query request receiving unit, configured to receive a query request sent by each of the function modules;
a topology network generating unit, configured to feed back target function module information to the function modules according to the query request, so that each function module establishes a connection with a target function module according to the target function module information, and generates a topology network;
and the chip verification unit is used for performing simulation verification on each functional module based on the topological network.
In a third aspect, the present application further discloses a chip simulation verification apparatus, including:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of any of the chip simulation verification methods described above.
In a fourth aspect, the present application further discloses a computer-readable storage medium, in which a computer program is stored, and the computer program is used to implement the steps of any one of the chip simulation verification methods described above when being executed by a processor.
The chip simulation verification method comprises the steps that a resource management center receives registration requests sent by all functional modules in a chip to be tested; acquiring information of each functional module according to the registration request, and registering each functional module according to the information of the functional module; receiving query requests sent by the functional modules; feeding back target function module information to the function modules according to the query request so as to enable each function module to establish connection with a target function module according to the target function module information and generate a topological network; and performing simulation verification on each functional module based on the topological network.
Therefore, the chip simulation verification method provided by the application has the advantages that for each functional module in the chip to be tested, the network topology is completed by registering and inquiring the resource management center, so that the connection can be established among the functional modules for direct communication without forwarding through the resource management center, the system efficiency is effectively improved, moreover, by constructing the topological network, each functional module in the topological network can be verified in each platform without being transplanted to the same platform, thereby greatly reducing the time overhead of constructing and configuring different environments on the same platform, meanwhile, by adopting the verification method, software personnel can intervene in the verification process in the middle stage before chip development, so that software and hardware cooperative verification and parallel execution of other work are realized, the chip development period is more effectively shortened, and the chip development efficiency is improved.
The chip simulation verification device, the equipment and the computer readable storage medium provided by the application all have the beneficial effects, and are not described again.
Drawings
In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the drawings that are needed to be used in the description of the prior art and the embodiments of the present application will be briefly described below. Of course, the following description of the drawings related to the embodiments of the present application is only a part of the embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the provided drawings without any creative effort, and the obtained other drawings also belong to the protection scope of the present application.
Fig. 1 is a schematic flowchart of a chip simulation verification method provided in the present application;
fig. 2 is a block diagram of a chip emulation verification platform according to the present application;
fig. 3 is a flowchart of resource information registration provided in the present application;
fig. 4 is a flowchart of a topology network construction provided in the present application;
fig. 5 is a schematic structural diagram of a chip simulation verification apparatus provided in the present application;
fig. 6 is a schematic structural diagram of a chip simulation verification apparatus provided in the present application.
Detailed Description
The core of the application is to provide a chip simulation verification method, which can effectively shorten the development period of a chip and improve the development efficiency of the chip; another core of the present application is to provide a chip simulation verification apparatus, a device and a computer-readable storage medium, which also have the above beneficial effects.
In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart of a chip simulation verification method provided in the present application, where the chip simulation verification method may include:
s101: the resource management center receives registration requests sent by all functional modules in the chip to be tested;
the chip simulation verification method provided by the application is realized based on a software and hardware cooperation verification technology, and before the physical prototype of the chip is produced, software is operated through a system model so as to check errors in hardware design, defects in the software and errors in a software/hardware interface.
Specifically, the verification of the chip function is the verification of each functional module in the chip, that is, the chip is divided into a plurality of functional modules, and then each functional module is subjected to function verification, the verification process is realized by a resource management center, which is equivalent to a main control module, specifically, the functional modules can be CPUs virtualized by qemulgators and virtualizers (a general open-source computer simulator developed by fabry bela, which can be used to simulate processors of various architectures), and of course, each functional module in the chip to be tested can also be realized by a virtual CPU. Furthermore, before the chip simulation verification, the corresponding connection relation of each functional module can be established, and a topological network in which each functional module can directly perform data interaction is generated, so that the verification of each functional module in the chip to be tested can be completed in the topological network. In the step, the registration request is received, that is, each functional module in the chip to be tested sends a registration request to the resource management center, so as to register each functional module in the resource management center.
S102: acquiring information of each functional module according to the registration request, and registering each functional module according to the information of the functional module;
the step aims to realize the registration of each functional module in the resource management center, and particularly, when each functional module sends a registration request to the resource management center, the relevant information of the functional module, namely the information of the functional module, can be added in the registration request, so that the resource management center can complete the registration of the corresponding functional module according to the information of the functional module. The registration process is equivalent to the storage process of the functional module information, and a functional module which only sends a registration request to the resource management center and does not provide the functional module information cannot complete registration or access the finally constructed topology network.
As a preferred embodiment, the registering each function module according to the function module information may include: storing the information of each functional module to a resource linked list; the function module information includes IP information, port information, and resource data of the function module.
The preferred embodiment provides a more specific registration method for functional modules, and specifically, the resource management center may maintain a resource linked list for registering each functional module, the resource linked list is empty before module registration, and when the resource management center receives a registration request, the resource management center may sequentially store information of the functional modules in the resource linked list. The functional module information may specifically include IP information, port information, and resource data of the corresponding functional module, where the port information may specifically be a port number, and the resource data is resource information externally provided by the corresponding functional module.
S103: receiving query requests sent by all functional modules;
s104: feeding back target function module information to the function modules according to the query request so that each function module establishes connection with the target function module according to the target function module information to generate a topological network;
the steps aim at realizing the generation of the topological network, and after each functional module finishes the registration, the corresponding connection relation can be established by inquiring the resource management center to generate the complete topological network. Specifically, each functional module sends a query request to the resource management center according to its own needs to obtain target functional module information fed back by the resource management center, and then establishes connection with the target functional module, where the target functional module information is information of a functional module that needs to establish a connection relationship with the functional module that sends the query request, that is, each functional module may be a module that sends the query request or may become a target functional module of other functional modules, and thus, the construction of the topology network is completed, and in the topology network, data interaction can be directly performed between two functional modules having a connection relationship.
As a preferred embodiment, the feeding back the target function module information to the function module according to the query request may include: determining target resource data according to the query request; determining IP information and port information of the target function module according to the target resource data; and feeding back the IP information and the port information of the target function module to the function module.
The preferred embodiment provides a method for feeding back information of a specific target function module, wherein each function module can add relevant information of resource data required by the function module, namely the target resource data, into a query request, so that a resource management center can query and determine the IP information and the port information of the target function module providing the target resource data from a resource linked list according to the target resource data, further feed back the IP information and the port information of the target function module to the function module, and the function module can establish a connection relation with the corresponding target function module according to the IP information and the port information.
As a preferred embodiment, after registering each function module according to the function module information, the method may further include: and feeding back the registration result to each functional module so that each functional module sends a query request to the resource management center according to the registration result.
The preferred embodiment aims to realize registration feedback, and after the registration is completed for the registration request initiated by each functional module, a corresponding registration result can be fed back to the functional module to inform that the functional module is successfully registered or fails to register, only the functional module which is successfully registered can send an inquiry request to the resource management center to establish a topology network, and the functional module which fails to register needs to be registered again to effectively ensure the availability of each functional module.
S105: and performing simulation verification on each functional module based on the topological network.
The method aims to realize the simulation verification of each functional module in the chip to be tested, and after the construction of the topology network is completed, each functional module can directly perform data interaction with a target functional module which has a connection relation with the functional module according to actual requirements so as to complete the simulation verification. The construction of the topology network ensures that data interaction can be directly carried out among all the functional modules, a resource management center is not required to carry out data forwarding, and the chip verification efficiency is effectively improved.
As a preferred embodiment, the simulation verification of each functional module based on the topology network may include: the functional module sends a resource access request to the target functional module to determine whether request response information fed back by the target functional module is received; the resource access request is a data read request and/or a data write request.
The preferred embodiment introduces the verification process of each functional module in the topology network more specifically, and after the connection relationship is established, each functional module can send a resource access request to its corresponding target functional module to determine whether it can receive its corresponding response information. The resource access request can be specifically a data read-write request, and for the data read request, when the functional module receives a data packet fed back by the target functional module and the data packet is an effective data packet, the response is successful; and for the data writing request, when receiving the information of successful writing fed back by the target functional module, responding successfully.
As a preferred embodiment, the sending, by the function module, the resource access request to the target function module may include: the function module sends a resource access request to the target function module through a TCP (Transmission Control Protocol).
The preferred embodiment provides a specific data interaction method, that is, the method is realized based on a TCP protocol, has high reliability, can realize the connection of each functional module between different networks, and avoids time waste caused by transplanting each functional module to the same network platform for verification. Of course, the selection of the above transmission protocol is only one implementation manner provided by the preferred embodiment, and is not unique, and the connection of each functional module between different networks may be implemented, which is not limited in this application.
As a preferred embodiment, the chip simulation verification method may further include: and when the resource data in the target function module is changed, sending the resource change information to the function module.
Specifically, for the functional module in which the externally provided resource data changes, the corresponding resource change information can be fed back to the functional module connected to the functional module in real time, so as to update the resource data in real time, ensure that the resource data accessed by the functional module is valid data, and further ensure that the chip verification is performed smoothly.
Therefore, the chip simulation verification method provided by the application has the advantages that for each functional module in the chip to be tested, the network topology is completed by registering and inquiring the resource management center, so that the connection can be established among the functional modules for direct communication without forwarding through the resource management center, the system efficiency is effectively improved, moreover, by constructing the topological network, each functional module in the topological network can be verified in each platform without being transplanted to the same platform, thereby greatly reducing the time overhead of constructing and configuring different environments on the same platform, meanwhile, by adopting the verification method, software personnel can intervene in the verification process in the middle stage before chip development, so that software and hardware cooperative verification and parallel execution of other work are realized, the chip development period is more effectively shortened, and the chip development efficiency is improved.
On the basis of the above embodiments, the preferred embodiment provides a more specific chip simulation verification method.
Firstly, please refer to fig. 2, fig. 2 is a frame diagram of a chip simulation verification platform provided in the present application, wherein a system resource management service is the above resource management center, QEMU context-a 53, an algorithm IP core, a serial port IP core, and QEMU context-M3 are each function module in a chip to be tested, each function module can be realized by a QEMU virtual CPU, and a transaction is realized by using SystemC (a computer language), systemveilog (a computer language), and the like. And, each functional module realizes data communication through TCP, more specifically, each functional module in the system comprises a TCP communication submodule, which is used for converting the access request of the functional module to the resource into TCP communication and sending the TCP communication to the corresponding functional module, and the TCP communication submodule of the corresponding functional module analyzes the request and transmits the request to the inside of the corresponding functional module for processing.
Furthermore, in order to make the communication between the functional modules more flexible, the network topology can be completed by registering and inquiring the system resource management service, after the network topology is completed, the functional modules can establish connection direct communication with the corresponding modules, and the communication does not need to be forwarded by the system resource management module, so that the system efficiency is improved. The data communication specifically includes that a functional module sends and receives a read-write request, the functional module sends the read-write request, the functional module realized based on QEMU and SystemC can directly call C language to send TCP data packets when needing to read and write, and SystemVerilog can call C language to send TCP data packets through a DPI Interface (Direct Programming Interface); for the functional module to receive the read-write request, starting a timer based on the functional module realized by QEMU and SystemC, receiving a TCP data packet at regular time, and responding to the data packet if the data packet is valid; the SystemVerilog may call a data receiving function through a DPI Interface on an AXI (Advanced eXtensible Interface, an on-chip Bus protocol), an AHB/APB (Advanced High Performance Bus) or PCIe Bus (Peripheral Component Interconnect express) clock rising edge, and process a valid data packet.
Further, based on the above chip simulation verification platform framework, the chip simulation verification process provided by the embodiment of the present application is specifically introduced. In order to realize the flexibility of the system, the system does not specify the IP address of the functional module, so that before starting the simulation verification, the functional module does not know on which computer the resources of other functional modules required by the functional module run, so that a topology network needs to be established first, and the establishment of the topology network includes two parts, namely registration and query of the module resources, and the detailed steps are as follows:
referring to fig. 3, fig. 3 is a resource information registration flowchart provided in the present application, first, a system resource management service is started, and the number of function modules required for this simulation verification is set, where the system resource management service is used as a TCP server for connection of each function module, and then a resource linked list is maintained for registration of each function module, and an initial resource linked list is empty; further, each functional module connects to a TCP server of the system resource management service, and performs resource registration to the system resource management service through TCP communication, and simultaneously starts the TCP server for connection with other functional modules and resource access, if the functional module does not provide accessible resources to other functional modules, then does not perform resource registration to the system, and does not start the TCP server, as in module 1 and module 4 in fig. 3; and finally, when the system resource management service detects that the functional modules required by the simulation are registered completely, sending a resource preparation completion notification to each functional module. Referring to fig. 4, fig. 4 is a flow chart of a topology network construction provided in the present application, after receiving a resource preparation completion notification sent by a system resource management service, each functional module queries an IP address and a port of the functional module corresponding to a resource required by the functional module to the system resource management service, and establishes a TCP connection with the IP address and the port to complete a network topology.
In the topology network, the functional module providing resources to the system is a resource provider, the module using resources of other functional modules in the system is a resource user, the resource user can read and write the storage spaces, the resource provider can modify the contents of the storage spaces according to the working logic in the resource provider itself, or perform corresponding actions according to the values of the storage spaces, and can also send a notification to the resource user according to the actual situation to inform the resource user that the related resource data is changed.
Furthermore, for the above TCP communication protocol, the embodiment of the present application is defined more specifically, the TCP communication protocol defines commands and responses required for the system to establish communication from the topology network to the resource access, and for convenience of protocol expansion, a variable length data frame is adopted, where the data frame includes a frame header, a command, a data length, data, and a frame trailer, and specifically as shown in table 1:
table 1 communication protocol definition table
| Domain name | Frame header | Command | Data length | Data of | Frame end |
| Length (byte) | 2 | 4 | 2 | N (N and data length field equal in value) | 2 |
Frame head: TCP is based on a communication protocol of byte streams, so frame headers are needed for frame synchronization;
command: the specific function of the data frame is detailed in table 2, and can be expanded according to the needs;
data length: the length of the data in the frame is represented, and specific values are related to commands, which are detailed in table 2;
data: the specific value of the data transmitted by the data frame command is related to the command, which is detailed in table 2;
and (4) frame end: the same as the frame header.
Referring to table 2, table 2 shows the command and data definitions of the communication protocol in table 1:
TABLE 2 Command and data definition Table in communication protocol
It can be seen that, in the chip simulation verification method provided in the embodiment of the present application, for each functional module in the chip to be tested, the network topology is completed by registering and inquiring the resource management center, so that the connection can be established among the functional modules for direct communication without forwarding through the resource management center, the system efficiency is effectively improved, moreover, by constructing the topological network, each functional module in the topological network can be verified in each platform without being transplanted to the same platform, thereby greatly reducing the time overhead of constructing and configuring different environments on the same platform, meanwhile, by adopting the verification method, software personnel can intervene in the verification process in the middle stage before chip development, so that software and hardware cooperative verification and parallel execution of other work are realized, the chip development period is more effectively shortened, and the chip development efficiency is improved.
To solve the above technical problem, the present application further provides a chip emulation verification apparatus, please refer to fig. 5, where fig. 5 is a schematic structural diagram of the chip emulation verification apparatus provided in the present application, and the chip emulation verification apparatus may include:
a registration request receiving unit 1, configured to receive, by a resource management center, a registration request sent by each functional module in a chip to be tested;
a function module registration unit 2, configured to obtain information of each function module according to the registration request, and register each function module according to the information of the function module;
the query request receiving unit 3 is used for receiving query requests sent by the functional modules;
the topological network generating unit 4 is used for feeding back target function module information to the function modules according to the query request so that each function module establishes connection with the target function module according to the target function module information to generate a topological network;
and the chip verification unit 5 is used for performing simulation verification on each functional module based on the topological network.
It can be seen that, the chip simulation verification apparatus provided in the embodiment of the present application, for each functional module in the chip to be tested, the network topology is completed by registering and inquiring the resource management center, so that the connection can be established among all the functional modules for direct communication without forwarding through the resource management center, the system efficiency is effectively improved, moreover, by constructing the topological network, each functional module in the topological network can be verified in each platform without being transplanted to the same platform, thereby greatly reducing the time overhead of constructing and configuring different environments on the same platform, meanwhile, by adopting the verification method, software personnel can intervene in the verification process in the middle stage before chip development, so that software and hardware cooperative verification and parallel execution of other work are realized, the chip development period is more effectively shortened, and the chip development efficiency is improved.
For the introduction of the apparatus provided in the present application, please refer to the above method embodiments, which are not described herein again.
To solve the above technical problem, the present application further provides a chip emulation verification apparatus, please refer to fig. 6, where fig. 6 is a schematic structural diagram of the chip emulation verification apparatus provided in the present application, and the chip emulation verification apparatus may include:
a memory 10 for storing a computer program;
the processor 20, when executing the computer program, may implement the steps of any of the above-described chip simulation verification methods.
For the introduction of the device provided in the present application, please refer to the above method embodiment, which is not described herein again.
In order to solve the above problem, the present application further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, can implement any of the steps of the chip simulation verification method described above.
The computer-readable storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
For the introduction of the computer-readable storage medium provided in the present application, please refer to the above method embodiments, which are not described herein again.
The embodiments are described in a progressive mode in the specification, the emphasis of each embodiment is on the difference from the other embodiments, and the same and similar parts among the embodiments can be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The technical solutions provided by the present application are described in detail above. The principles and embodiments of the present application are described herein using specific examples, which are only used to help understand the method and its core idea of the present application. It should be noted that, for those skilled in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall into the protection scope of the present application.
Claims (9)
1. A chip simulation verification method is characterized by comprising the following steps:
the resource management center receives registration requests sent by all functional modules in the chip to be tested;
acquiring information of each functional module according to the registration request, and storing the information of each functional module to a resource linked list; the functional module information comprises IP information, port information and resource data of the functional module;
receiving query requests sent by the functional modules;
feeding back target function module information to the function modules according to the query request so as to enable each function module to establish connection with a target function module according to the target function module information and generate a topological network;
and performing simulation verification on each functional module based on the topological network.
2. The method for verifying chip simulation according to claim 1, wherein the feeding back target function module information to the function module according to the query request comprises:
determining target resource data according to the query request;
determining IP information and port information of the target function module according to the target resource data;
and feeding back the IP information and the port information of the target function module to the function module.
3. The method for verifying chip simulation according to claim 1, wherein after registering each of the functional modules according to the functional module information, the method further comprises:
and feeding back a registration result to each functional module so that each functional module sends the query request to the resource management center according to the registration result.
4. The method according to any one of claims 1 to 3, wherein the performing simulation verification on each functional module based on the topology network includes:
the functional module sends a resource access request to the target functional module to determine whether request response information fed back by the target functional module is received; the resource access request is a data read request and/or a data write request.
5. The method for verifying chip emulation according to claim 4, wherein the sending, by the functional module, the resource access request to the target functional module comprises:
and the functional module sends a resource access request to the target functional module through a TCP protocol.
6. The method for verifying chip simulation according to claim 4, further comprising:
and when the resource data in the target function module are changed, sending the resource change information to the function module.
7. A chip emulation verifying apparatus, comprising:
a registration request receiving unit, which is used for the resource management center to receive the registration request sent by each functional module in the chip to be tested;
the functional module registration unit is used for acquiring information of each functional module according to the registration request and storing the information of each functional module to a resource linked list; the functional module information comprises IP information, port information and resource data of the functional module;
a query request receiving unit, configured to receive a query request sent by each of the function modules;
a topology network generating unit, configured to feed back target function module information to the function modules according to the query request, so that each function module establishes a connection with a target function module according to the target function module information, and generates a topology network;
and the chip verification unit is used for carrying out simulation verification on each functional module based on the topological network.
8. A chip emulation verification apparatus, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of the chip emulation verification method of any one of claims 1 to 6.
9. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the chip simulation verification method according to any one of claims 1 to 6.
Priority Applications (1)
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| CN113591422B (en) * | 2021-08-03 | 2024-01-30 | 眸芯科技（上海）有限公司 | System for generating test case flow information in chip verification and application |
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| CN114330178B (en) * | 2021-12-28 | 2023-03-14 | 杭州朗迅科技有限公司 | Drive system for debugging and verifying embedded hardware circuit |
| CN117556754B (en) * | 2024-01-11 | 2024-03-19 | 北京数渡信息科技有限公司 | PCIe switch chip pre-silicon simulation system |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6678645B1 (en) * | 1999-10-28 | 2004-01-13 | Advantest Corp. | Method and apparatus for SoC design validation |
| CN101051332A (en) * | 2007-05-23 | 2007-10-10 | 中兴通讯股份有限公司 | Verifying system and method for SOC chip system grade |
| CN101377793A (en) * | 2008-09-22 | 2009-03-04 | 浪潮电子信息产业股份有限公司 | SOC chip logic verification method for server safe monitoring management |
| CN101377795A (en) * | 2008-09-22 | 2009-03-04 | 浪潮电子信息产业股份有限公司 | SOC chip logical verification method special for industry portable terminal |
| US7571284B1 (en) * | 2004-06-30 | 2009-08-04 | Sun Microsystems, Inc. | Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor |
| CN103036734A (en) * | 2011-10-10 | 2013-04-10 | 盛科网络（苏州）有限公司 | Logic verification method and logic verification system for network chip |
| CN103439648A (en) * | 2013-08-08 | 2013-12-11 | 北京华大信安科技有限公司 | Validation method, validation device and chip |
| CN104572384A (en) * | 2014-12-25 | 2015-04-29 | 记忆科技(深圳)有限公司 | Chip multi-FPGA (Field Programmable Gate Array) verification method and system |
| JP2015096997A (en) * | 2013-11-15 | 2015-05-21 | 株式会社メガチップス | Logic verification method |
| CN105158681A (en) * | 2015-08-07 | 2015-12-16 | 广州中大微电子有限公司 | Radio frequency identification reader chip verification method and system |
| CN105512418A (en) * | 2015-12-18 | 2016-04-20 | 山东海量信息技术研究院 | Method for realizing block level verification through multiplexing system level model verification environment |
| CN106133537A (en) * | 2014-12-30 | 2016-11-16 | 京微雅格（北京）科技有限公司 | A kind of FPGA function module emulation verification method and system thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8997034B2 (en) * | 2012-07-30 | 2015-03-31 | Synopsys, Inc. | Emulation-based functional qualification |
-
2020
- 2020-07-16 CN CN202010686252.XA patent/CN111859832B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6678645B1 (en) * | 1999-10-28 | 2004-01-13 | Advantest Corp. | Method and apparatus for SoC design validation |
| US7571284B1 (en) * | 2004-06-30 | 2009-08-04 | Sun Microsystems, Inc. | Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor |
| CN101051332A (en) * | 2007-05-23 | 2007-10-10 | 中兴通讯股份有限公司 | Verifying system and method for SOC chip system grade |
| CN101377793A (en) * | 2008-09-22 | 2009-03-04 | 浪潮电子信息产业股份有限公司 | SOC chip logic verification method for server safe monitoring management |
| CN101377795A (en) * | 2008-09-22 | 2009-03-04 | 浪潮电子信息产业股份有限公司 | SOC chip logical verification method special for industry portable terminal |
| CN103036734A (en) * | 2011-10-10 | 2013-04-10 | 盛科网络（苏州）有限公司 | Logic verification method and logic verification system for network chip |
| CN103439648A (en) * | 2013-08-08 | 2013-12-11 | 北京华大信安科技有限公司 | Validation method, validation device and chip |
| JP2015096997A (en) * | 2013-11-15 | 2015-05-21 | 株式会社メガチップス | Logic verification method |
| CN104572384A (en) * | 2014-12-25 | 2015-04-29 | 记忆科技(深圳)有限公司 | Chip multi-FPGA (Field Programmable Gate Array) verification method and system |
| CN106133537A (en) * | 2014-12-30 | 2016-11-16 | 京微雅格（北京）科技有限公司 | A kind of FPGA function module emulation verification method and system thereof |
| CN105158681A (en) * | 2015-08-07 | 2015-12-16 | 广州中大微电子有限公司 | Radio frequency identification reader chip verification method and system |
| CN105512418A (en) * | 2015-12-18 | 2016-04-20 | 山东海量信息技术研究院 | Method for realizing block level verification through multiplexing system level model verification environment |
Non-Patent Citations (3)
| Title |
|---|
| AFDX-ES SoC虚拟仿真平台的构建与应用;田靖 等;《计算机技术与发展》;20100810;第20卷(第08期);第192-194、198页 * |
| VHDL-AMS modelling of multi-chip SiC power modules;Olufisayo Olanrewaju 等;《2016 IEEE 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)》;20161231;第347-352页 * |
| 基于FPGA的接口芯片逻辑设计及仿真;张皓月 等;《软件导刊》;20111031;第10卷(第10期);第45-46页 * |
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