CN114024871B - Chip verification method, system, computer equipment and readable storage medium - Google Patents
Chip verification method, system, computer equipment and readable storage medium Download PDFInfo
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Abstract
The invention discloses a chip verification method, a system, computer equipment and a readable storage medium, wherein the method comprises the following steps: running a verification environment at the server, and executing the following steps based on the verification environment: creating a socket-based link to allow receipt of commands sent by client software over a network; in response to receiving a command sent by the client software through the network, analyzing the command and sending a return command to the client software; and converting the analyzed command into physical bus access to access the register of the chip to be verified based on the bus access protocol of the chip to be verified. The method further comprises the following steps: the software is run on the client side and performs the following steps: a socket-based link is established with an authentication environment of a server to send a command to the authentication environment over a network, wherein the command is for accessing a register of a chip to be authenticated in the authentication environment. The scheme of the invention improves the chip verification quality and accelerates the chip verification speed.
Description
Technical Field
The present invention relates to the field of chip verification technologies, and in particular, to a chip verification method, a chip verification system, a computer device, and a readable storage medium.
Background
In the development process of chips, verification is an important ring, and each chip is subjected to a great amount of test verification from a module level, a system level and finally to a chip level. At present, most of conventional verification methods adopt functional verification to build a verification environment for a part to be tested, generate excitation and check a corresponding output result. However, in the test and verification process, when input excitation needs to be adjusted according to an output result, some software algorithms are often accompanied, most of the algorithms are realized by adopting C language, how to verify the hardware function of the chip and the correctness of the algorithms as early as possible becomes an important ring in the chip design and development process, and also provides a new challenge for the chip verification method. If the complete algorithm is subjected to functional simulation, the algorithm needs to be compiled into a dynamic link library and loaded into an EDA simulation tool, but the problems that the simulation time is multiplied and the like caused by the increase of the scale of the design to be tested are bound to be faced, meanwhile, the debugging of software codes in the EDA simulation tool is very inconvenient, and the adverse factors can cause the increase of the chip verification period. In order to solve the problem, a common method at present is to simplify a software algorithm and simulate the software algorithm in an EDA tool by writing a corresponding test case, but the method needs a verifier to deeply know an algorithm model, otherwise, the correctness of the algorithm and the hardware implementation is difficult to verify.
Disclosure of Invention
In view of this, the invention provides a chip verification method, a system, a computer device and a readable storage medium, which organically combine algorithm verification and chip verification through a network, so that the development environment and debugging tools of software algorithms are not limited any more, and the chip verification quality is improved.
In view of the foregoing, an aspect of the embodiments of the present invention provides a chip verification method, where a server runs a verification environment, and the following steps are performed based on the verification environment:
creating a socket-based link to allow receipt of commands sent by client software over a network;
in response to receiving a command sent by the client software through the network, analyzing the command and sending a return command to the client software;
and converting the analyzed command into physical bus access to access the register of the chip to be verified based on a bus access protocol of the chip to be verified.
Analyzing the command and sending a return command to the client software, wherein the steps of:
judging whether the command is a disconnection link;
if the command is not the disconnection link, judging whether the command is the write operation of the register;
and if the command is write operation on the register, generating register write bus access and sending a return command to the client software.
In some embodiments, the method further comprises:
if the command is not the write operation of the register, judging whether the command is the read operation of the register;
and if the command is read operation of the register, generating register read bus access, and sending a return command with data to the client software.
In some embodiments, the method further comprises:
and if the command is not the read operation of the register, sending a return command with data to the client software.
In some embodiments, the method further comprises:
and if the command is a disconnection link, sending a return command with data to the client software, and disconnecting the link.
In some embodiments, in response to receiving a command sent by the client software over a network, parsing the command, and sending a return command to the client software, includes:
in response to receiving a command sent by a plurality of the client software over a network, creating a corresponding number of threads based on the client software;
and analyzing the command sent by each client software based on the corresponding thread, and sending a return command to the client software.
In another aspect of the embodiments of the present invention, a chip verification method is further provided, where software is run at a client, and the software executes the following steps:
establishing a socket-based link with a verification environment of a server to send a command to the verification environment over a network, wherein the command is used to access a register of a chip to be verified in the verification environment.
In another aspect of the embodiments of the present invention, a chip verification system is further provided, including:
a listening process configured to create a socket-based link to allow receipt of commands sent by client software over a network;
the command analysis module is configured to respond to a command sent by the client software through a network, analyze the command and send a return command to the client software;
the bus function module is configured to convert the analyzed command into physical bus access to access a register of the chip to be verified based on a bus access protocol of the chip to be verified.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing a computer program executable on the processor, the computer program when executed by the processor implementing the steps of the method as above.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has at least the following beneficial technical effects: by running software at a client, running a verification environment at a server, monitoring the network state by establishing a link in the verification environment, analyzing a command when the command sent by the client software is monitored, converting the analyzed command into a physical bus to access to realize the access to an internal register of a chip to be verified, realizing the cooperative verification of a software algorithm and the chip, improving the verification quality of the chip and accelerating the verification speed of the chip; when a plurality of pieces of software are executed in parallel, the chips are verified in a unified way in a multithreading mode, the verification time is further shortened, hardware resources are fully utilized, and the correctness of the internal functions of the chips during the concurrent execution of the multi-core tasks is verified.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a block diagram of an embodiment of a chip verification method provided by the present invention;
FIG. 2 is a flow diagram illustrating one embodiment of receiving and parsing commands in a verification environment, in accordance with the present invention;
FIG. 3 is a schematic structural diagram of a chip verification method according to another embodiment of the present invention;
FIG. 4 is a block diagram illustrating an embodiment of multi-threaded concurrent chip verification of client software and a verification environment according to the present invention;
FIG. 5 is a diagram illustrating a chip verification system according to an embodiment of the present invention;
FIG. 6 is a block diagram of yet another embodiment of a chip verification system provided by the present invention;
FIG. 7 is a schematic structural diagram of an embodiment of a computer device provided in the present invention;
fig. 8 is a schematic structural diagram of an embodiment of a computer-readable storage medium provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above object, a first aspect of the embodiments of the present invention provides an embodiment of a chip verification method. As shown in fig. 1, a verification environment is run on a server, and the following steps are executed based on the verification environment:
step S101, creating a link based on a socket to allow receiving a command sent by client software through a network;
step S103, responding to the received command sent by the client software through the network, analyzing the command, and sending a return command to the client software;
and step S105, converting the analyzed command into physical bus access to access a register of the chip to be verified based on a bus access protocol of the chip to be verified.
And responding to the test verification start of the chip, creating a link in a verification environment, monitoring the network state in real time, and waiting for a link request sent by client software.
And the network communication function is realized by adopting a DPI mode. Specifically, a socket is established based on the socket function, the network state is monitored, and the request for accessing other client software is allowed to be received.
The specific function is defined as follows, where the parameter port represents a defined server port:
int listen_fd,command_fd;
void mm_start(unsigned int port)
{
v. statement socket attribute construct
struct socketaddr_in servaddr;
V. establishing a socket +
listen_fd = socket(AF_INET,SOCK_STREAM,0);
…
V binding socket to machine port number +
bind( listen_fd,(struct sockaddr*)& servaddr,sizeof(servaddr));
V setting socket in listen mode
listen(listen_fd,1);
V. waiting for a link request from a client +
command_fd = accept( listen_fd,(struct sockaddr*)NULL,NULL);
}
If the command sent by the client software through the network is monitored, analyzing the command, converting the command into the contents of read-write instructions, access addresses, data and the like of the internal register of the chip to be verified, and sending a corresponding return command to the client software; and converting the analyzed command into physical bus access based on a bus access protocol of the chip to be verified so as to access a relevant register in the chip to be verified.
In the embodiment, the verification environment monitors the network state by creating the link, when a command sent by the client software is monitored, the command is analyzed, and the analyzed command is converted into the physical bus access to realize the access to the internal register of the chip to be verified, so that the cooperative verification of the software algorithm and the chip is realized, the verification quality of the chip is improved, and the verification speed of the chip is accelerated.
Analyzing the command and sending a return command to the client software, wherein the steps of:
judging whether the command is a disconnection link;
if the command is not the disconnection link, judging whether the command is the write operation of the register;
and if the command is write operation on the register, generating register write bus access and sending a return command to the client software.
In some embodiments, the method further comprises:
if the command is not the write operation of the register, judging whether the command is the read operation of the register;
and if the command is read operation of the register, generating register read bus access, and sending a return command with data to the client software.
In some embodiments, the method further comprises:
and if the command is not the read operation of the register, sending a return command with data to the client software.
In some embodiments, the method further comprises:
and if the command is a disconnection link, sending a return command with data to the client software, and disconnecting the link.
Several embodiments of the present invention are described below with reference to specific examples.
When the verification environment receives a command transmitted through a network, the command needs to be split and analyzed. The data format can be customized according to the requirements of users.
The specific function is defined as follows, where cmd represents the received command, offset represents the address of the register to be accessed, value represents the data of the register to be accessed, and opcode represents the operation mode selection:
int mm_getcommand(unsigned short *cmd，unsigned short *offset，unsigned short *value，unsigned short *opcode )
{
v variable assertion
int bytes_read；
unsigned char str[20]；
V. capture data of specified length in input buffer +
bytes_read = read(command_fd,str,20)；
…
return bytes_read；
}
After the verification environment receives the command transmitted through the network, the verification environment needs to return related information to the client software sending the command through a return command, and the return command comprises: return commands without data and return commands with data. The return command without data is mainly applicable to the write register operation, and the return command with data is applicable to the read register operation.
The specific function is defined as follows, wherein the function mm _ respwovaile represents a return command without data, and the function mm _ respvalue represents a return command with data:
void mm_respwovalue (char resp_value)
{
…
v. return to client a particular encoding without valid data
write(command_fd, &resp_value)；
}
void mm_respvalue (int resp_value)
{
V variable assertion
char response[8]；
bzero(response,8)
…
*((unsigned int*)( response+4)) = resp_value；
V. returning valid data of specified length to client
write(command_fd, response,8)；
}
When the simulation environment does not need to receive a command or when the client software side where the software is located is reset, the network link needs to be disconnected, and the specific function definition is as follows:
void mm_stop ()
{
…
/. closed socket link
close(commnd_fd);
close(listen_fd);
}
In a verification environment, a complete verification platform is usually built by using a UVM verification methodology. After the test case is started, the function is called in a DPI mode, the link is started, the command sent from the opposite terminal through the network is received uninterruptedly, and the bus access of the standard register is converted according to the received command. Specific examples are as follows:
v. acquiring port number ++,
uvm_cmdline_proc.get_arg_value(“+PORT”,port);
v. Start Link
mm_start(port);
V. cycle receives command
do begin
mm_getcommand(command, offset, value , opcode)
if(command =0)begin
V. open network link when receiving command 0
mm_stop();
end else if(command ==1) begin
V. performing a register write operation when the received command is 1
register_write(offset,value);
mm_respondwovalue(8'h11);
…
end
end while (command!=0)
When the verification environment receives a command sent by software through a network, the relevant information of the operation of the internal register of the chip is analyzed, and then the internal standard bus is driven through the BFM in the verification platform, so that the access to the register is realized. Furthermore, the verification environment can record all operation information simultaneously in the chip verification process, so that the software can be conveniently tracked and debugged.
In the process of realizing the software algorithm, interaction with a register inside the chip is needed, the operation is carried out by acquiring the state inside the chip in real time, and the parameters needing to be adjusted are written back to the inside of the chip. Therefore, the software algorithm needs to consider that the software algorithm is directly operated on a processor in the chip at the later stage, and can also package the operation of the read-write register into a self-defined command format in the verification stage of the early-stage chip algorithm and transmit the command to one side of the verification platform through a network so as to carry out the cooperative verification of the software algorithm and the chip as soon as possible.
As shown in fig. 2, the parsing the command specifically includes the following steps:
receiving a command;
judging whether the command is a disconnection link, if so, sending a return command with specific data to the client software, and disconnecting the link;
if not, judging whether the operation is register write operation;
if the register write operation is carried out, generating register write bus access, sending a return command to the client software, and returning to the step of receiving the command after sending the return command;
if the register is not in the write operation, judging whether the register is in the read operation;
if the read operation is the register read operation, generating register read bus access, sending a return command with data to the client software, and returning to the step of receiving the command after sending the return command;
if the read operation is not the register read operation, sending a return command with specific data to the client software, and returning to the step of receiving the command after sending the return command.
In some embodiments, in response to receiving a command sent by the client software over a network, parsing the command, and sending a return command to the client software, includes:
in response to receiving a command sent by a plurality of the client software over a network, creating a corresponding number of threads based on the client software;
and analyzing the command sent by each client software based on the corresponding thread, and sending a return command to the client software.
In this embodiment, when multiple pieces of software are executed in parallel, multiple threads are created in the verification environment for performing unified verification, which further shortens the time for chip verification.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a chip verification method. As shown in fig. 3, software is run on the client, which performs the following steps:
step S301, establishing a link based on a socket with a verification environment of a server to send a command to the verification environment through a network, wherein the command is used for accessing a register of a chip to be verified in the verification environment.
The software is operated at a client, a network communication protocol based on a socket is embedded in the bottom layer of a software algorithm in advance, when a software method operates a chip hardware register, the software and a chip verification environment establish a link relation, and then a series of commands in a custom command set are sent through a network.
And customizing a command set, packaging the access operation of the software to the internal resources of the chip into the command set, and communicating with the verification environment in a network transmission mode. When software needs to access the internal register of the chip, information such as data, address, operational characters and the like can be put into a command set and sent out through a network.
The verification environment monitors network data in real time, after receiving a corresponding data command, the network data is analyzed according to a predefined format, and effective information is forwarded to the bus function module, the bus function module can have different implementation modes according to different verification environments, but access to a register inside a chip is achieved, and meanwhile, the state of the register inside the chip is returned to one side of software through a network.
When a plurality of pieces of software are executed in parallel, multi-core access inside the chip is simulated by starting a multi-thread mode, and related software can be independently simulated and run according to respective execution modes and access resources, so that cross-platform verification of the software is realized.
The invention organically combines the algorithm verification with the chip verification through the network, does not limit the development environment and debugging tools of the software algorithm any more, realizes the cooperative verification of the software algorithm and the chip, improves the verification quality of the chip and accelerates the verification speed of the chip.
Due to the complex functions inside the chip, multiple processors need to complete different algorithm processing, and therefore the situation that multiple cores run different software simultaneously needs to be simulated. The invention can access the chip hardware resources by establishing a multi-thread mode to support multi-point concurrency. Specifically, as shown in fig. 4, the present invention provides a schematic structural diagram of performing chip verification in parallel by multithreading between client software and a verification environment. In fig. 4, software 1 and software 2 represent different software processing units, respectively, and run on respective clients, after a link is created in a verification environment, the software 1 and software 2 may be circularly waited for network link, and when any one software link succeeds, a single thread is started to perform a task of receiving a command and analyzing, thereby implementing a multi-thread task. After the command is analyzed, the access operation of the register is processed by a BFM bus function module, the BFM converts the operation of the register into standard bus access according to a bus protocol and sends the standard bus access to an interface of a chip to be verified, because different software exists, multiple tasks are performed simultaneously, and the accessed addresses are possibly different, decoding is required to be performed in the chip according to the access address, so that the software can access the corresponding module, furthermore, the decoding function can be realized by the interconnection module in fig. 4, and the module 1 and the module 2 represent different modules in the chip.
The software verification of the chip is advanced through a network communication mode, so that the verification quality under the condition that the functions of the software and the chip are tightly coupled is greatly improved. Usually, when there are some high-speed interfaces inside the chip, there will be some deviations more or less due to the influence of the production process, and these will have a serious influence on the high-speed interfaces, resulting in unstable data transmission and even some errors. Therefore, after the chips with the high-speed interfaces are produced, training and calibration are needed, software is needed to participate in the training and calibration, and proper parameters are calculated and corrected by acquiring a state register in the chip and performing algorithm calculation, so that the correctness and the stability of data transmission of the chip can be ensured. Because these software algorithms are tightly coupled with the functional design inside the chip, it is difficult to ensure the correctness of the later functions if not fully verified. According to the scheme of the invention, the chip function simulation verification stage and the software algorithm can be cooperatively and uniformly verified, and the software algorithm can be debugged on a proper platform, so that the verification speed is greatly increased, and the verification quality is improved.
When a plurality of pieces of software are executed in parallel, unified verification is carried out in a multithreading mode, the verification time is further shortened, hardware resources are fully utilized, and the correctness of the internal functions of the chip can be verified when a plurality of cores execute tasks concurrently. A lot of verification work of interaction between the chip and the software is advanced, so that the time and the cost for later debugging of the software are greatly saved.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 5, an embodiment of the present invention further provides a chip verification system 500, including:
a listening process 510, the listening process 510 configured to create a socket-based link to allow receiving commands sent by client software over a network;
a command parsing module 520, wherein the command parsing module 520 is configured to parse a command sent by the client software through a network in response to receiving the command, and send a return command to the client software;
a bus function module 530, where the bus function module 530 is configured to convert the parsed command into a physical bus access based on a bus access protocol of the chip to be verified so as to access a register of the chip to be verified.
As shown in fig. 6, the present invention provides a schematic structural diagram of another embodiment of chip verification.
The software runs on the software side of the client and is connected with the server through the network, and the verification environment runs in an EDA simulation tool installed on the server. The verification environment needs to include a monitoring process, and after the monitoring process establishes a network communication link, the monitoring process receives a command sent by the software side through the network. The command analysis module needs to split and analyze the received command set, so as to convert the received command set into contents such as read-write instructions, access addresses, data and the like of a register inside the chip, and transfer the contents to the BFM, and the BFM converts the received software instructions into real physical bus read-write access according to a bus access protocol of the piece to be tested, so as to control the operation of the internal state of the piece to be tested.
In the embodiment, the verification environment monitors the network state through the monitoring process, when a command sent by the client software is monitored, the command is analyzed through the command analysis module, and the analyzed command is converted into the physical bus access through the BMF module, so that the access of the software to the internal register of the chip to be verified is realized, the cooperative verification of the software and the chip is realized, the verification quality of the chip is improved, and the verification speed of the chip is accelerated.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 7, the embodiment of the present invention further provides a computer device 70, in which the computer device 70 comprises a processor 710 and a memory 720, the memory 720 stores a computer program 721 capable of running on the processor, and the processor 710 executes the program to perform the steps of the above method.
The memory, as a non-volatile computer-readable storage medium, may be used to store a non-volatile software program, a non-volatile computer-executable program, and modules, such as program instructions/modules corresponding to the chip verification method in the embodiments of the present application. The processor executes various functional applications and data processing of the device by running the nonvolatile software program, instructions and modules stored in the memory, that is, the chip verification method of the above-described method embodiment is realized.
The memory may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the device, and the like. Further, the memory may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, the memory optionally includes memory located remotely from the processor, and such remote memory may be coupled to the local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 8, an embodiment of the present invention further provides a computer-readable storage medium 80, and the computer-readable storage medium 80 stores a computer program 810 for executing the above method when executed by a processor.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (8)
1. A method for chip verification, wherein a verification environment is run at a server, and the following steps are performed based on the verification environment:
creating a socket-based link to allow receipt of commands sent by client software over a network;
in response to receiving a command sent by a plurality of the client software over a network, creating a corresponding number of threads based on the client software;
analyzing the command sent by each client software based on the corresponding thread, and sending a return command to the client software;
and converting the analyzed command into physical bus access to access the register of the chip to be verified based on a bus access protocol of the chip to be verified.
2. The method of claim 1, wherein parsing the commands sent by each of the client software based on the corresponding thread and sending a return command to the client software comprises:
judging whether the command sent by the client software is a broken link or not in a corresponding thread;
if the command is not the disconnection link, judging whether the command is the write operation of the register;
and if the command is write operation on the register, generating register write bus access and sending a return command to the client software.
3. The method of claim 2, further comprising:
if the command is not the write operation of the register, judging whether the command is the read operation of the register;
and if the command is read operation of the register, generating register read bus access, and sending a return command with data to the client software.
4. The method of claim 3, further comprising:
and if the command is not the read operation of the register, sending a return command with data to the client software.
5. The method of claim 2, further comprising:
and if the command is a disconnection link, sending a return command with data to the client software, and disconnecting the link.
6. A chip verification system, comprising:
a listening process configured to create a socket-based link to allow receipt of commands sent by client software over a network;
a command parsing module configured to create a corresponding number of threads based on a plurality of client software in response to receiving commands sent by the client software over a network; the command analysis model is also configured to analyze the command sent by each client software based on the corresponding thread and send a return command to the client software;
the bus function module is configured to convert the analyzed command into physical bus access to access a register of the chip to be verified based on a bus access protocol of the chip to be verified.
7. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of the method according to any of claims 1 to 5.
8. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.
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| CN114417761B (en) * | 2022-03-30 | 2022-07-22 | 新华三半导体技术有限公司 | Chip verification method, device and system, control server and medium |
| CN116776783B (en) * | 2023-05-04 | 2024-07-09 | 合芯科技有限公司 | White box verification method, system, equipment and medium for analog register read-write |
| CN117787155B (en) * | 2023-12-28 | 2024-08-20 | 上海合芯数字科技有限公司 | Chip testability code dynamic simulation test system and test method |
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