CN105158681A - Radio frequency identification reader chip verification method and system - Google Patents
Radio frequency identification reader chip verification method and system Download PDFInfo
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- CN105158681A CN105158681A CN201510486530.6A CN201510486530A CN105158681A CN 105158681 A CN105158681 A CN 105158681A CN 201510486530 A CN201510486530 A CN 201510486530A CN 105158681 A CN105158681 A CN 105158681A
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Abstract
Embodiments of the invention disclose a radio frequency identification reader chip verification method and system. The method comprises steps of separately verifying modules of a radio frequency identification reader chip to obtain separate verification results of each module; connecting all the modules, and performing module joint debugging verification of all the modules to obtain a system-level verification result; placing all the modules in a hardware platform for verification, simulating corresponding transmission flows according to practical application scenes, and developing corresponding hardware platforms; automatically generating testing data and performing simulation verification of all the modules. According to the invention, automatic verification of the chip is carried out in the design stage of the RFID reader chip and after the design; under a precondition of using lots of testing data, manpower cost is saved, the chip verification time is shortened, the effectiveness of chip verification is improved, and the stability and reliability of the chip is improved.
Description
Technical field
The present invention relates to radio-frequency (RF) identification (RadioFrequencyIdentification, RFID) technical field, particularly relate to a kind of verification method and system of radio-frequency identification reader/writer chip.
Background technology
With bar code, magnetic card, contact integrated circuit card (IntegratedCircuitCard, IC-card) etc. other automatic identification technology compare, namely RFID technique have identifying need not manual intervention, can identify that multiple target, information storage are large, can work in the advantages such as various rugged surroundings simultaneously.Therefore, RFID technique has been widely used in the fields such as fixed capital management, production line automation, animal and vehicle identification, highway toll, gate control system, storage, commodity counterfeit prevention, airline baggage management, container management.
The all compatible various communications protocols of chip, coded system, decoding process, traffic rate, modulation /demodulation, anti-collision algorithms, CRC check algorithm etc. of major part rfid interrogator, easily there is various unthinkable boundary problem in the circuit design of complexity like this, affects the reliability of chip.
After chip design stage and complete design, all to do a large amount of checking work, guarantee stability and the reliability of chip operation, avoid chip run duration to go wrong.Because the chip design cycle is longer, need the half a year above time from being designed into throwing sheet, only chip manufacturing will spend about 3 months time, if chip manufacturing is by the time complete, test is pinpointed the problems, and so redesigns, and needs to spend the more time, has a strong impact on chip Time To Market.
In order to ensure the correctness of chip, completeness and security, the process verified more must be paid attention to.If amount of test data is too little, be not enough to find out potential problem, thus need to use a large amount of data to be verified.But, because data volume is large, adopt the right method of manpower comparing not conform to reality.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, the invention provides a kind of verification method and system of radio-frequency identification reader/writer chip, the proving time of rfid interrogator chip can be saved, improve the validity of chip checking, improve stability and the reliability of chip operation.
In order to solve the problem, the present invention proposes a kind of verification method of radio-frequency identification reader/writer chip, described method comprises:
Each module of radio frequency identification read write line chip is verified separately, obtains the independent the result of each module;
Each module is connected, module uniting and adjustment checking is carried out to all modules, obtain whole-system verification result;
All modules are put in hardware platform checking, simulate corresponding transfer process according to the application scenarios of reality, develop corresponding hardware platform;
Automatic Data Generation Test, carries out simulating, verifying to all modules.
Preferably, described automatic Data Generation Test, carries out the step of simulating, verifying, comprising to all modules:
After the digital circuit of radio-frequency identification reader/writer chip is passed through logic synthesis, programming is in field programmable gate array (Field-ProgrammableGateArray, FPGA) development board;
Communicate with FPGA development board, obtain the output signal of FPGA development board;
Compare output signal and the Expected Response output signal of FPGA development board, obtain the result.
Correspondingly, the present invention also provides a kind of verification system of radio-frequency identification reader/writer chip, and described system comprises:
Independent authentication module, each module for radio frequency identification read write line chip is verified separately, obtains the independent the result of each module;
Whole-system verification module, for each module being connected, carries out module uniting and adjustment checking to all modules, obtains whole-system verification result;
Hardware Verification Platform, for all modules being put in hardware platform checking, simulating corresponding transfer process according to the application scenarios of reality, developing corresponding hardware platform; Automatic Data Generation Test, carries out simulating, verifying to all modules.
Preferably, described Hardware Verification Platform comprises:
FPGA development board, for by the digital circuit of radio-frequency identification reader/writer chip by programming after logic synthesis in FPGA development board;
Jtag interface, for communicating with FPGA development board, obtains the output signal of FPGA development board;
Comparative result module, for comparing output signal and the Expected Response output signal of FPGA development board, obtains the result.
Preferably, described Hardware Verification Platform also comprises:
Vector generation module, for generation of test and excitation signal.
Preferably, described Hardware Verification Platform also comprises:
Expected Response generation module, outputs signal for generation of Expected Response.
In embodiments of the present invention, after rfid interrogator chip design stage and complete design, automatic Verification is carried out to chip, can under the prerequisite using a large amount of test data, save labour turnover, shorten the proving time of chip, improve the validity of chip checking, improve stability and the reliability of chip operation.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic flow sheet of the verification method of the radio-frequency identification reader/writer chip of the embodiment of the present invention;
Fig. 2 is the schematic flow sheet in the embodiment of the present invention, all modules being carried out to simulating, verifying;
Fig. 3 is the schematic diagram of software verification platform in the embodiment of the present invention;
Fig. 4 is the framework composition schematic diagram of the verification system of the radio-frequency identification reader/writer chip of the embodiment of the present invention;
Fig. 5 is the structure composition schematic diagram of Hardware Verification Platform in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 1 is the schematic flow sheet of the verification method of the radio-frequency identification reader/writer chip of the embodiment of the present invention, and as shown in Figure 1, the method comprises:
S101, each module of radio frequency identification read write line chip is verified separately, obtains the independent the result of each module;
S102, connects each module, carries out module uniting and adjustment checking to all modules, obtains whole-system verification result;
S103, is put in hardware platform checking, simulates corresponding transfer process, develop corresponding hardware platform according to the application scenarios of reality by all modules;
S104, automatic Data Generation Test, carries out simulating, verifying to all modules.
As shown in Figure 2, S104 comprises further:
S1041, after the digital circuit of radio-frequency identification reader/writer chip is passed through logic synthesis, programming is in FPGA development board;
S1042, communicates with FPGA development board, obtains the output signal of FPGA development board;
S1043, compares output signal and the Expected Response output signal of FPGA development board, obtains the result.
In embodiments of the present invention, in the chip design starting stage, adopt the independent verification method of module level, verify the correctness of each functions of modules; Module level has designed, and is linked together by modules, and start whole-system verification, i.e. module uniting and adjustment, now should generate a large amount of excited data verification system level function.
After whole-system verification completes, this system should be put into hardware platform checking, according to the application scenarios of reality, simulate corresponding transaction flow, develop corresponding hardware platform, automatically generate a large amount of test data, scan each arbitrary boundary conditions, strengthen function coverage.Finally this system code is carried out logic synthesis, placement-and-routing, and simulating, verifying is carried out to it.
Software verification platform as shown in Figure 3 comprises that namely input pattern encourages, upper computer software, desired output, output response, contrast and north side design object (DUT).
Namely input pattern encourages, and inputs in platform by the signaling interface write with Verilog, and start verification platform and carry out functional verification, the result of calculating is obtained by Verilog code, contrasts, export comparing result simultaneously with the output expected.Upper computer software is an interface, can select different excitations by interface.
Tested design object is exactly identifying object of the present invention, i.e. rfid interrogator chip digital circuit, writes with Verilog code, and verification platform only needs the top layer interface of call number circuit, and provides corresponding excitation and can verify it.
Because the data of digital circuit process can not be each all the same, the data of carrying out encryption and decryption can be the arbitrary datas in field of definition.Therefore one or two data simulation is verified the correctness that can not ensure this safety circuit, but need to be tested by mass data, only have selective data targetedly in a large number to have passed test, just can think that the function of chip design is correct.
Equally also can carry out mass data test by the method for software verification, but software verification requires a great deal of time, when test data set is very large, the speed of software verification becomes bottleneck undoubtedly.Hardware verification is then different, and it can complete the most multidata test with the shortest time.Therefore combined with hardware of the present invention verifies this step, assists checking work by its high efficiency.Meanwhile, carry out location of mistake because hardware verification is bad, when hardware verification go out design wrong time, software verification can be re-started with this input vector, to carry out location of mistake, facilitate Amending design.Measurand (DUT) now is also rfid interrogator chip digital circuit, but this circuit by programming after logic synthesis in FPGA development board, owing to having possessed real logical time delay and sequential, can chip application scene that is virtually reality like reality.
Correspondingly, the embodiment of the present invention also provides a kind of verification system of radio-frequency identification reader/writer chip, and as shown in Figure 4, this system comprises:
Independent authentication module 40, each module for radio frequency identification read write line chip is verified separately, obtains the independent the result of each module;
Whole-system verification module 41, for each module being connected, carries out module uniting and adjustment checking to all modules, obtains whole-system verification result;
Hardware Verification Platform 42, for all modules being put in hardware platform checking, simulating corresponding transfer process according to the application scenarios of reality, developing corresponding hardware platform; Automatic Data Generation Test, carries out simulating, verifying to all modules.
Further, as shown in Figure 5, Hardware Verification Platform comprises:
FPGA development board, for by the digital circuit of radio-frequency identification reader/writer chip by programming after logic synthesis in FPGA development board;
Jtag interface, for communicating with FPGA development board, obtains the output signal of FPGA development board;
Comparative result module, for comparing output signal and the Expected Response output signal of FPGA development board, obtains the result.
Vector generation module, for generation of test and excitation signal.
Expected Response generation module, outputs signal for generation of Expected Response.
Test and excitation is produced by vector generation module, is communicated with FPGA development board by quartus2 software, by the output of the output and Expected Response generation module of comparing FPGA development board, can obtain comparing result like this, conveniently pinpoint the problems.
By carrying out reading and writing data to FPGA, sending to FPGA to carry out encryption and decryption operation data before treatment, and sending its result back to PC, by software, this result and desired output being contrasted, circulation checking is carried out to obtain the result to mass data.
In embodiments of the present invention, after rfid interrogator chip design stage and complete design, automatic Verification is carried out to chip, can under the prerequisite using a large amount of test data, save labour turnover, shorten the proving time of chip, improve the validity of chip checking, improve stability and the reliability of chip operation.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment is that the hardware that can carry out instruction relevant by program has come, this program can be stored in a computer-readable recording medium, storage medium can comprise: ROM (read-only memory) (ROM, ReadOnlyMemory), random access memory (RAM, RandomAccessMemory), disk or CD etc.
In addition, above the verification method of the radio-frequency identification reader/writer chip that the embodiment of the present invention provides and system are described in detail, apply specific case herein to set forth principle of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (6)
1. a verification method for radio-frequency identification reader/writer chip, is characterized in that, described method comprises:
Each module of radio frequency identification read write line chip is verified separately, obtains the independent the result of each module;
Each module is connected, module uniting and adjustment checking is carried out to all modules, obtain whole-system verification result;
All modules are put in hardware platform checking, simulate corresponding transfer process according to the application scenarios of reality, develop corresponding hardware platform;
Automatic Data Generation Test, carries out simulating, verifying to all modules.
2. the verification method of radio-frequency identification reader/writer chip as claimed in claim 1, is characterized in that described automatic Data Generation Test carries out the step of simulating, verifying, comprising to all modules:
After the digital circuit of radio-frequency identification reader/writer chip is passed through logic synthesis, programming is in FPGA development board;
Communicate with FPGA development board, obtain the output signal of FPGA development board;
Compare output signal and the Expected Response output signal of FPGA development board, obtain the result.
3. a verification system for radio-frequency identification reader/writer chip, is characterized in that, described system comprises:
Independent authentication module, each module for radio frequency identification read write line chip is verified separately, obtains the independent the result of each module;
Whole-system verification module, for each module being connected, carries out module uniting and adjustment checking to all modules, obtains whole-system verification result;
Hardware Verification Platform, for all modules being put in hardware platform checking, simulating corresponding transfer process according to the application scenarios of reality, developing corresponding hardware platform; Automatic Data Generation Test, carries out simulating, verifying to all modules.
4. the verification system of radio-frequency identification reader/writer chip as claimed in claim 3, it is characterized in that, described Hardware Verification Platform comprises:
FPGA development board, for by the digital circuit of radio-frequency identification reader/writer chip by programming after logic synthesis in FPGA development board;
Jtag interface, for communicating with FPGA development board, obtains the output signal of FPGA development board;
Comparative result module, for comparing output signal and the Expected Response output signal of FPGA development board, obtains the result.
5. the verification system of radio-frequency identification reader/writer chip as claimed in claim 4, it is characterized in that, described Hardware Verification Platform also comprises:
Vector generation module, for generation of test and excitation signal.
6. the verification system of radio-frequency identification reader/writer chip as claimed in claim 4, it is characterized in that, described Hardware Verification Platform also comprises:
Expected Response generation module, outputs signal for generation of Expected Response.
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| CN107885181A (en) * | 2016-09-30 | 2018-04-06 | 上海复旦微电子集团股份有限公司 | The test system of DSP unit in field programmable gate array chip |
| CN109144668A (en) * | 2018-08-06 | 2019-01-04 | 华大半导体有限公司 | RFID emulates use-case implementation method and device |
| CN110276106A (en) * | 2019-05-24 | 2019-09-24 | 杰创智能科技股份有限公司 | A kind of detection circuit of the radio frequency SOC chip based on numerical model analysis emulation platform |
| CN111859832A (en) * | 2020-07-16 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | Chip simulation verification method and device and related equipment |
| CN112416686A (en) * | 2020-12-02 | 2021-02-26 | 海光信息技术股份有限公司 | Chip verification method, chip verification device and storage medium |
| CN112465084A (en) * | 2020-11-25 | 2021-03-09 | 广州智慧城市发展研究院 | Verification system for reader-writer |
| CN112699695A (en) * | 2021-03-23 | 2021-04-23 | 广州智慧城市发展研究院 | RFID reader-writer software verification device and method and electronic equipment |
| CN113704043A (en) * | 2021-08-30 | 2021-11-26 | 地平线(上海)人工智能技术有限公司 | Chip function verification method and device, readable storage medium and electronic equipment |
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| CN106095675B (en) * | 2016-06-07 | 2018-12-14 | 无锡键桥电子科技有限公司 | A kind of reusable verifying system of EDA and FPGA for passive label chip |
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| CN112465084B (en) * | 2020-11-25 | 2024-03-01 | 广州智慧城市发展研究院 | Verification system for reader-writer |
| CN112416686A (en) * | 2020-12-02 | 2021-02-26 | 海光信息技术股份有限公司 | Chip verification method, chip verification device and storage medium |
| CN112699695B (en) * | 2021-03-23 | 2021-07-20 | 广州智慧城市发展研究院 | RFID reader-writer software verification device and method and electronic equipment |
| CN112699695A (en) * | 2021-03-23 | 2021-04-23 | 广州智慧城市发展研究院 | RFID reader-writer software verification device and method and electronic equipment |
| CN113704043A (en) * | 2021-08-30 | 2021-11-26 | 地平线(上海)人工智能技术有限公司 | Chip function verification method and device, readable storage medium and electronic equipment |
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Application publication date: 20151216 |