CN103235749A - FPGA-based sensor network SoC proto verification platform - Google Patents

FPGA-based sensor network SoC proto verification platform Download PDF

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Publication number
CN103235749A
CN103235749A CN2013101025868A CN201310102586A CN103235749A CN 103235749 A CN103235749 A CN 103235749A CN 2013101025868 A CN2013101025868 A CN 2013101025868A CN 201310102586 A CN201310102586 A CN 201310102586A CN 103235749 A CN103235749 A CN 103235749A
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interface
daughter board
fpga
sensor
sensor network
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虞致国
顾晓峰
胡峥
张建国
邵宇
王晓涧
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Jiangnan University
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Jiangnan University
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Abstract

The invention discloses an FPGA (Field Programmable Gate Array) sensor network SoC (System on Chip) proto verification platform. The sensor network SoC proto verification platform comprises a PC upper computer, an FPGA motherboard and a pluggable daughterboard, wherein the PC upper computer is connected with the FPGA motherboard; the FPGA motherboard is provided with a daughterboard interface, an FPGA clip, an ARM7 testing clip and other peripheral circuits; the daughterboard interface comprises an ADC (Analog to Digital Converter) daughterboard interface, a wireless transmit-receive daughterboard interface, an analog sensor interface, an intelligent sensor interface and an expansion interface; and the pluggable daughterboard comprises a multi-channel ADC daughterboard, a wireless transmit-receive daughterboard, an analog sensor interface daughterboard and an intelligent sensor interface daughterboard. According to the invention, the motherboard and the pluggable daughterboard are adopted by the sensor network SoC proto verification platform, so that verification of a sensor network SoC clip based on ARM7 core can be accomplished with flexibility and universality to a certain degree.

Description

A kind of sensor network SoC prototype verification platform based on FPGA
Technical field
The invention belongs to technical field of integrated circuits, relate to the prototype verification platform of a kind of sensor network SoC, be specifically related to the reusable verification platform of a kind of sensor network SoC based on FPGA.
Background technology
Along with the development of integrated circuit (IC) design technology, the System on Chip/SoC design epoch have been entered at present.System on Chip/SoC is also referred to as SoC (System-on-Chip), is function and performance from total system, and design and verification method with software and hardware utilize IP reuse, realizes complicated function at a chip.
In the design process of SoC, be verified as extremely important step, its objective is the consistance that will guarantee design data and design specifications.Functional verification will account for the workload of 50-80% in the integrated circuit (IC) design process.SoC checking based on the prototype verification platform is one of verification method of a kind of main flow.The chip prototype can adopt soft prototype or virtual prototype, is about to design object to be verified and adopts the form of software to represent.The emulation degree of this method is very high, but because SoC hardware module number is numerous, embedded software is complicated, can become very slow based on the checking of soft prototype or virtual prototype, and debugging software is extremely inconvenient.Along with the fast development of FPGA technology, its speed, scale constantly increase, and cost constantly reduces, and make with it to be that hardware carrier carries out the chip prototype verification and becomes a kind of important method.Thereby in the System on Chip/SoC exploitation in earlier stage, utilize FPGA that the platform of an emulation as early as possible, verification system chip is provided, move the software and hardware codes that collaborative design is produced in real-time mode, problem in the discovery system integration process as early as possible, thus reach the tempo of development of accelerating chip, the purpose that is provided as power.
Fast development along with technology such as embedded system, radio communication, networks, have the sensor of perception, calculating and wireless communication ability and caused people's very big concern by the wireless sensor network that it constitutes, wireless sensor network SoC demand low-cost, miniaturization is also more and more urgent.
Advantages such as ARM7 nuclear is the IP kernel of a maturation of ARM company, and it is high to have stability based on the SoC of this IP kernel, and development ability is strong.Be designed to power in order to accelerate the design rate based on the wireless sensor network SoC of ARM7 nuclear, to improve, press for the prototype verification platform of sensor network SoC.
Summary of the invention
The present invention is slow in view of the SoC verifying speed based on soft prototype or virtual prototype, the widespread use of examining in view of ARM7 simultaneously, provide a kind of towards ARM7, based on the prototype verification platform of the sensor network SoC of FPGA, for improving sensor network SoC flow success ratio, accelerate the exploitation of sensor network SoC, the cost of development that reduces sensor network SoC application system provides possibility.
The present invention is achieved through the following technical solutions:
A kind of sensor network SoC prototype verification platform based on FPGA is provided, comprises PC host computer, FPGA motherboard and plug type daughter board; The FPGA motherboard is connected with the PC host computer; Described FPGA plate is provided with daughter board interface, fpga chip, ARM7 test chip and other peripheral circuits; Described daughter board interface comprises ADC daughter board interface, wireless receiving and dispatching daughter board interface, analog sensor interface, intelligence sensor interface, expansion interface; Described plug type daughter board comprises hyperchannel ADC daughter board, wireless receiving and dispatching daughter board, analog sensor interface daughter board, intelligence sensor interface daughter board; Described hyperchannel ADC daughter board is inserted in the ADC daughter board interface, the wireless receiving and dispatching daughter board is inserted in the wireless receiving and dispatching daughter board interface, the simulated sensor data daughter board is inserted in the analog sensor interface, and intelligence sensor data daughter board is inserted in the intelligence sensor interface.
Described FPGA motherboard Core Feature is the logical model of analog sensor network SoC chip, and sensor network SoC prototype is diagnosed debugging, and provides the rich in natural resources interface for the interconnection and interflow of each daughter board.
Described wireless receiving and dispatching daughter board is used for the radio receiving transmitting module of simulation, verificating sensor network SoC, comprises wireless ZigBee transceiving chip, clock circuit, antenna, power circuit.
Described analog sensor interface daughter board is used for the analog sensor interface of simulation, verificating sensor network SoC, the data of the compatible multiple analog sensor of energy insert, adopt modulate circuits such as I/V conversion, amplification, filtering that the simulating signal of sensor input is done corresponding conversion, and pass to hyperchannel ADC daughter board and carry out digital-to-analog conversion.
Described intelligence sensor interface daughter board be used for simulation, verificating sensor network SoC the intelligence sensor interface, can insert the intelligence sensor signal of CAN interface, SPI interface, IIC interface and UART interface.
Described expansion interface is used for resource expansion and the debugging of prototype verification platform, and the I/O mouth of having drawn a large amount of FPGA on the FPGA motherboard is used for the function expansion.
The verification method of the prototype verification platform of above-mentioned platform is as follows
1) module level checking
The correctness of each module of checking hardware platform guarantees that each module of sensor network SoC is working properly, interface meets the sequential requirement.
2) system-level checking
By loading kernel file that compiling produces in the storer of prototype verification system, CPU just can read-write memory operation system, further carries out the prototype verification of all application programs of sensor network SoC.
Owing to adopted above-mentioned technical scheme, the present invention compared with prior art has following advantage and good effect: the present invention adds the prototype verification platform of the sensing net SoC that can plug daughter board for adopting motherboard, has certain dirigibility, versatility.
Description of drawings
Fig. 1 is the hardware configuration synoptic diagram of a kind of sensor network SoC prototype verification platform based on FPGA provided by the invention.
Embodiment
The invention will be further described below in conjunction with concrete accompanying drawing and case study on implementation.
A kind of sensor network SoC prototype verification platform based on FPGA is provided, as shown in Figure 1, comprises PC host computer, FPGA motherboard and plug type daughter board; The FPGA motherboard is connected with the PC host computer; The plug type daughter board comprises hyperchannel ADC daughter board, wireless receiving and dispatching daughter board, analog sensor interface daughter board, intelligence sensor interface daughter board, hyperchannel ADC daughter board and wireless receiving and dispatching daughter board.
Comprise two jumbo FPGA, ARM7 test chip, Flash storer, daughter board interface, power management and peripheral circuit on the described FPGA motherboard, its Core Feature is that the checking for sensor network SoC provides a carrier, and in order to the logical model of the sensor network SoC of simulation except ARM7 nuclear, storer, analog module part, and sensor network SoC debugged, diagnoses.
FPGA in the described motherboard adopts the Spartan-6 series of products XC6SLX150 of a slice Xilinx, the Spartan-6 series of products XC6SLX150T of a slice Xilinx; XC6SLX150 is used as the logical model of checking SoC chip, and XC6SLX150T is used as connection and the diagnosis of prototype verification platform.
Described wireless receiving and dispatching daughter board comprises a slice MC13202, the integrated 2.4GHz radio-frequency (RF) transceiver of this chip internal, IEEE802.15.4MAC hardware accelerator, adopt the SPI interface to PERCOM peripheral communication, in order to PHY/MAC consensus standard among the 802.15.4 in simulation, the verificating sensor network SoC chip.
Described analog sensor interface daughter board is mainly used to simulate, the simulated sensor data acquisition interface of verificating sensor network SoC; This daughter board is gathered the physical message that outside temperature, pressure, light intensity and magnetic field etc. need collection, shaping by integrating circuit, amplifying circuit is handled, above-mentioned physical quantity is converted into the voltage range that system sensor network SoC can accept, for the A/D module samples.
Described intelligence sensor interface daughter board is realized the conversion of non-CMOS level such as RS232, RS485, RS422, the CAN bus of intelligence sensor interface and CMOS level, thereby be convenient to the data of sensor are connected with sensor network SoC prototype verification platform, and the intelligence sensor Interface design is carried out functional verification.
Described hyperchannel ADC daughter board comprises a slice AD7858, and this chip is 12 ADC of eight inputs, adopts the SPI interface to PERCOM peripheral communication, in order to realize the model of embedded ADC, realizes the analog to digital conversion of analog sensor signal.
Below motherboard and each daughter board are specifically described.
Comprise two jumbo FPGA, ARM7 test chip, Flash storer, daughter board interface, serial communication interface, FPGA debugging jtag interface, SoC debugging jtag interface, clock and reseting module, electric power management circuit on the described FPGA motherboard, its structure is shown in Fig. 1 institute.A slice FPGA XC6SLX150 in the described FPGA motherboard is used for the Digital Logic of simulation SoC chip, comprises static memory, clock-reset module in on-chip bus, peripheral hardware, the sheet; SoC chip logic model is write with hardware description language (HDL), utilizes the process of PC host computer comprehensive, downloads among the FPGA after the placement-and-routing and realize; Model can not adopt the plug type daughter board to realize in the SoC chip with the analog peripheral that FPGA realizes.A slice FPGAXC6SLX150T in the described FPGA motherboard is mainly used in realizing to designing supervision, the diagnosis of internal node, in the operational process, the signal value of monitoring point is deposited into the SRAM that is attached thereto, PC can read signal value among the SRAM by the PCI-E mode, thereby realized that software reads the data in the prototype verification platform operational process, strengthen the diagnosis capability of prototype, can also directly signal have been imported logic analyser analysis in addition.Shown on the PPGA motherboard CPU nuclear prototype adopt the test chip of ARM company, the hardware behavior of ARM7 kernel that is virtually reality like reality; Because the test chip of ARM CPU nuclear has ICE artificial debugging interface, so also can become relatively easy for the debugging of software.Flash storer on the described FPGA motherboard comprises the parallel Flash memory chip of a slice, a slice based on the Flash memory chip of SPI interface, is used for the procedure stores of FLASH storer of checking and operation, data storage function.The serial communication interface of described FPGA motherboard is one group of external serial line interface, comprises IIC, SPI, UART interface, realizes the functional verification of the serial line interface of SoC; FPGA debugging jtag interface on the described FPGA motherboard is a JTAG debug port, is used for download and the function debugging of the configuration data on the FPGA Debugging; SoC debugging jtag interface on the described FPGA motherboard is a JTAG debug port, is used for the jtag interface function of verificating sensor network SoC chip, realizes that debugging, the program in the storer of CPU nuclear downloaded and read.
Described radio frequency daughter board comprises a slice MC13202, clock circuit, antenna, one group of motherboard interface.Described motherboard interface is the interface of one group of 2*10pin, and this interface comprises power supply, resets, SPI, interruption and state indication.Resetting in the interface of described radio frequency daughter board, SPI, interruption and state indication link to each other with FPGA on the FPGA motherboard, and in order to the radio frequency daughter board with obtain the internal register value, realization is to the control of radio frequency daughter board.
Described analog sensor interface daughter board is considered the diversity of collection in worksite signal and the difference of various sensor output signals, and sensor network SoC prototype verification platform receives following several sensor output signals: millivolt magnitude voltage signals input channel; 4-20mA current signal input channel; 1-5V voltage signal input channel; A cell voltage input signal channel makes things convenient for the detection system chip.Described analog sensor interface daughter board has one group of motherboard interface 2*10pin, and this interface comprises power supply, simulating signal input, simulating signal output, digital control interface (being used for amplifier control).The input of simulating signal in the interface of described analog sensor interface daughter board links to each other with the sensor signal source, simulating signal export link to each other with the analog input of hyperchannel ADC daughter board, digital control interface links to each other with FPGA on the FPGA motherboard.
Described intelligence sensor interface daughter board is realized the level conversion of the intelligence sensor of RS232, RS485, RS422, CAN bus.Described intelligence sensor daughter board comprises a slice MAX13223E, a slice MAX14841E, a slice PCA82C250; MAX13223E realizes the conversion of RS232 and UART level, and MAX14841E realizes the conversion of RS485/RS422 and UART level, and PCA82C250 realizes the physical interface of CAN bus.Described intelligence sensor interface daughter board has one group of motherboard interface 2*20pin, and this interface comprises the input and output after power supply, RS232/RS485/RS422/CAN input and output, the RS232/RS485/RS422/CAN level conversion.The RS232/RS485/RS422/CAN signal input and output of described intelligence sensor interface daughter board link to each other with external sensor, the input and output after the RS232/RS485/RS422/CAN level conversion link to each other with FPGA on the FPGA motherboard.
Described hyperchannel ADC daughter board comprises a slice AD7858, clock, electric power management circuit, one group of motherboard interface.Described motherboard interface is the interface of one group of 2*10pin, comprises power supply, SPI interface, multichannel analog input, control and state indication.FPGA on the FPGA motherboard disposes AD7858 and obtains the internal register value by the SPI interface, starts, stops ADC by control and state indication interface.
The verification method of described sensor network SoC prototype verification platform based on FPGA is as follows:
1) module level checking
Each module of sensor network SoC is applied excitation, and the correctness of each module of checking hardware platform guarantees that each module of sensor network SoC is working properly, interface meets the sequential requirement; During the authentication module function, adopt the ARM7 test chip to carry out the checking of accumulator system earlier, after memory verification finishes, can carry out the instruction-level checking with small routine at each peripheral hardware.Utilize compiled program to be loaded into storer, working procedure is observed the data transmission situation between CPU, storer and the peripheral hardware three, thus function and the performance of checking peripheral hardware.
2) system-level checking
After loading kernel file that compiling the produces storer to the prototype verification platform FPGA motherboard, ARM7 test chip on the FPGA motherboard just can read-write memory operation system, further carries out the prototype verification of all application programs of sensor network SoC; When carrying out system-level checking, the software debugging environment adopts the RealView software of ARM company to carry out.
Explanation is at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although with reference to preferred embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from aim and the scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.

Claims (2)

1. the sensor network SoC prototype verification platform based on FPGA comprises PC host computer, FPGA motherboard and plug type daughter board; Described PC host computer is connected with described FPGA motherboard; Described FPGA plate is provided with daughter board interface, fpga chip, ARM7 test chip and FPGA plate peripheral circuit; Described daughter board interface comprises ADC daughter board interface, wireless receiving and dispatching daughter board interface, analog sensor interface, intelligence sensor interface, expansion interface; Described plug type daughter board comprises hyperchannel ADC daughter board, wireless receiving and dispatching daughter board, analog sensor interface daughter board, intelligence sensor interface daughter board; Described hyperchannel ADC daughter board is inserted in the ADC daughter board interface, the wireless receiving and dispatching daughter board is inserted in the wireless receiving and dispatching daughter board interface, the simulated sensor data daughter board is inserted in the analog sensor interface, intelligence sensor data daughter board is inserted in the intelligence sensor interface;
Described FPGA motherboard is used for the logical model of analog sensor network SoC chip, and sensor network SoC prototype is diagnosed debugging, and provides the rich in natural resources interface for the interconnection and interflow of each daughter board;
Described wireless receiving and dispatching daughter board is used for the radio receiving transmitting module of simulation, verificating sensor network SoC, and it comprises wireless ZigBee transceiving chip, clock circuit, antenna, power circuit;
Described analog sensor interface daughter board is used for the analog sensor interface of simulation, verificating sensor network SoC, the data of its compatible multiple analog sensor insert, and by I/V conversion, amplification, filtering modulate circuit the simulating signal of sensor input is done corresponding conversion, and pass to hyperchannel ADC daughter board and carry out analog to digital conversion;
Described intelligence sensor interface daughter board is used for the intelligence sensor interface of simulation, verificating sensor network SoC, and it inserts the intelligence sensor signal based on CAN interface, SPI interface, IIC interface and UART interface;
Described expansion interface is used for resource expansion and the debugging of prototype verification platform, draws the I/O mouth of a large amount of FPGA on the described FPGA motherboard to be used for the function expansion.
2. a verification method that is used for the sensor network SoC prototype verification platform based on FPGA as claimed in claim 1 is characterized in that, comprising:
(1) module level checking applies excitation to each module of sensor network SoC, and the correctness of each module of checking hardware platform guarantees that each module of sensor network SoC is working properly, interface meets the sequential requirement;
(2) system-level checking, by loading kernel file that compiling produces in the storer of prototype verification system, CPU is read-write memory operation system, further carries out the prototype verification of all application programs of sensor network SoC.
CN2013101025868A 2013-03-26 2013-03-26 FPGA-based sensor network SoC proto verification platform Pending CN103235749A (en)

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Application publication date: 20130807