CN101377795A - SOC chip logical verification method special for industry portable terminal - Google Patents
SOC chip logical verification method special for industry portable terminal Download PDFInfo
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- CN101377795A CN101377795A CNA2008101398788A CN200810139878A CN101377795A CN 101377795 A CN101377795 A CN 101377795A CN A2008101398788 A CNA2008101398788 A CN A2008101398788A CN 200810139878 A CN200810139878 A CN 200810139878A CN 101377795 A CN101377795 A CN 101377795A
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000012795 verification Methods 0.000 title claims abstract description 16
- 230000006870 function Effects 0.000 claims description 14
- 230000000977 initiatory effect Effects 0.000 claims description 3
- 238000004088 simulation Methods 0.000 claims description 3
- LHMQDVIHBXWNII-UHFFFAOYSA-N 3-amino-4-methoxy-n-phenylbenzamide Chemical compound C1=C(N)C(OC)=CC=C1C(=O)NC1=CC=CC=C1 LHMQDVIHBXWNII-UHFFFAOYSA-N 0.000 claims description 2
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Abstract
The invention provides a special SOC chip logic verification system for an industrial portable terminal. In the SOC chip logic verification method, a field programmable gate array FPGA is used for establishing a special SOC chip system for the industrial portable terminal. The system comprises a software platform and a hardware platform. The hardware platform comprises a chip logic verification model with the FPGA as the carrier of the model, various functional modules and interface modules thereof. The functional modules and the interface modules thereof are connected with the chip logic verification model. The software platform is used for configuration of the chip logic verification model, the functional modules and the interface modules thereof and processing the related data, and inputting signals to the interface modules; the incoming signals of the chip logic verification model are generated through each functional module; control signals over software are generated through the chip logic verification model; the signals are converted into software display scalar quantities through each of the functional modules and the interface modules thereof.
Description
Technical field
This patent relates to a kind of integrated circuit (IC) design field, the logic verification method of a kind of specifically server safe monitoring management SOC (System On Chip, SOC (system on a chip)) chip.
Background technology
Along with the development of microelectric technique, the integrated level of chip is more and more higher, and the design of SOC chip is used more and more general, but its checking and test job become increasingly complex.
Any a chip all will pass through algorithm design, system design, RTL design, allocation plan and comprehensive, layout, connect up, authenticates to the process of the such complexity of flow, verifies that wherein this step is full of in all steps.Therefore, we can say that checking is a most important parts in the chip production process.
The logic checking of chip passed through application-specific integrated circuit ASIC more in the past.Because the ASIC function singleness, reusable must not cause the raising greatly of R﹠D costs.And the appearance of on-site programmable gate array FPGA has then improved ASIC function singleness, the shortcoming of reusable not, makes chip development flow process flexible and convenient more.
Summary of the invention
The objective of the invention is logic verification method, make in this way, can improve SOC chip design performance, shorten the construction cycle of SOC chip for the special-purpose SOC chip of a kind of industry portable terminal.
Method of the present invention is to utilize on-site programmable gate array FPGA to build the special-purpose SOC chip system of an industry portable terminal, and this system comprises software platform and hardware platform.Hardware platform comprises the chip logic checking model, does carrier, types of functionality module and the interface module thereof of model by FPGA, and wherein functional module and interface module thereof link to each other with the chip logic checking model.Software platform is used for realizing the configuration of chip logic checking model, functional module and interface module thereof and related data are handled, and signal is input to interface module, produce the input signal of chip logic checking model by each functional module, by the control signal of chip logic checking model generation, be converted into software by each functional module and interface module thereof and show scalar software.
Concrete verification step is as follows:
(1) describes the chip logic checking model by hardware description language, make it meet SOC chip logic function;
(2) software platform is configured on-site programmable gate array FPGA by functional module and interface thereof, and the result of configuration makes on-site programmable gate array FPGA become SOC chip logic checking model, and is identical with the SOC chip logic function of required checking;
(3) software platform produces the checking initiation command, by functional module and interface module thereof signal is sent into the chip logic checking model.Signal is sent to functional module and interface module thereof through the logical process of chip logic checking model, is converted into software by each functional module and interface module thereof and shows scalar;
(4) software platform produces checking the finish command, by functional module and interface module thereof signal is sent into the chip logic checking model, and the generation Data Receiving was finished signal after model received the finish command, finished checking.
Wherein, simulation waveform output and the oscillographic waveform of the chip logic function in step (1), (2) by software platform exported and verified its logic function.In step (3), (4), all signals are by after the data acquisition, the checking conclusion that draws.
The invention has the beneficial effects as follows and utilize on-site programmable gate array FPGA to build SOC chip logic checking model, the system verification method that utilization software platform and hardware platform combine, the correctness of check SOC chip logic, and can in time be corrected mistake in the logical design and problem, thereby improved the design performance of SOC chip, shortened the construction cycle.
Description of drawings
Fig. 1 is the special-purpose SOC chip logic checking of an industry portable terminal model structure synoptic diagram;
Fig. 2 is the hardware platform structural representation;
Fig. 3 is a SOC chip logic verification method process flow diagram.
Embodiment
With reference to accompanying drawing method of the present invention is done following detailed explanation.
Method of the present invention is to utilize on-site programmable gate array FPGA to build the special-purpose SOC chip system of an industry portable terminal, this system comprises software platform and hardware platform, hardware platform comprises chip logic checking model, functional module and the interface module that is made of on-site programmable gate array FPGA, and wherein functional module links to each other with the chip logic checking model with interface module; Software platform is used for realizing the configuration of chip logic checking model, functional module and interface module thereof and related data are handled, and signal is input to interface module, produce the input signal of chip logic checking model by functional module, by the control signal of chip logic checking model generation, be converted into software by functional module and interface module at last and show scalar software.
On-site programmable gate array FPGA is configured by software platform, describes the chip logic checking model by hardware description language, is realized that by the chip logic checking model step of SOC chip logic checking comprises:
(1) describes the chip logic checking model by hardware description language, make the chip logic checking model meet SOC chip logic function;
(2) software platform is configured on-site programmable gate array FPGA by functional module and interface thereof, and the result of configuration makes on-site programmable gate array FPGA become SOC chip logic checking model, and is identical with the SOC chip logic function of required checking;
(3) software platform produces the checking initiation command, by functional module and interface module thereof signal is sent into the chip logic checking model, signal is sent to functional module and interface module thereof through the logical process of chip logic checking model, is converted into software by each functional module and interface module thereof and shows scalar;
(4) software platform produces checking the finish command, by functional module and interface module thereof signal is sent into the chip logic checking model, and the generation Data Receiving was finished signal after model received the finish command, finished checking.
In step (3), (4), all signals are the checking conclusions by drawing after the data acquisition.
Simulation waveform output and the oscillographic waveform of chip logic function in step (1), (2) by software platform exported and verified its logic function.
Embodiment
The special-purpose SOC chip logic checking of industry portable terminal model as shown in Figure 1, wherein, keyboard scan module 3, CF card driver module 4, rfid card driver module 5, LCD driver module 6, SPI control module 7, I2C control module 8, DSU serial ports 9, JTAG10, USB slave unit 11, Ethernet driver module 12, serial port module 13, USB main equipment module 14 and keyboard scan module 17 link to each other with 32 risc processors 2 by the AMBA bus.Flash flash memory 15 is connected with 32 risc processors 2 by the EMI bus with SRAM storer 16, and above-mentioned module all is configured in the on-site programmable gate array FPGA with the form of code, constitutes SOC logic checking model.
The hardware platform structure as shown in Figure 2, IC-card seat 18 links to each other with IC-card driver module 3, CF deck 19 links to each other with CF card driver module 4, rfid card seat 20 links to each other with rfid card driver module 5, LCD screen 21 links to each other with LCD driver module 6, the CAN bus circuit links to each other with SPI control module 7, serial Flash 22 links to each other with I2C control module 8 with RTC real-time clock 24, PC and software platform 25 and USB slave unit 11, JTAG10 links to each other with DSU serial ports 9, Ethernet PHY circuit 26 links to each other with Ethernet driver module 12, RS485/RS232 interface 27 links to each other with serial port module 13, and USB flash disk 28 links to each other with USB main equipment module 14, and keyboard 29 links to each other with keyboard scan module 17.The course of work is by PC and software platform 25, by the JTAG10 socket, on-site programmable gate array FPGA (SOC logic checking model) to be configured; By DSU serial ports 9, make the intercommunication of PC and software platform 25 and on-site programmable gate array FPGA (SOC logic checking model), debug.
To sum up reach with reference to shown in Figure 3, this patent makes the chip checking process simplification, has improved the design performance of SOC chip, has shortened the construction cycle, thereby, have good value for applications.
Claims (6)
1, a kind of SOC chip logical verification method special for industry portable terminal, it is characterized in that: utilize on-site programmable gate array FPGA to build the special-purpose SOC chip system of an industry portable terminal, this system comprises software platform and hardware platform, hardware platform comprises chip logic checking model, functional module and the interface module that is made of on-site programmable gate array FPGA, and wherein functional module links to each other with the chip logic checking model with interface module; Software platform is used for realizing the configuration of chip logic checking model, functional module and interface module thereof and related data are handled, and signal is input to interface module, produce the input signal of chip logic checking model by functional module, by the control signal of chip logic checking model generation, be converted into software by functional module and interface module at last and show scalar software.
2, SOC chip logic verification method according to claim 1, it is characterized in that: on-site programmable gate array FPGA is configured by software platform, by hardware description language the chip logic checking model is described, realize the SOC chip logic checking by the chip logic checking model, concrete steps comprise:
(1) describes the chip logic checking model by hardware description language, make the chip logic checking model meet SOC chip logic function;
(2) software platform is configured FPGA by functional module and interface thereof, and the result of configuration makes FPGA become SOC chip logic checking model, and is identical with the SOC chip logic function of required checking;
(3) software platform produces the checking initiation command, by functional module and interface module thereof signal is sent into the chip logic checking model, signal is sent to functional module and interface module thereof through the logical process of chip logic checking model, is converted into software by each functional module and interface module thereof and shows scalar;
(4) software platform produces checking the finish command, by functional module and interface module thereof signal is sent into the chip logic checking model, and the generation Data Receiving was finished signal after model received the finish command, finished checking.
3, method according to claim 2 is characterized in that: in step (3), (4), all signals are the checking conclusions by drawing after the data acquisition.
4, method according to claim 2 is characterized in that: simulation waveform output and the oscillographic waveform of the chip logic function in step (1), (2) by software platform exported and verified its logic function.
5, method according to claim 1, it is characterized in that the special-purpose SOC chip logic checking of industry portable terminal model comprises, the keyboard scan module, CF card driver module, the rfid card driver module, the LCD driver module, the SPI control module, the I2C control module, the DSU serial ports, JTAG, the USB slave unit, the Ethernet driver module, serial port module, USB main equipment module and keyboard scan module, wherein, the keyboard scan module, CF card driver module, the rfid card driver module, the LCD driver module, the SPI control module, the I2C control module, the DSU serial ports, JTAG, the USB slave unit, the Ethernet driver module, serial port module, USB main equipment module links to each other with 32 risc processors by the AMBA bus with the keyboard scan module, the Flash flash memory is connected with 32 risc processors by the EMI bus with the SRAM storer, above-mentioned module all is configured in the on-site programmable gate array FPGA with the form of code, constitutes SOC logic checking model.
6, method according to claim 1, it is characterized in that the hardware platform structure comprises, the IC-card seat, the CF deck, the rfid card seat, the LCD screen, the CAN bus circuit, serial Flash, the RTC real-time clock, PC and software platform, Ethernet PHY circuit, the RS485/RS232 interface, USB flash disk, keyboard, wherein, the IC-card seat links to each other with the IC-card driver module, the CF deck links to each other with CF card driver module, the rfid card seat links to each other with the rfid card driver module, the LCD screen links to each other with the LCD driver module, the CAN bus circuit links to each other with the SPI control module, serial Flash links to each other with the I2C control module with the RTC real-time clock, PC and software platform and USB slave unit, JTAG10 links to each other with the DSU serial ports, Ethernet PHY circuit links to each other with the Ethernet driver module, the RS485/RS232 interface links to each other with serial port module, USB flash disk links to each other with USB main equipment module, and keyboard links to each other with the keyboard scan module, by PC and software platform and JTAG socket SOC logic checking model is configured; By the DSU serial ports, make the intercommunication of PC and software platform and SOC logic checking model, debug.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2008101398788A CN101377795A (en) | 2008-09-22 | 2008-09-22 | SOC chip logical verification method special for industry portable terminal |
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| CNA2008101398788A CN101377795A (en) | 2008-09-22 | 2008-09-22 | SOC chip logical verification method special for industry portable terminal |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102497596A (en) * | 2011-12-02 | 2012-06-13 | 青岛海信信芯科技有限公司 | Debugging device and verification method of field programmable gate array (FPGA) platform of television network signal |
| WO2016155290A1 (en) * | 2015-04-01 | 2016-10-06 | 山东华芯半导体有限公司 | Soc chip authentication system and authentication method for dynamic simulation of static compilation |
| CN109189624A (en) * | 2018-09-11 | 2019-01-11 | 西安微电子技术研究所 | A kind of magnanimity information processing device single particle experiment implementation method and single particle test plate |
| CN110188389A (en) * | 2019-04-28 | 2019-08-30 | 上海芷锐电子科技有限公司 | A kind of functional verification structure for artificial intelligence process device chip |
| CN111025129A (en) * | 2019-12-25 | 2020-04-17 | 中电海康无锡科技有限公司 | FPGA-based SOC chip automatic test tool and test method |
| CN111859832A (en) * | 2020-07-16 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | Chip simulation verification method and device and related equipment |
| CN113407393A (en) * | 2021-05-25 | 2021-09-17 | 鹏城实验室 | Chip verification method, terminal device, verification platform and storage medium |
-
2008
- 2008-09-22 CN CNA2008101398788A patent/CN101377795A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102497596A (en) * | 2011-12-02 | 2012-06-13 | 青岛海信信芯科技有限公司 | Debugging device and verification method of field programmable gate array (FPGA) platform of television network signal |
| WO2016155290A1 (en) * | 2015-04-01 | 2016-10-06 | 山东华芯半导体有限公司 | Soc chip authentication system and authentication method for dynamic simulation of static compilation |
| CN109189624A (en) * | 2018-09-11 | 2019-01-11 | 西安微电子技术研究所 | A kind of magnanimity information processing device single particle experiment implementation method and single particle test plate |
| CN109189624B (en) * | 2018-09-11 | 2022-02-01 | 西安微电子技术研究所 | Mass information processor single particle test implementation method and single particle test board |
| CN110188389A (en) * | 2019-04-28 | 2019-08-30 | 上海芷锐电子科技有限公司 | A kind of functional verification structure for artificial intelligence process device chip |
| CN110188389B (en) * | 2019-04-28 | 2023-01-03 | 上海芷锐电子科技有限公司 | Function verification system for artificial intelligent processor chip |
| CN111025129A (en) * | 2019-12-25 | 2020-04-17 | 中电海康无锡科技有限公司 | FPGA-based SOC chip automatic test tool and test method |
| CN111859832A (en) * | 2020-07-16 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | Chip simulation verification method and device and related equipment |
| CN111859832B (en) * | 2020-07-16 | 2022-07-08 | 山东云海国创云计算装备产业创新中心有限公司 | Chip simulation verification method and device and related equipment |
| CN113407393A (en) * | 2021-05-25 | 2021-09-17 | 鹏城实验室 | Chip verification method, terminal device, verification platform and storage medium |
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Open date: 20090304 |