WO2016155290A1 - Soc chip authentication system and authentication method for dynamic simulation of static compilation - Google Patents
Soc chip authentication system and authentication method for dynamic simulation of static compilation Download PDFInfo
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- the invention relates to the field of SOC chip verification, in particular to a SOC chip verification system and a verification method for static compilation dynamic simulation.
- the invention provides a static compilation dynamic simulation SOC chip verification system and a verification method, which can reduce the calculation amount of the simulator and shorten the simulation time.
- a static compilation dynamic simulation SOC chip verification system comprising the following modules:
- the verification model encapsulation module is configured to instantiate each verification model and encapsulate the verification model
- a bidirectional switch control module for connecting a verification model of the chip and the package to implement communication or disconnection between the verification model of the chip and the package;
- the model selection module is used to capture simulation commands and control which verification models need to participate in the simulation according to the simulation commands.
- the model selection module captures macro parameters in the simulation command to control which simulation models need to participate in the simulation.
- a static compilation dynamic simulation SOC chip verification method includes the following steps:
- the chip is connected to the corresponding verification model for simulation.
- the instantiation is first performed, and when simulating, according to different test function requirements, the macro parameters for the relevant verification model enable are defined by the simulation command option.
- the instantiation of the verification model is implemented within the verification model encapsulation module.
- the verification model is connected to the chip through a bidirectional switch.
- the model selection module receives the macro parameter in the simulation command, and determines an enable signal of the corresponding verification model according to the value of the macro parameter.
- the enable signal controls the on and off of the bidirectional switch to verify the connection between the verification model and the chip. If disconnected, the verification model is not triggered and does not participate in the simulation. Otherwise, the verification model participates in the simulation.
- the SOC chip verification system and the verification method for static compiling dynamic simulation provided by the present invention, in order to realize the dynamic selection of the verification model during simulation, the model selection module controls which simulation model needs by grasping macro parameters defined in the simulation command parameters. Participate in the simulation.
- a verification model encapsulation module is designed for each verification model, in which the verification model is encapsulated, and a controllable bidirectional switch is used to control the connection or disconnection between the verification model and the SOC design, thereby controlling whether the verification model is actually Participate in dynamic simulation. All the verification models are compiled and linked statically at compile time, while the simulation dynamically selects which models to participate in the simulation, which can greatly reduce the amount of computation of the simulator and shorten the simulation time.
- FIG. 1 is a schematic structural diagram of a SOC chip verification system for static compilation dynamic simulation according to an embodiment of the present invention.
- the embodiment of the invention provides a static compilation dynamic simulation SOC chip verification system. As shown in FIG. 1 , the system includes the following modules:
- the bidirectional switch control module is a controllable bidirectional switch for connecting the verification model (i) of the chip and the package to realize the connection or disconnection between the SOC chip and the verification model of the package;
- the model selection module tb_model_sel is used to capture macro parameters in the simulation command parameters to control which simulation models need to participate in the simulation.
- the model selection module connects or disconnects the chip and the verification model through the bidirectional switch control module.
- each verification model is connected to the input and output interface of the SOC chip through a controllable bidirectional switch (tranif1 or other switch).
- the enable signal en_model_(i) controls the on and off of the bidirectional switch.
- the enable signal en of each verification model is 0.
- the bidirectional switch tranif1 as an example, when the enable signal en is 0, the switch tranif1 is disconnected, and the connection between the verification model and the SOC is cut off, and then the verification is performed. The model will not be triggered and will not participate in the entire system simulation. Conversely, when the en signal is set to 1 and the switch tranif1 is connected, the verification model participates in the overall system simulation.
- the en signal is generated from the model selection module tb_model_sel.
- the simulation will first receive the macro parameters passed in the emulation command option (-sim_opt), according to the value of the macro parameter. Enable the en signal of the corresponding verification model. Since the macro parameters are passed in when the system is compiled and then enter the simulation phase, all validation models are compiled during the compilation phase and are selectively executed during the simulation phase.
- the embodiment of the invention further provides a static compilation dynamic simulation SOC chip verification method, comprising the following steps:
- the chip is connected to the corresponding verification model for simulation.
- the instantiation is first performed, and when simulating, according to different test function requirements, the macro parameters for the relevant verification model enable are defined by the simulation command option.
- the instantiation of the verification model is implemented within the verification model encapsulation module.
- the verification model is connected to the chip through a bidirectional switch.
- the model selection module receives the macro parameter in the simulation command, and determines an enable signal of the corresponding verification model according to the value of the macro parameter.
- the enable signal controls the on and off of the bidirectional switch to verify the connection between the verification model and the chip. If disconnected, the verification model is not triggered and does not participate in the simulation. Otherwise, the verification model participates in the simulation.
- the SOC chip verification system and the verification method for static compilation dynamic simulation provided by the embodiment of the present invention, in order to realize the dynamic selection of the verification model during simulation, the model selection module controls which simulations are performed by grasping the macro parameters defined in the simulation command parameters.
- the model needs to participate in the simulation.
- a verification model encapsulation module is designed for each verification model, in which the verification model is encapsulated, and a controllable bidirectional switch is used to control the connection or disconnection between the verification model and the SOC design, thereby controlling whether the verification model is actually Participate in dynamic simulation. All the verification models are compiled and linked statically at compile time, while the simulation dynamically selects which models to participate in the simulation, which can greatly reduce the amount of computation of the simulator. Short simulation time.
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Abstract
A SOC chip authentication system and authentication method for dynamic simulation of static compilation, the system comprising authentication model packaging modules, used for implementing instantiation of each authentication model, and packaging the authentication models; a bi-directional switch control module, used for linking the chip and the packaged authentication models, implementing connection or disconnection of the chip and the authentication models; and a model selection module, used for capturing a simulation command and, on the basis of the simulation command, controlling which authentication models need to be involved in the simulation. The present method and system allow dynamic selection of the authentication models during simulation, and the model selection module, by means of capturing the macro parameters defined in the simulation command parameters, controls which authentication models need to be involved in the simulation. An authentication model packaging module is designed for each authentication model, the authentication model being packaged in said module, and a controllable bi-directional switch is used to control the connection and disconnection of the authentication models and the SOC design, thereby controlling whether the authentication models are actually involved in dynamic simulation.
Description
本发明涉及SOC芯片验证领域，尤其涉及一种静态编译动态仿真的SOC芯片验证系统及验证方法。The invention relates to the field of SOC chip verification, in particular to a SOC chip verification system and a verification method for static compilation dynamic simulation.
在片上系统(SOC)芯片设计开发过程中，为了保证各模块之间互连和接口正确性，需要外挂验证模型(也称验证IP)进行芯片级仿真和验证。随着SOC芯片集成规模越来越大，需要外挂的验证模型越来越多。这些外挂的验证模型一旦跟SOC直接连在一起，在SOC系统仿真时就会跟其它设计一起被编译并且参与仿真，仿真器的运算量较大，导致整个设计代码编译仿真速度非常慢，仿真时间较长。In the design and development of the system-on-a-chip (SOC) chip, in order to ensure the interconnection and interface correctness between modules, a plug-in verification model (also called verification IP) is required for chip-level simulation and verification. As the integration of SOC chips becomes larger and larger, more and more verification models need to be plugged in. Once these external verification models are directly connected with the SOC, they will be compiled and participated in the simulation together with other designs during the SOC system simulation. The computational complexity of the simulator is large, resulting in very slow simulation and simulation time of the entire design code. Longer.
发明内容Summary of the invention
本发明提供一种静态编译动态仿真的SOC芯片验证系统及验证方法，可以减少仿真器的运算量，缩短仿真时间。The invention provides a static compilation dynamic simulation SOC chip verification system and a verification method, which can reduce the calculation amount of the simulator and shorten the simulation time.
为了实现上述目的，本发明采用如下技术方案：In order to achieve the above object, the present invention adopts the following technical solutions:
一种静态编译动态仿真的SOC芯片验证系统，包括如下模块：A static compilation dynamic simulation SOC chip verification system, comprising the following modules:
验证模型封装模块，用于对每个验证模型实现例化，并对验证模型进行封装；The verification model encapsulation module is configured to instantiate each verification model and encapsulate the verification model;
双向开关控制模块，用于连接芯片和封装的验证模型，实现芯片和封装的验证模型之间的连通或断开；a bidirectional switch control module for connecting a verification model of the chip and the package to implement communication or disconnection between the verification model of the chip and the package;
模型选择模块，用于抓取仿真命令，并根据仿真命令控制哪些验证模型需要参与仿真。
The model selection module is used to capture simulation commands and control which verification models need to participate in the simulation according to the simulation commands.
可选的，所述的模型选择模块抓取仿真命令中的宏参数来控制哪些仿真模型需要参与仿真。Optionally, the model selection module captures macro parameters in the simulation command to control which simulation models need to participate in the simulation.
一种静态编译动态仿真的SOC芯片验证方法，包括如下步骤：A static compilation dynamic simulation SOC chip verification method includes the following steps:
1)抓取仿真命令中的宏参数，并确定宏参数中的使能信号；1) grab the macro parameter in the simulation command and determine the enable signal in the macro parameter;
2)根据使能信号，连通芯片与相应的验证模型，进行仿真。2) According to the enable signal, the chip is connected to the corresponding verification model for simulation.
可选的，在验证模型参与仿真之前，先进行例化，并且仿真时，根据不同测试功能需求，通过仿真命令选项定义用于相关验证模型使能的宏参数。Optionally, before the verification model participates in the simulation, the instantiation is first performed, and when simulating, according to different test function requirements, the macro parameters for the relevant verification model enable are defined by the simulation command option.
可选的，在验证模型封装模块内实现验证模型的例化。Optionally, the instantiation of the verification model is implemented within the verification model encapsulation module.
可选的，验证模型与芯片之间通过双向开关连接。Optionally, the verification model is connected to the chip through a bidirectional switch.
可选的，在步骤1)中，模型选择模块接收仿真命令中的宏参数，根据宏参数的值确定相应验证模型的使能信号。Optionally, in step 1), the model selection module receives the macro parameter in the simulation command, and determines an enable signal of the corresponding verification model according to the value of the macro parameter.
可选的，使能信号控制双向开关的通断，实现验证模型与芯片之间连接的通断，如果断开则验证模型不会被触发，不参与仿真，反之，验证模型参与仿真。Optionally, the enable signal controls the on and off of the bidirectional switch to verify the connection between the verification model and the chip. If disconnected, the verification model is not triggered and does not participate in the simulation. Otherwise, the verification model participates in the simulation.
本发明提供的静态编译动态仿真的SOC芯片验证系统及验证方法，为了实现验证模型在仿真时的动态可选，模型选择模块通过抓取仿真命令参数中定义的宏参数来控制有哪些仿真模型需要参与仿真。此外，针对每个验证模型设计一个验证模型封装模块，在该模块中将验证模型封装起来，并且使用可控的双向开关控制验证模型与SOC设计之间连通或断开，进而控制验证模型是否实际参与动态仿真。编译时所有的验证模型都被静态地编译和链接，而仿真时则动态地选择哪几个模型参与仿真，从而可以大大减少仿真器的运算量，缩短仿真时间。The SOC chip verification system and the verification method for static compiling dynamic simulation provided by the present invention, in order to realize the dynamic selection of the verification model during simulation, the model selection module controls which simulation model needs by grasping macro parameters defined in the simulation command parameters. Participate in the simulation. In addition, a verification model encapsulation module is designed for each verification model, in which the verification model is encapsulated, and a controllable bidirectional switch is used to control the connection or disconnection between the verification model and the SOC design, thereby controlling whether the verification model is actually Participate in dynamic simulation. All the verification models are compiled and linked statically at compile time, while the simulation dynamically selects which models to participate in the simulation, which can greatly reduce the amount of computation of the simulator and shorten the simulation time.
图1为本发明实施例提供的静态编译动态仿真的SOC芯片验证系统的结构示意图。FIG. 1 is a schematic structural diagram of a SOC chip verification system for static compilation dynamic simulation according to an embodiment of the present invention.
为能清楚说明本方案的技术特点，下面通过一个具体实施方式，并结合其附图，对本方案进行阐述。In order to clearly illustrate the technical features of the present solution, the present embodiment will be described below through a specific embodiment and in conjunction with the accompanying drawings.
本发明实施例提供一种静态编译动态仿真的SOC芯片验证系统，如图1所示，所述系统包括如下模块：The embodiment of the invention provides a static compilation dynamic simulation SOC chip verification system. As shown in FIG. 1 , the system includes the following modules:
验证模型封装模块tb_model，用于对每个验证模型verification model(i)实现例化，并对验证模型verification model(i)进行封装；Verifying the model encapsulation module tb_model for instantiating each verification model verification model(i) and encapsulating the verification model verification model(i);
双向开关控制模块，为可控的双向开关，用于连接芯片和封装的验证模型verification model(i)，实现SOC芯片和封装的验证模型之间的连通或断开；The bidirectional switch control module is a controllable bidirectional switch for connecting the verification model (i) of the chip and the package to realize the connection or disconnection between the SOC chip and the verification model of the package;
模型选择模块tb_model_sel，用于抓取仿真命令参数中的宏参数来控制哪些仿真模型需要参与仿真。The model selection module tb_model_sel is used to capture macro parameters in the simulation command parameters to control which simulation models need to participate in the simulation.
模型选择模块通过双向开关控制模块实现芯片与验证模型的连通或断开。The model selection module connects or disconnects the chip and the verification model through the bidirectional switch control module.
验证时，在tb_model模块内实现验证模型的例化和验证模型与SOC之间的选通连接。各验证模型通过可控的双向开关(tranif1或其它开关)连接到SOC芯片的输入输出接口。使能信号en_model_(i)控制双向开关的通断。默认情况下各验证模型的使能信号en均为0值，以使用双向开关tranif1为例，当使能信号en为0时开关tranif1断开，验证模型与SOC之间的连接被切断，则验证模型不会被触发，不会参与整个系统仿真。反之，当en信号被置1时开关tranif1连通，则验证模型参与整个系统仿真。During verification, the instantiation of the verification model and the gating connection between the verification model and the SOC are implemented within the tb_model module. Each verification model is connected to the input and output interface of the SOC chip through a controllable bidirectional switch (tranif1 or other switch). The enable signal en_model_(i) controls the on and off of the bidirectional switch. By default, the enable signal en of each verification model is 0. To use the bidirectional switch tranif1 as an example, when the enable signal en is 0, the switch tranif1 is disconnected, and the connection between the verification model and the SOC is cut off, and then the verification is performed. The model will not be triggered and will not participate in the entire system simulation. Conversely, when the en signal is set to 1 and the switch tranif1 is connected, the verification model participates in the overall system simulation.
en信号的产生来自于模型选择模块tb_model_sel。在模块tb_model_sel中，仿真时首先会接收仿真命令选项(-sim_opt)中传入的宏参数，根据宏参数的值
使能相应验证模型的en信号。由于宏参数是在系统编译完成后进入仿真阶段时才被传入的，所以所有验证模型在编译阶段都会被编译，在仿真阶段才被选择性地执行。The en signal is generated from the model selection module tb_model_sel. In the module tb_model_sel, the simulation will first receive the macro parameters passed in the emulation command option (-sim_opt), according to the value of the macro parameter.
Enable the en signal of the corresponding verification model. Since the macro parameters are passed in when the system is compiled and then enter the simulation phase, all validation models are compiled during the compilation phase and are selectively executed during the simulation phase.
本发明实施例还提供一种静态编译动态仿真的SOC芯片验证方法，包括如下步骤：The embodiment of the invention further provides a static compilation dynamic simulation SOC chip verification method, comprising the following steps:
1)抓取仿真命令中的宏参数，并确定宏参数中的使能信号；1) grab the macro parameter in the simulation command and determine the enable signal in the macro parameter;
2)根据使能信号，连通芯片与相应的验证模型，进行仿真。2) According to the enable signal, the chip is connected to the corresponding verification model for simulation.
可选的，在验证模型参与仿真之前，先进行例化，并且仿真时，根据不同测试功能需求，通过仿真命令选项定义用于相关验证模型使能的宏参数。Optionally, before the verification model participates in the simulation, the instantiation is first performed, and when simulating, according to different test function requirements, the macro parameters for the relevant verification model enable are defined by the simulation command option.
可选的，在验证模型封装模块内实现验证模型的例化。Optionally, the instantiation of the verification model is implemented within the verification model encapsulation module.
可选的，验证模型与芯片之间通过双向开关连接。Optionally, the verification model is connected to the chip through a bidirectional switch.
可选的，在步骤1)中，模型选择模块接收仿真命令中的宏参数，根据宏参数的值确定相应验证模型的使能信号。Optionally, in step 1), the model selection module receives the macro parameter in the simulation command, and determines an enable signal of the corresponding verification model according to the value of the macro parameter.
可选的，使能信号控制双向开关的通断，实现验证模型与芯片之间连接的通断，如果断开则验证模型不会被触发，不参与仿真，反之，验证模型参与仿真。Optionally, the enable signal controls the on and off of the bidirectional switch to verify the connection between the verification model and the chip. If disconnected, the verification model is not triggered and does not participate in the simulation. Otherwise, the verification model participates in the simulation.
本发明实施例提供的静态编译动态仿真的SOC芯片验证系统及验证方法，为了实现验证模型在仿真时的动态可选，模型选择模块通过抓取仿真命令参数中定义的宏参数来控制有哪些仿真模型需要参与仿真。此外，针对每个验证模型设计一个验证模型封装模块，在该模块中将验证模型封装起来，并且使用可控的双向开关控制验证模型与SOC设计之间连通或断开，进而控制验证模型是否实际参与动态仿真。编译时所有的验证模型都被静态地编译和链接，而仿真时则动态地选择哪几个模型参与仿真，从而可以大大减少仿真器的运算量，缩
短仿真时间。The SOC chip verification system and the verification method for static compilation dynamic simulation provided by the embodiment of the present invention, in order to realize the dynamic selection of the verification model during simulation, the model selection module controls which simulations are performed by grasping the macro parameters defined in the simulation command parameters. The model needs to participate in the simulation. In addition, a verification model encapsulation module is designed for each verification model, in which the verification model is encapsulated, and a controllable bidirectional switch is used to control the connection or disconnection between the verification model and the SOC design, thereby controlling whether the verification model is actually Participate in dynamic simulation. All the verification models are compiled and linked statically at compile time, while the simulation dynamically selects which models to participate in the simulation, which can greatly reduce the amount of computation of the simulator.
Short simulation time.
本发明并不仅限于上述具体实施方式，本领域普通技术人员在本发明的实质范围内做出的变化、改型、添加或替换，也应属于本发明的保护范围。
The invention is not limited to the specific embodiments described above, and variations, modifications, additions or substitutions made by those skilled in the art within the scope of the invention are also intended to fall within the scope of the invention.
Claims (8)
- 一种静态编译动态仿真的SOC芯片验证系统，其特征在于，包括如下模块：A static compilation dynamic simulation SOC chip verification system, characterized in that it comprises the following modules:验证模型封装模块，用于对每个验证模型实现例化，并对验证模型进行封装；The verification model encapsulation module is configured to instantiate each verification model and encapsulate the verification model;双向开关控制模块，用于连接芯片和封装的验证模型，实现芯片和封装的验证模型之间的连通或断开；a bidirectional switch control module for connecting a verification model of the chip and the package to implement communication or disconnection between the verification model of the chip and the package;模型选择模块，用于抓取仿真命令，并根据仿真命令控制哪些仿真模型需要参与仿真。The model selection module is used to capture simulation commands and control which simulation models need to participate in the simulation according to the simulation commands.
- 根据权利要求1所述的静态编译动态仿真的SOC芯片验证系统，其特征在于，所述模型选择模块抓取仿真命令中的宏参数来控制哪些验证模型需要参与仿真。The static compilation dynamic simulation SOC chip verification system according to claim 1, wherein the model selection module captures macro parameters in the simulation command to control which verification models need to participate in the simulation.
- 一种静态编译动态仿真的SOC芯片验证方法，其特征在于，包括如下步骤：A static compilation dynamic simulation SOC chip verification method, characterized in that the method comprises the following steps:1)抓取仿真命令中的宏参数，并确定宏参数中的使能信号；1) grab the macro parameter in the simulation command and determine the enable signal in the macro parameter;2)根据使能信号，连通芯片与相应的验证模型，进行仿真。2) According to the enable signal, the chip is connected to the corresponding verification model for simulation.
- 根据权利要求3所述的静态编译动态仿真的SOC芯片验证方法，其特征在于，在验证模型参与仿真之前，先进行例化，并且仿真时，根据不同测试功能需求，通过仿真命令选项定义用于相关验证模型使能的宏参数。The static compilation dynamic simulation SOC chip verification method according to claim 3, wherein the verification model is instantiated before the simulation model participates in the simulation, and is defined by the simulation command option according to different test function requirements during simulation. Related macro parameters enabled by the validation model.
- 根据权利要求4所述的静态编译动态仿真的SOC芯片验证方法，其特征在于，在验证模型封装模块内实现验证模型的例化。The static compilation dynamic simulation SOC chip verification method according to claim 4, wherein the verification model is instantiated in the verification model encapsulation module.
- 根据权利要求3所述的静态编译动态仿真的SOC芯片验证方法，其特征在于，验证模型与芯片之间通过双向开关连接。 The static compilation dynamic simulation SOC chip verification method according to claim 3, wherein the verification model and the chip are connected by a bidirectional switch.
- 根据权利要求6所述的静态编译动态仿真的SOC芯片验证方法，其特征在于，在步骤1)中，模型选择模块接收仿真命令中的宏参数，根据宏参数的值确定相应验证模型的使能信号。The static compilation dynamic simulation SOC chip verification method according to claim 6, wherein in step 1), the model selection module receives the macro parameter in the simulation command, and determines the enablement of the corresponding verification model according to the value of the macro parameter. signal.
- 根据权利要求7所述的静态编译动态仿真的SOC芯片验证方法，其特征在于，使能信号控制双向开关的通断，实现验证模型与芯片之间连接的通断，如果断开则验证模型不会被触发，不参与仿真，反之，验证模型参与仿真。 The static compilation dynamic simulation SOC chip verification method according to claim 7, wherein the enable signal controls the on and off of the bidirectional switch, and the connection between the verification model and the chip is verified, and if the disconnection is performed, the verification model is not Will be triggered, do not participate in the simulation, and vice versa, verify the model to participate in the simulation.
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| CN106599343B (en) * | 2016-11-01 | 2020-10-20 | 深圳国微技术有限公司 | SOC system verification method and device for improving simulation efficiency |
| CN107293330B (en) * | 2017-06-12 | 2020-08-11 | 北京东土军悦科技有限公司 | Method and system for performing simulation verification on Random Access Memory (RAM) |
| CN110688811B (en) * | 2019-09-12 | 2023-05-02 | 山东华芯半导体有限公司 | Random weight controllable method for accelerating design verification of SOC module |
| CN113204939A (en) * | 2021-04-29 | 2021-08-03 | 山东华芯半导体有限公司 | Full-chip simulation verification method |
| CN115687187B (en) * | 2022-12-15 | 2023-03-31 | 深圳鲲云信息科技有限公司 | Simulation verification method and device, electronic equipment and storage medium |
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