CN106354966B - The method of the conversion of chip id E project file and rapid configuration artificial debugging environment - Google Patents
The method of the conversion of chip id E project file and rapid configuration artificial debugging environment Download PDFInfo
- Publication number
- CN106354966B CN106354966B CN201610811503.6A CN201610811503A CN106354966B CN 106354966 B CN106354966 B CN 106354966B CN 201610811503 A CN201610811503 A CN 201610811503A CN 106354966 B CN106354966 B CN 106354966B
- Authority
- CN
- China
- Prior art keywords
- chip
- project file
- file
- ide
- project
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Abstract
The invention discloses a kind of conversion of chip id E project file and the methods of rapid configuration artificial debugging environment, old edition IDE project file is imported into new edition IDE project file by this method first, generate project file template, the project file template is loaded, then passes through the template rapid configuration artificial debugging environment.The present invention can be compatible with the project file of new version and legacy version, while after completing conversion, realization and slave computer acquirement communication, in the emulation timing file slave computer emulation board of transmission chip, the debugging enironment of rapid configuration chip hardware emulation.
Description
Technical field
The invention belongs to the Integrated Development Environment technical field of chip, in particular to a kind of chip id E project file conversion
With the method for chip hardware artificial debugging environment.
Background technique
The Integrated Development Environment (IDE Integrated Development Environment) of chip is opened as manufacturer
The platform of hair chip plays and its important role, but chip software platform can be continuously updated according to demand, this is related to
The problem of engineering of the compatible legacy version of one new version, when software upgrading is regenerated software frame all change when, new edition
This software cannot will directly open the engineering of legacy version, this needs a project transformation device to extract from old project file
Information is converted into new openable project file.
Old IDE project file and new project file content format are different, old in order to enable new IDE to open
IDE project file and use, therefore to provide a project transformation device to be converted, old project file is converted to newly
Project file.
After the conversion for completing project file, it is also necessary to which a problem of solution is how quickly to obtain to lead to slave computer
Letter, the debugging enironment of rapid configuration chip hardware emulation.According to the parameter that the project file after conversion provides, host computer needs
Connection communication is realized with slave computer emulation board, quickly the emulation timing file of chip is sent in slave computer emulation board, quickly
Configure the debugging enironment of chip hardware emulation.
Patent application 201210595918.6 discloses a kind of emulator for supporting multi-chip configuration feature, including imitative
True device configuration module and emulator hardware.Emulator configuration module is responsible for the selection, downloading and configuration of chip emulation configuration file
The setting of information；Emulator hardware is by download configuration module and data path selecting module, passing under emulator configuration module
Data write memory module corresponding chip emulation configuration file area and configuration information area.After the completion of downloading, control module
According to the content in current configuration information area, the configuration to chip emulation module is completed, realizes the copying of chip.Emulator is matched
Chip configuration file area can flexibly be downloaded by setting module, read current emulator hardware version information.Although this application can be real
The configuration of existing artificial debugging environment, but it is limited only to common simulated environment, it is not particularly suited for the chip configuration of IDE.
Summary of the invention
Based on this, therefore primary mesh of the invention be to provide a kind of conversion of chip id E project file and rapid configuration is imitative
The method of true debugging enironment, the project file of this method compatible new version and legacy version, while after completing conversion, realize with
Slave computer obtains communication, in the emulation timing file slave computer emulation board of transmission chip, the tune of rapid configuration chip hardware emulation
Test ring border.
Another mesh of the invention it is to provide a kind of chip id E project file conversion and rapid configuration artificial debugging ring
The method in border, this method can the artificial debugging environment rapidly and accurately to chip configure, and realize it is easy, it is at low cost
It is honest and clean.
To achieve the above object, the technical solution of the present invention is as follows:
A kind of chip id E project file conversion method, it is characterised in that this method comprises the following steps:
101, new edition IDE project file or solution are opened；
102, the project file of old edition IDE is chosen by the selection catalogue of new edition IDE project file；
103, the project file for parsing old edition IDE, obtains the configuration parameter of chip；
The configuration parameter mainly includes source filename, chip model, engineering type etc..Call project transformation device module；
Obtain the parameter of old edition project file.
104, engineering parameter intermediate file is generated according to the configuration parameter；
The intermediate file of parameter is generated according to the project file of old edition IDE；Intermediate file uses the format of XML, in generation
Between the purpose of file be for some necessary chip parameters of old project file before recording, such as source filename, chip
Series, chip model, engineering type, file path etc..It prepares next to change engineering type or chip model.
105, judge whether engineering type and chip model have change；Judge that engineering type is similar with chip whether to change,
The two parameters are written in above-mentioned intermediate file simultaneously；
106, it generates and loads project file template；
According to the chip configuration parameter that the intermediate file of previous step provides, the parameter of chip model and engineering type is utilized
It generates and loads corresponding project file template.
107, new project file is generated according to above-mentioned chip configuration parameter.
New IDE project file not only includes the IDE project file of new edition as a result, also includes the IDE engineering text of old edition
Part can be compatible with the IDE project file of new edition and old edition；Only need to will project file and interface initialization after, so that it may carry out
The debugging enironment of emulation configures.
A kind of method of chip id E project file rapid configuration artificial debugging environment, it is characterised in that this method includes such as
Lower step:
201, host computer and slave computer, which are established, communicates to connect；
Host computer sends link order, judges that slave computer whether there is or abnormal；Slave computer is waited to return link order；
Slave computer, which receives, to be ordered and parses, and is responded to host computer；Host computer waits whether slave computer is responded, if there is responding, after
Continuous next step exports the error message of communication failure if do not responded.
202, host computer loads chip emulation timing (RBF file) to slave computer；
FPAG emulation timing (RBF file) for starting to load chip needs to send several times since RBF file is larger, sends out
After having sent a bag data, wait whether slave computer has response.
203, slave computer is waited to respond, if midway mistake, output error message；If there is responding, judge whether to send
It finishes.
204, judge whether file is sent.
205, building for chip software and hardware simulated environment is completed.
The RBF file, which issues, needs transport protocol, and protocol format includes that the sum without data includes the two of data kinds
Format, in which:
The first format is free from data, and command format includes synchronous code, order, packet length and check code；Second
Kind format includes data, and command format includes synchronous code, order, packet length, data and check code.
Further, in the first format, primary commands have: direction, include upper line command and down order；Command name,
The entitled PSF_LINKPC of the order of down order, there are two the command names of upper line command, respectively FSP_REPYL, FSP_
ERROR；Description, being described as of down order PSF_LINKPC send link order, under being described as of upper line command FSP_REPYL
Position machine sends response instruction, and the slave computer that is described as of upper line command FSP_ERROR sends mistake；Size of data and remarks.
In second of format, primary commands have: direction, command name, description, size of data and remarks；Direction is downlink life
It enables, orders entitled PSF_RBFPC, be described as sending RBF, size of data nBytes.
The method that the present invention realizes the conversion of chip id E project file solves the compatible legacy version project file of new version
Commission；It can realize according to new edition IDE template and the rapid configuration parameter of chip model simultaneously and obtain communication with slave computer,
In the emulation timing file slave computer emulation board of transmission chip, the debugging enironment of rapid configuration chip hardware emulation.
Detailed description of the invention
Fig. 1 is the chip id E project file flow path switch figure that the present invention is implemented.
Fig. 2 is the structural block diagram for the upper and lower computer that the present invention is implemented.
Fig. 3 is the debugging enironment flow chart for the rapid configuration chip hardware emulation that the present invention is implemented.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
It is the flow chart of chip id E project file conversion method provided by the invention, specific step as shown in Figure 1 are as follows:
S101, file engineering or solution are opened in new edition IDE.
S102, the project file that old edition IDE is chosen into project file selection catalogue.
S103, the project file for parsing old edition IDE, obtain the configuration parameter of chip；Parameter mainly includes source filename, core
Piece model, engineering type etc..
S104, engineering parameter intermediate file is generated according to configuration parameter；Call project transformation device module；Obtain old edition engineering
Parameter of file, such as source filename, chip model, engineering type etc..
It is the intermediate file that parameter is generated according to old edition IDE project file in the step；Intermediate file uses the lattice of XML
Formula, the purpose for generating intermediate file is for some necessary chip parameters of old project file before recording, such as engineering
Name, chip series, chip model, project file type, file path etc..Next to change engineering type or chip model
It prepares.
S105, the selection dialog box that engineering type (C, ASM), chip type switching are shown by graphical interfaces, in order to
Carry out the selection of engineering type and chip model.
S106, judge whether engineering type and chip model have change；Judge whether engineering type and chip model change,
Simultaneously in the intermediate file the two parameter write steps 5.
S107, generation simultaneously load project file template；According to the intermediate file of previous step provide chip configuration parameter,
It is generated using the parameter of chip type and engineering type and loads corresponding project file template.
S108, new project file is generated according to chip configuration parameter.
New IDE project file can be compatible with the IDE project file of old edition as a result,.Project file and interface initialize it
Afterwards, so that it may the debugging enironment configuration emulated.
Upper and lower computer simulation hardware chase figure as indicated at 3, in an embodiment of the present invention, using altera corp's FPGA conduct
Emulator realizes the carrier of emulation, uses FT245BL chip as the interface chip of USB, realizes the communication of PC and FPGA.According to
The modularization design agreement of FPGA concrete model, so that it may send chip emulation timing file (FPGA configuration file RBF) to
In FPGA emulation board.
It realizes that RBF file issues and needs transport protocol, the protocol format of part is as follows:
The first format is free from data, command format such as table 1,
| Synchronous code | Order | Packet length | Check code |
| 1Bytes | 1Byte | 1Bytes | 1Byte |
Table 1
The primary commands of this format have:
Second of format includes data, command format such as table 2.
| Synchronous code | Order | Packet length | Data | Check code |
| 1Bytes | 1Byte | 1Bytes | Length is variable | 1Byte |
Table 2
The primary commands of this format have:
It is that host computer communicates the side for realizing rapid configuration chip hardware artificial debugging environment with lower computer hardware as shown in Figure 3
Method, the specific steps are that:
S201, host computer send bind command；Host computer sends link order, judges that slave computer whether there is or different
Often；Slave computer is waited to return link order,
S202, slave computer, which receive, to be ordered and parses；
S203, host computer wait whether slave computer is responded, and if there is responding, continue in next step, if do not responded, export
The error message of communication failure.
S204, host computer load chip emulation timing (RBF file) to slave computer；When starting to load the FPAG emulation of chip
Sequence (RBF file) needs to send several times since RBF file is larger, after having sent a bag data, whether waits slave computer
There is response.
S205, slave computer is waited to respond, if midway mistake, output error message；If there is responding, judge whether to send
It finishes.
S206, judge whether file is sent.
S207, building for chip software and hardware simulated environment is completed.
S208, output successful information.
The purpose that host computer sends link order is that determining slave computer whether there is or USB connection is abnormal；It waits the next
Machine returns link order and has response according to communication protocol, if do not replied, output error message；If just should indeed
It answers, starts FPAG emulation timing (RBF file) for loading chip, this RBF file is the chip-shaped of the project transformation before
Number and determine, since RBF file is larger, need to cycle through several times, after having sent a bag data, waiting slave computer be
It is no to have response, if midway mistake, output error message；If there is responding, judges whether to be sent, not be sent
Words then need to continue cycling through load RBF file；If load is completed, the debugging enironment of chip hardware emulation is completed, is exported successfully
Information.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (3)
1. a kind of chip id E project file conversion method, it is characterised in that this method comprises the following steps:
101, new edition IDE project file or solution are opened；
102, the project file of old edition IDE is chosen by the selection catalogue of new edition IDE project file；
103, the project file for parsing old edition IDE, obtains the configuration parameter of chip；
104, engineering parameter intermediate file is generated according to the configuration parameter；
105, judge whether engineering type and chip model have change；Judge whether engineering type and chip model change, simultaneously
The two parameters are written in above-mentioned intermediate file；
106, it generates and loads project file template；
107, new project file is generated according to above-mentioned chip configuration parameter；
In 103 step, the configuration parameter mainly includes source filename, chip model, engineering type, by calling engineering
Conversion module obtains the parameter of old edition project file.
2. chip id E project file conversion method as described in claim 1, it is characterised in that in 104 step, according to old
The project file of version IDE generates the intermediate file of parameter；Intermediate file uses the format of XML.
3. chip id E project file conversion method as described in claim 1, it is characterised in that in 106 step, according to upper
The chip configuration parameter that the intermediate file of one step provides is generated using the parameter of chip model and engineering type and is loaded corresponding
Project file template.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610811503.6A CN106354966B (en) | 2016-09-06 | 2016-09-06 | The method of the conversion of chip id E project file and rapid configuration artificial debugging environment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610811503.6A CN106354966B (en) | 2016-09-06 | 2016-09-06 | The method of the conversion of chip id E project file and rapid configuration artificial debugging environment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106354966A CN106354966A (en) | 2017-01-25 |
| CN106354966B true CN106354966B (en) | 2019-11-08 |
Family
ID=57858293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610811503.6A Active CN106354966B (en) | 2016-09-06 | 2016-09-06 | The method of the conversion of chip id E project file and rapid configuration artificial debugging environment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106354966B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107390111A (en) * | 2017-06-22 | 2017-11-24 | 芯海科技（深圳）股份有限公司 | A kind of ICNewProject automated testing methods |
| CN115291963A (en) * | 2022-06-17 | 2022-11-04 | 芯华章科技股份有限公司 | Method for configuring hardware resources, electronic device and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102436385A (en) * | 2011-11-15 | 2012-05-02 | 电子科技大学 | Online updating device for configuration files of programmable logic device |
| CN103580975A (en) * | 2013-11-22 | 2014-02-12 | 北京机械设备研究所 | On-line reconfigurable generalized bus data conversion method |
| CN103678751A (en) * | 2012-09-25 | 2014-03-26 | 上海华虹集成电路有限责任公司 | Processor chip simulation debugging system |
| CN104090792A (en) * | 2014-07-03 | 2014-10-08 | 电子科技大学 | Method for dynamically loading logical files in broadband access network |
| CN104461624A (en) * | 2014-12-03 | 2015-03-25 | 电子科技大学 | Remote upgrading method of near probe measuring module for three-dimensional acoustic logging instrument |
| CN105022869A (en) * | 2015-06-30 | 2015-11-04 | 深圳市芯海科技有限公司 | Fast reconfigurable MCU simulation method |
| CN105373407A (en) * | 2015-12-07 | 2016-03-02 | 中国船舶重工集团公司第七〇五研究所 | DSP and FPGA online upgrading method for embedded system |
| CN105718339A (en) * | 2015-12-31 | 2016-06-29 | 山东大学 | FPGA/CPLD remote debugging system and method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120005693A1 (en) * | 2010-01-08 | 2012-01-05 | Cypress Semiconductor Corporation | Development, Programming, and Debugging Environment |
| CN102779056B (en) * | 2012-06-28 | 2016-02-24 | 深圳市芯海科技有限公司 | Remote hardware method for updating program and system |
-
2016
- 2016-09-06 CN CN201610811503.6A patent/CN106354966B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102436385A (en) * | 2011-11-15 | 2012-05-02 | 电子科技大学 | Online updating device for configuration files of programmable logic device |
| CN103678751A (en) * | 2012-09-25 | 2014-03-26 | 上海华虹集成电路有限责任公司 | Processor chip simulation debugging system |
| CN103580975A (en) * | 2013-11-22 | 2014-02-12 | 北京机械设备研究所 | On-line reconfigurable generalized bus data conversion method |
| CN104090792A (en) * | 2014-07-03 | 2014-10-08 | 电子科技大学 | Method for dynamically loading logical files in broadband access network |
| CN104461624A (en) * | 2014-12-03 | 2015-03-25 | 电子科技大学 | Remote upgrading method of near probe measuring module for three-dimensional acoustic logging instrument |
| CN105022869A (en) * | 2015-06-30 | 2015-11-04 | 深圳市芯海科技有限公司 | Fast reconfigurable MCU simulation method |
| CN105373407A (en) * | 2015-12-07 | 2016-03-02 | 中国船舶重工集团公司第七〇五研究所 | DSP and FPGA online upgrading method for embedded system |
| CN105718339A (en) * | 2015-12-31 | 2016-06-29 | 山东大学 | FPGA/CPLD remote debugging system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106354966A (en) | 2017-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103178996B (en) | Distributed packet-switching chip model verification system and method | |
| CN102375778B (en) | Method and system for automatically testing digital signal processor (DSP) | |
| CN102866944B (en) | Pressure testing system and method | |
| CN108845940B (en) | Enterprise-level information system automatic function testing method and system | |
| US8209341B2 (en) | Configurable transformation macro | |
| CN102750301B (en) | Blueprint generating method for integrated avionic system model aiming at architecture analysis and design language (AADL) description | |
| CN101739334A (en) | Automatic testing method of embedded software | |
| CN104679488A (en) | Flow path customized development platform and method | |
| CN105528290A (en) | Construction method of script-based embedded software simulation and test integrated platform | |
| CN102306122A (en) | Automated testing method and equipment | |
| US10528688B1 (en) | System and method for schematic-driven generation of input/output models | |
| CN110362490B (en) | Automatic testing method and system for integrating iOS and Android mobile applications | |
| CN105591779A (en) | Method and device for inspecting network element | |
| CN106528184A (en) | App development method based on cordova platform | |
| CN105577463A (en) | Testing method and testing device based on communication protocol | |
| WO2023082926A1 (en) | Configuration method and apparatus, and device and storage medium | |
| CN106354966B (en) | The method of the conversion of chip id E project file and rapid configuration artificial debugging environment | |
| CN106339249B (en) | Dynamic configuration programmed method | |
| CN106484452A (en) | A kind of unified configuring management method of software platform and device | |
| WO2017113848A1 (en) | Testing method, testing platform and simulated testing device for test case | |
| CN1996265A (en) | Method and system for implementing automatic testing | |
| CN108287720A (en) | software compilation method, device, equipment and storage medium | |
| CN110045963A (en) | A kind of method and device of linux kernel compiling and verifying | |
| US10606569B2 (en) | Declarative configuration elements | |
| CN109543122B (en) | Content synchronization method, device, storage medium and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |