CN103580975A - On-line reconfigurable generalized bus data conversion method - Google Patents
On-line reconfigurable generalized bus data conversion method Download PDFInfo
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- CN103580975A CN103580975A CN201310592100.3A CN201310592100A CN103580975A CN 103580975 A CN103580975 A CN 103580975A CN 201310592100 A CN201310592100 A CN 201310592100A CN 103580975 A CN103580975 A CN 103580975A
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Abstract
The invention discloses an on-line reconfigurable generalized bus data conversion method. The method is implemented by a bus data conversion circuit (1), a multi-bus interface circuit (4), a CPU (central processing unit) circuit (6), an Ethernet communication circuit (7), an FPGA (field programmable gate array) configuration module (8) and a power control circuit (9); an FPGA configuration file, downloaded by an upper computer, of a bus protocol conversion module (5) is received by the CPU circuit (6) and written to a FPGA configuration chip (3); an FPGA circuit (2) is powered on and reads the FPGA configuration chip (3) for configuration, and then the system starts bus data conversion work; and different bus protocol conversion modules (5) perform on-line reconfiguration with the same steps. By virtue of a multi-bus interface sharing hardware and software platform and on-line reconfiguration, the system size and power consumption are reduced while various types of bus data conversion are performed, and hardware and software resource utilization rate is increased.
Description
Technical field
The present invention relates to a kind of bus data conversion method, particularly a kind of online reconfigurable generalization bus data conversion method.
Background technology
Bus data exchange is widely used in domestic and international Modern distribution formula control system, complicated along with control system, single control system is no longer only used unified bus to communicate and is controlled, and a typical control system inside exists the multiple bus of multichannel to carry out the exchanges data of subsystem or intermodule conventionally simultaneously.At present conventional bus data conversion method is all forever solidificated in the computer program for bus protocol conversion or FPGA configuration file the bus data conversion that the subsidiary electric board of computer or fpga chip complete fixed type when adopting computer or FPGA to carry out bus protocol conversion.Described these conventional bus data conversion methods have following limitation: all compare Focus on the one hand, can only carry out the conversion of data between specific two kinds of buses; Even if can carry out the mutual conversion between multiple bus on the other hand, but in order to realize the conversion of data between multiple bus simultaneously, need integrated more software and hardware resources simultaneously, cause that system bulk, power consumption are large, reliability reduces, and the module of software and hardware of a plurality of different bus datas conversions when system in can cause software and hardware resources to leave unused while not needing to work simultaneously.
Summary of the invention
The object of the present invention is to provide a kind of online reconfigurable generalization bus data conversion method, between functions of modules unification, function and the volume that in solution dcs, bus data conversion exists and power consumption, have the problem of contradiction and resources idle.
A kind of concrete steps of online reconfigurable generalization bus data conversion method are:
The first step is built bus data conversion platform
Bus data conversion platform, comprising: bus data change-over circuit, cpu circuit, ethernet communication circuit and power control circuit.Described bus data change-over circuit, comprising: FPGA circuit, FPGA configuring chip and multi-bus interface circuit, comprise bus protocol modular converter in FPGA circuit; In cpu circuit, comprise FPGA configuration module.Cpu circuit is connected with FPGA configuring chip with FPGA circuit by jtag port simultaneously, the universal I/O port of FPGA circuit is connected with multi-bus interface circuit, predetermines the IO port of FPGA circuit and the mapping relations between the bus interface in multi-bus interface circuit.The power supply of power control circuit control bus data converting circuit, cpu circuit and ethernet communication circuit.Ethernet communication circuit is connected with host computer by Ethernet.
Bus protocol modular converter is to use hardware description language to develop and obtain in the FPGA of host computer Integrated Development Environment, by host computer by Ethernet to pass under FPGA configuration file form.The function of bus protocol modular converter, for configuration FPGA circuit, makes FPGA circuit carry out bus data conversion work.
FPGA configuration module operates in cpu circuit.The function of FPGA configuration module is for receiving the FPGA configuration file of bus protocol modular converter and this file being write to FPGA configuring chip.
Second step cpu circuit and ethernet communication circuit Power-On Self-Test
Power control circuit is to cpu circuit and ethernet communication circuit supply, and cpu circuit and ethernet communication circuit complete self check, then move FPGA configuration module, waits for the FPGA configuration file that receives bus protocol modular converter.
The 4th step FPGA configuration module receives the FPGA configuration file of bus protocol modular converter
Host computer passes down by Ethernet after the FPGA configuration file of bus protocol modular converter, and the FPGA configuration file that FPGA configuration module receives bus protocol modular converter by ethernet communication circuit deposits cpu circuit in.
The 5th step FPGA configuration module writes FPGA configuring chip by the FPGA configuration file of bus protocol modular converter
Power control circuit is to the power supply of FPGA configuring chip, and cpu circuit operation FPGA configuration module, writes FPGA configuring chip by jtag port by the FPGA configuration file of bus protocol modular converter.
The 6th step cpu circuit and ethernet communication circuit and the power-off of FPGA configuring chip
Power control circuit is to cpu circuit, ethernet communication circuit and the power-off of FPGA configuring chip.FPGA configuring chip is Flash structure, can power down preserves the FPGA configuration file of bus protocol modular converter.After the power-off of FPGA configuring chip, wait for that FPGA circuit powers on and read the FPGA configuration file of bus protocol modular converter.
The 7th step FPGA configuring chip configuration FPGA circuit
Power control circuit is powered to bus data change-over circuit, after powering on, reads in FPGA circuit FPGA configuring chip, after the FPGA configuration file of bus protocol modular converter is read in and is configured, bus data change-over circuit starts to carry out the bus data conversion work that bus protocol modular converter is corresponding.
The 8th step bus data change-over circuit switches bus data translation type online
While needing the dissimilar bus data of online switching to change, first make power control circuit close the power supply of bus data change-over circuit and connect cpu circuit and the power supply of ethernet communication circuit, the FPGA configuration file of the dissimilar bus protocol modular converter that then FPGA configuration module reception host computer passes down also writes FPGA configuring chip by this file, then power control circuit is closed the power supply of cpu circuit and ethernet communication circuit the power supply of turn-on bus data converting circuit, the FPGA circuit FPGA configuration file that reads the dissimilar bus protocol modular converter of preserving in FPGA configuring chip that powers on is reshuffled the rear dissimilar bus data conversion work that starts to carry out.
So far completed online reconfigurable generalization bus data conversion.
The present invention carries out the unitized bus data change-over circuit of polytype bus data conversion formation by using multi-bus interface to share FPGA circuit, can carry out unitized multibus conversion, has reduced conversion equipment volume simultaneously, has reduced its power consumption.Especially use Embedded cpu circuit and ethernet communication circuit by Ethernet, to carry out the online reconfiguration of bus protocol modular converter, make can switch flexibly between the conversion of polytype bus, utilized very efficiently the software and hardware resources of system.
Accompanying drawing explanation
A kind of online reconfigurable generalization bus data conversion method block diagram of Fig. 1;
1. bus data change-over circuit 2.FPGA circuit 3.FPGA configuring chip 4. multi-bus interface circuit 5. bus protocol modular converter 6.CPU circuit 7. ethernet communication circuit 8.FPGA configuration module 9. power control circuits.
Embodiment
A kind of concrete steps of online reconfigurable generalization bus data conversion method are:
The first step is built bus data conversion platform
Bus data conversion platform, comprising: bus data change-over circuit 1, cpu circuit 6, ethernet communication circuit 7 and power control circuit 9.Described bus data change-over circuit 1, comprising: FPGA circuit 2, FPGA configuring chip 3 and multi-bus interface circuit 4, comprise bus protocol modular converter 5 in FPGA circuit 2; In cpu circuit 6, comprise FPGA configuration module 8.Cpu circuit 6 is connected with FPGA configuring chip 3 with FPGA circuit 2 by jtag port simultaneously, the universal I/O port of FPGA circuit 2 is connected with multi-bus interface circuit 4, predetermines the IO port of FPGA circuit 2 and the mapping relations between the bus interface in multi-bus interface circuit 4.The power supply of power control circuit 9 control bus data converting circuits 1, cpu circuit 6 and ethernet communication circuit 7.Ethernet communication circuit 7 is connected with host computer by Ethernet.
Bus protocol modular converter 5 is to use hardware description language to develop and obtain in the FPGA of host computer Integrated Development Environment, by host computer by Ethernet to pass under FPGA configuration file form.The function of bus protocol modular converter 5, for configuration FPGA circuit 2, makes FPGA circuit 2 carry out bus data conversion work.
FPGA configuration module 8 operates in cpu circuit 6.The function of FPGA configuration module 8 is for receiving the FPGA configuration file of bus protocol modular converter 5 and this file being write to FPGA configuring chip 3.
Second step cpu circuit 6 and ethernet communication circuit 7 Power-On Self-Tests
Power control circuit 9 is given cpu circuit 6 and 7 power supplies of ethernet communication circuit, and cpu circuit 6 and ethernet communication circuit 7 complete self check, then move FPGA configuration module 8, wait for the FPGA configuration file that receives bus protocol modular converter 5.
The 4th step FPGA configuration module 8 receives the FPGA configuration file of bus protocol modular converter 5
Host computer passes down by Ethernet after the FPGA configuration file of bus protocol modular converter 5, and the FPGA configuration file that FPGA configuration module 8 receives bus protocol modular converter 5 by ethernet communication circuit 7 deposits cpu circuit 6 in.
The 5th step FPGA configuration module 8 writes FPGA configuring chip 3 by the FPGA configuration file of bus protocol modular converter 5
Power control circuit 9 gives FPGA configuring chip 3 power supplies, and cpu circuit 6 operation FPGA configuration modules 8, write FPGA configuring chip 3 by jtag port by the FPGA configuration file of bus protocol modular converter 5.
The 6th step cpu circuit 6 and ethernet communication circuit 7 and 3 power-off of FPGA configuring chip
Power control circuit 9 is given cpu circuit 6, ethernet communication circuit 7 and 3 power-off of FPGA configuring chip.FPGA configuring chip 3 is Flash structure, can power down preserves the FPGA configuration file of bus protocol modular converter 5.After 3 power-off of FPGA configuring chip, wait for that FPGA circuit 2 powers on and read the FPGA configuration file of bus protocol modular converter 5.
The 7th step FPGA configuring chip 3 configuration FPGA circuit 2
Power control circuit 9 gives bus data change-over circuit 1 power supply, after powering on, reads in FPGA circuit 2 FPGA configuring chip 3, after the FPGA configuration file of bus protocol modular converter 5 is read in and is configured, bus data change-over circuit 1 starts to carry out the bus data conversion work of bus protocol modular converter 5 correspondences.
The online bus data translation type of switching of the 8th step bus data change-over circuit 1
While needing the dissimilar bus data of online switching to change, first make power control circuit 9 close the power supply of bus data change-over circuit 1 and connect cpu circuit 6 and the power supply of ethernet communication circuit 7, the FPGA configuration file of the dissimilar bus protocol modular converter 5 that then FPGA configuration module 8 reception host computers pass down also writes FPGA configuring chip 3 by this file, then power control circuit 9 is closed the power supply of cpu circuit 6 and ethernet communication circuit 7 power supply of turn-on bus data converting circuit 1, the FPGA circuit 2 FPGA configuration file that reads in FPGA configuring chip 3 the dissimilar bus protocol modular converter 5 of preserving that powers on is reshuffled the rear dissimilar bus data conversion work that starts to carry out.
So far completed online reconfigurable generalization bus data conversion.
Claims (1)
1. an online reconfigurable generalization bus data conversion method, is characterized in that the concrete steps of this method are:
The first step is built bus data conversion platform
Bus data conversion platform, comprising: bus data change-over circuit (1), cpu circuit (6), ethernet communication circuit (7) and power control circuit (9); Described bus data change-over circuit (1), comprising: FPGA circuit (2), FPGA configuring chip (3) and multi-bus interface circuit (4), comprise bus protocol modular converter (5) in FPGA circuit (2); In cpu circuit (6), comprise FPGA configuration module (8); Cpu circuit (6) is connected with FPGA configuring chip (3) with FPGA circuit (2) by jtag port simultaneously, the universal I/O port of FPGA circuit (2) is connected with multi-bus interface circuit (4), predetermines the IO port of FPGA circuit (2) and the mapping relations between the bus interface in multi-bus interface circuit (4); The power supply of power control circuit (9) control bus data converting circuit (1), cpu circuit (6) and ethernet communication circuit (7); Ethernet communication circuit (7) is connected with host computer by Ethernet;
Bus protocol modular converter (5) is to use hardware description language to develop and obtain in the FPGA of host computer Integrated Development Environment, by host computer by Ethernet to pass under FPGA configuration file form; The function of bus protocol modular converter (5), for configuration FPGA circuit (2), makes FPGA circuit (2) carry out bus data conversion work;
FPGA configuration module (8) operates in cpu circuit (6); The function of FPGA configuration module (8) is for receiving the FPGA configuration file of bus protocol modular converter (5) and this file being write to FPGA configuring chip (3);
Second step cpu circuit (6) and ethernet communication circuit (7) Power-On Self-Test
Power control circuit (9) is given cpu circuit (6) and ethernet communication circuit (7) power supply, cpu circuit (6) and ethernet communication circuit (7) complete self check, then move FPGA configuration module (8), wait for the FPGA configuration file that receives bus protocol modular converter (5);
The 4th step FPGA configuration module (8) receives the FPGA configuration file of bus protocol modular converter (5)
Host computer passes down by Ethernet after the FPGA configuration file of bus protocol modular converter (5), and the FPGA configuration file that FPGA configuration module (8) receives bus protocol modular converter (5) by ethernet communication circuit (7) deposits cpu circuit (6) in;
The 5th step FPGA configuration module (8) writes FPGA configuring chip (3) by the FPGA configuration file of bus protocol modular converter (5)
Power control circuit (9) is given FPGA configuring chip (3) power supply, and cpu circuit (6) operation FPGA configuration module (8), writes FPGA configuring chip (3) by jtag port by the FPGA configuration file of bus protocol modular converter (5);
The 6th step cpu circuit (6), ethernet communication circuit (7) and FPGA configuring chip (3) power-off
Power control circuit (9) is given cpu circuit (6), ethernet communication circuit (7) and FPGA configuring chip (3) power-off; FPGA configuring chip (3) is Flash structure, can power down preserves the FPGA configuration file of bus protocol modular converter (5); After FPGA configuring chip (3) power-off, wait for that FPGA circuit (2) powers on and read the FPGA configuration file of bus protocol modular converter (5);
The 7th step FPGA configuring chip (3) configuration FPGA circuit (2)
Power control circuit (9) is given bus data change-over circuit (1) power supply, after powering on, reads in FPGA circuit (2) FPGA configuring chip (3), after the FPGA configuration file of bus protocol modular converter (5) is read in and is configured, bus data change-over circuit (1) starts to carry out the bus data conversion work that bus protocol modular converter (5) is corresponding;
The 8th step bus data change-over circuit (1) switches bus data translation type online
While needing the dissimilar bus data of online switching to change, first make power control circuit (9) close the power supply of bus data change-over circuit (1) and connect cpu circuit (6) and the power supply of ethernet communication circuit (7), the FPGA configuration file of the dissimilar bus protocol modular converter (5) that then FPGA configuration module (8) reception host computer passes down also writes FPGA configuring chip (3) by this file, then power control circuit (9) is closed the power supply of cpu circuit (6) and ethernet communication circuit (7) the power supply of turn-on bus data converting circuit (1), FPGA circuit (2) the FPGA configuration file that reads the dissimilar bus protocol modular converter (5) of preserving in FPGA configuring chip (3) that powers on is reshuffled the rear dissimilar bus data conversion work that starts to carry out,
So far completed online reconfigurable generalization bus data conversion.
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| CN104035422A (en) * | 2014-06-23 | 2014-09-10 | 中国北方车辆研究所 | Data calculation method based on smart mobile terminal |
| CN104394150A (en) * | 2014-11-26 | 2015-03-04 | 大连梯耐德网络技术有限公司 | System and method for implementing mimic security network architecture based on hardware reconfiguration |
| CN105159252A (en) * | 2015-08-18 | 2015-12-16 | 深圳市科昭科技有限公司 | Robot intelligent cloud compatible control system |
| CN105516158A (en) * | 2015-12-18 | 2016-04-20 | 山东海量信息技术研究院 | Configurable protocol conversion state machine circuit structure and protocol configuration method |
| CN106354966A (en) * | 2016-09-06 | 2017-01-25 | 芯海科技（深圳）股份有限公司 | Method for converting chip IDE project files and rapidly configuring simulation debugging environment |
| CN107741733A (en) * | 2017-08-08 | 2018-02-27 | 研祥智能科技股份有限公司 | Field bus system and fieldbus recognition methods |
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Application publication date: 20140212 |