CN201174706Y - Ethernet serial power converter based on FPGA technique - Google Patents
Ethernet serial power converter based on FPGA technique Download PDFInfo
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- CN201174706Y CN201174706Y CNU2007201883197U CN200720188319U CN201174706Y CN 201174706 Y CN201174706 Y CN 201174706Y CN U2007201883197 U CNU2007201883197 U CN U2007201883197U CN 200720188319 U CN200720188319 U CN 200720188319U CN 201174706 Y CN201174706 Y CN 201174706Y
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Abstract
The utility model relates to an Ethernet serial port converter based on the FPGA technology. The Ethernet serial port converter is a data automatic converting device which realizes the interconnection of the serial port field bus RS232/422/485 data interface standard and the computer Ethernet data interface standard. The converter adopts the embedded system design based on FPGA. The whole circuit system mainly consists of four parts, wherein the first part is an embedded system circuit which is established by taking the FPGA as the core design, a 32-bit soft-core CPU is established inside of the FPGA, a periphery circuit of the embedded system mainly consists of a 16MBSDRAM program memory, 8MB Flash data memory and 4Mbits serial port configuration device; the second part is a serial port bus level driving circuit which consists of a RS232/422/485 driving chip; the third part is an Ethernet communication circuit and mainly consists of an isolated pulse transformer and an Ethernet MAC control chip; and the fourth part is a power supply circuit. The converter can automatically realize the conversion of the standard serial port bus data to the Ethernet data and transmits the converted data by TCP protocol and UDP protocol.
Description
Technical field
The utility model is a kind of data communication conversion equipment that is used for the serial bus of industrial equipment is converted to computer Ethernet data bus, belongs to the data conversion equipment of fieldbus in the industrial equipment.
Background technology
The most of universal serial bus (being the RS232/422/485 standard) that adopts of the data communication of equipment such as instrument and meter transducer in the industrial equipment, will carry out centralized control to this class industrial equipment must connect by universal serial bus, adopt polling mode, realize equipment pointwise communication.And exist a large amount of equipment to need to control in the industrial equipment now, a large amount of field datas need read, equipment room needs interactive type communication control, if still adopt universal serial bus to carry out data communication, it is limited then can communication distance to occur, data format is complicated alternately, the control logic confusion, the transfer of data real-time is poor, efficiency of transmission is low, can not effectively realize centralized management and on-site supervision, another problem appears again simultaneously, promptly how that the industrial equipment realization of different manufacturers is integrated mutually, realize interactive type communication control, make full use of existing software and hardware resources.
Along with the fast development of computer ethernet technology and day by day ripe, it is convenient, flexible that it has networking, connects convenient and reliable, transmission range is unrestricted, control mode is flexible, is convenient to safeguard and the centralized management monitoring, and has advantages such as good opening and reliability.And ethernet communication technology and standard thereof have promoted to global data insert standard, are that industrial equipment, surveying instrument, household electrical appliance are all actively being realized device networkization now.The utility model is just in order to realize device networkization design.
Summary of the invention
The purpose of this utility model is based on the embedded technology of FPGA, design the Ethernet serial converter that a kind of serial bus with industrial equipment is converted to the Ethernet data bus based on the FPGA technology, it is by the embedded technology based on FPGA, data between realization serial data bus (RS232/422/485 bus) and the Ethernet are changed automatically, and existing industrial equipment based on serial bus communication control is carried out device network transformation and design.
The novel technical scheme of this use is as follows:
The utility model is realized the realistic problem of interactive operation at a large amount of serial bus that use in the industrial equipment, and the development of consideration embedded ethernet technology, design and Implement a kind of Ethernet serial converter based on the FPGA technology, the hardware configuration of entire circuit system adopts modularized design, comprises with FPGA being embedded processing module, serial bus level driver module, ethernet communication module and the power circuit of core.
The embedded processing module that with FPGA is core is the core of design construction embedded system circuit, the processor of embedded system is by forming at 32 soft nucleus CPUs of FPGA internal build, for cooperating its work embedded system peripheral circuit mainly to constitute, simultaneously in FPGA indoor design serial data transmission/reception and Synchronization Control logic by SDRAM program storage, Flash data storage and series arrangement device.
Serial bus level drive circuit is made of the RS232/422/485 chip for driving, the RXD of RS232 chip for driving, TXD signal link to each other with the IO pin of fpga chip respectively, DI, RO signal that RS422 drives link to each other with the IO pin of FPGA respectively, the DI of RS485 chip for driving, RO, RE#, DE signal link to each other with the IO pin of fpga chip, and they carry out exporting after the level conversion to the data of sending from fpga chip.The data that will send output to the TXD end of RS232/422/485 chip for driving from fpga chip, carry out exporting after the level conversion, when received signal is finished level conversion through the RS232/422/485 chip for driving after the RXD end is sent to fpga chip, handle to received signal and sample, and the transmission receive logic of universal serial bus data is all realized with the VHDL programming in fpga chip.
The ethernet mac control module is made of Isolated Pulse Transformer, ethernet mac control chip, the data/address bus of ethernet mac control chip, control bus link to each other with the IO pin of fpga chip respectively, and the TX+ of ethernet mac control chip, TX-, RX+, RX-pin then link to each other with TDP, TDN, RDP, the RDN pin of Isolated Pulse Transformer.
Power circuit is whole transducer power supply.
The utlity model has following advantage:
(1) solves in the industrial equipment serial bus to the transformation of device networkization
Serial bus interface place at traditional industry equipment connects the Ethernet serial converter, can directly data encapsulation be transmitted by Ethernet in the TCP/IP Frame, the structure that settings such as its IP address setting, communication protocol selection need not changed industrial equipment, only need the Ethernet serial converter is set, the utility model is realized universal serial bus industrial equipment networking transformation easily, have and use simply, characteristics easily are set.
Topology diagram behind the industrial equipment access network based on ethernet serial converter is referring to Fig. 1.
(2) guarantee the real-time and the reliability of serial bus communication between devices network
After the industrial equipment networking of universal serial bus, it is convenient, flexible to have a networking, connects convenient and reliablely, and transmission range is unrestricted, and control mode is flexible, is convenient to safeguard and the centralized management monitoring, and has advantages such as good opening and reliability.Just can carry out Synchronization Control, monitoring, data acquisition, interactive type communication by center-controlling computer to the industrial equipment of all-networkization, make every cover industrial equipment that independent IP address all be arranged, control centre can finish management roles such as following inspection, order, control, location, transmission rate strengthens the real-time of control efficiently, the maturation of Ethernet networking equipment and technology strengthens the reliability of controlling simultaneously.
(3) make things convenient for telemanagement and plant maintenance
Adopt the Ethernet serial converter, strengthen the controllability of on-the-spot serial bus equipment, be convenient to system's centralized management, every cover industrial equipment has independent IP address, in the Control Software of backstage, can utilize the uniqueness of IP address accurately to locate, owing to adopt the Ethernet technology, the industrial equipment after the networking can be inserted public network simultaneously, make things convenient for telemanagement and industrial equipment producer remote equipment to safeguard or system upgrade.
(4) opening of realization system
Because the Ethernet serial converter adopts the Embedded System Design based on FPGA, development and Design has extremely strong flexibility, can be at the data format of universal serial bus and frame definition different, adopt VHDL language programming realization that different data format frames is sampled and transmit control, can realize secondary development; Data encapsulation after will sampling then becomes the TCP/IP Frame to carry out Network Transmission, and the Ethernet transmission technology is open agreement, also can easily realize secondary development.
Description of drawings
Fig. 1 is the topology diagram behind the industrial equipment access network based on ethernet serial converter
Fig. 2 is based on the hardware block diagram of the Ethernet serial converter of FPGA
Fig. 3 A is based on the input/output interface circuit figure of fpga chip
Fig. 3 B is the circuit diagram of SDRAM program storage;
Fig. 3 C is the circuit diagram of Flash data storage;
Fig. 3 D-1, Fig. 3 D-2, Fig. 3 D-3 are the configuration circuit figure of FPGA;
Fig. 3 E is ethernet mac control circuit figure;
Fig. 3 F is universal serial bus level shifting circuit figure;
Fig. 3 G is a power circuit diagram;
Fig. 4 is the inner VHDL software architecture diagram of FPGA;
Fig. 5 is based on the c program software flow pattern of NiosII;
Fig. 6 asynchronous serial communication form;
Fig. 7 is with the synchronous detecting and the sampling process of 16 times of baud rate clocks.
Embodiment
Owing to adopt the Ethernet serial converter, strengthen the controllability of on-the-spot serial bus equipment, be convenient to system's centralized management and monitoring in real time, and Synchronization Control between industrial equipment and operation.The Ethernet serial converter is except finishing protocol conversion, and each transducer all has independent IP address, and control centre can finish management roles such as following inspection, order, control, location, is convenient to management and also can determines its particular location simultaneously.
(1) hardware configuration of Ethernet serial converter
, mainly constitute, as shown in Figure 2 by the modular method design based on the hardware configuration of the Ethernet serial converter of FPGA by the embedded processing module, serial bus level driver module, ethernet communication module and the power circuit that with FPGA are core.
1, with FPGA be the embedded processing module of core, referring to Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D-1, Fig. 3 D-2,
Fig. 3 D-3:
This processing module adopts the SOPC system based on the soft nuclear of FPGA embedding IP to carry out Embedded System Design, fpga chip U3 adopts the EP1C12Q240C8 chip of altera corp, the soft nuclear of the IP NiosII that employing altera corp provides is as embedded type CPU, NiosII is a kind of 32 RISC flush bonding processors, it is soft kernel form, has very big flexibility, can be provided with in the combination in multiple systems and select, satisfy the requirement of cost and function, adopt the NiosII kit to contain a general peripheral hardware of cover and an interface library simultaneously, utilize the SOPC Builder of the altera corp designing user logic interfacing that develops software, the utility model is presented to the serial bus control logic in the NiosII system with SOPC Builder instrument exactly, because the operation embedded system needs lot of data to handle and storage, with a slice 16MB SDRAM chip U4 as program storage, adopt the MT48LC4M32B2 chip of Micron company, it has the memory capacity of 16MB.Finish all logics of SDRAM at the NiosII of FPGA inside processor by sdram controller, its 32 data/address buss, 12 row address buses, 4 column address bus, 2 block address bus, 6 control buss link to each other with the IO pin of U3 (FPGA) respectively.As data storage, adopt the AM29LV065D chip of AMD with a slice 8MB Flash chip U7, it has the memory capacity of 8MB.Its 23 address buss, 8 data/address buss, 4 control buss link to each other with the IO pin of U3 (FPGA) respectively, to pass through the programmable device programming in AM29LV065D based on the application program of NiosII processor, before program running, the code among the AM29LV065D can be copied in the MT48LC4M32B2 chip, carry out then.Because EP1C12Q240C8 is based on the SRAM look-up table, configuration data must reload when device powers on, and therefore must be that a device that can power down keeps is preserved configuration data, when EP1C12Q240C8 powers on configuration data is loaded among the FPGA then.The series arrangement memory adopts the EPCS4 chip U10 of altera corp to be used for the configuration that powers on to FPGA, and it directly links to each other with the specific pin of EP1C12Q240C8.The circuit theory diagrams of this part as shown in Figure 3.
2, universal serial bus level switch module is referring to Fig. 3 F
The universal serial bus level shifting circuit is respectively that the RS232 bus adopts MAX3232 chip U5, its RXD, TXD signal link to each other with the IO pin of U3 (FPGA) respectively, the RS422 bus adopts MAX3490 chip U6, its DI, RO signal link to each other with the IO pin of U3 (FPGA) respectively, the RS485 bus adopts MAX3485 chip U11, and its DI, RO, RE#, DE signal link to each other with the IO pin of U3 (FPGA).
3, ethernet control module. referring to Fig. 3 E:
The ethernet mac control circuit adopts the DM9000a special chip U8 of Davicom company, DM9000a be one fully integrated, powerful, the ethernet mac controller that cost performance is high, it has a general processor interface, the EEPROM interface, the SRAM of 10/100PHY and 16KB, adopt single power supply, I/O interface level that can compatibility+3.3V/5V, its 16 data wires, article 7, control bus links to each other with the IO pin of U3 (FPGA) respectively, its TX+, TX-, RX+, the RX-pin then with the TDP of Isolated Pulse Transformer U12, TDN, RDP, the RDN pin links to each other, and Isolated Pulse Transformer adopts the HR601680 small size Isolated Pulse Transformer of HanRun company.
4, power circuit, referring to Fig. 3 G:
Consider the power supply unit and the low-power consumption demand of industrial equipment, employing+5V voltage input (can obtain) by the Switching Power Supply of outside 220V alternating voltage, the builtin voltage of whole transducer only needs+3.3V and+1.5V, the power circuit design time considers+electric current of 3.3V is bigger, so employing LT1086-3.3 linear transformer U1 general+5V voltage becomes+3.3V; And the electric current of right+1.5V is less, adopts LM1117-ADJ linear transformer U2 general+5V voltage to become+1.5V.
(2) based on the software design of FPGA, referring to Fig. 4:
Software design based on FPGA is divided into two aspects, and the firstth, design serial bus control logic, it adopts the VHDL language design, mainly finishes serial data transmission/reception and Synchronization Control logic; The secondth, utilizing the SOPC Builder of altera corp to develop software and making up with the NiosII flush bonding processor is the embedded hardware system of core.
1. the VHDL programming of serial bus control logic,
During asynchronous serial communication, each character can appear in the data flow at random as frame information independently, and promptly to appear at the relative time in the data flow be arbitrarily to each character.Yet after a character Once you begin occurred, everybody was the clock frequency transmission with predetermined fixed in the character.Therefore, " asynchronous " of asynchronous communication means is mainly reflected between character and the character, as for same character inside the position and interdigit but be synchronous.As seen,, must find a kind of method, receiving-transmitting sides is realized synchronously at character that transmits at random and intercharacter in order to ensure the correctness of asynchronous communication.This method is provided with start bit and position of rest exactly in character format.
The transformat of asynchronous communication as shown in Figure 6.Every frame information (being each character) is made up of 4 parts:
1) 1 start bit is defined as low level " 0 ".
2) 5～8 bit data positions, it is the effective information that will transmit immediately following in the start bit back.Regulation transmits successively from low level a to high position.
3) 0 or 1 bit parity check position.
4) 1,1
Position or 2 position of rests are defined as high level.
For improving the reliability of asynchronous serial communication, sampling clock adopts the clock of 4 or 16 times of baud rates usually, as shown in Figure 7.After sampling clock adopts 16 frequencys multiplication, sampling, testing process is as follows: the back of position of rest or arbitrary number spare bits, receiver is sampled to input traffic at the rising edge of each receive clock, by detecting whether 9 continuous low levels are arranged, determines if it is start bit.In this way, then be confirmed to be start bit, and corresponding be the start bit center, then as accurate time reference,, detect a data bit every 16 the clock once sampling same period.As not being 9 continuous low levels (even in 9 sampled values one non-" 0 " being arranged), think that then this is an interference signal, its deletion.As seen, adopt 16 frequency multiplication measures after, not only help realizing transmitting-receiving synchronously, and help anti-interference and improve the reliability of asynchronous serial communication.
In the Synchronization Control that serial data receives, one 6 digit counter is set, utilize the count status of this counter, realize the Synchronization Control that serial data receives, this technology device holding position " 0 " all before the start bit no show of RXD end, when detecting start bit, synchronizing control just immediately this counter is changed to " 011100B " later on, after this counter startup is counted CLK, when the counter meter arrives " 111111B ", a data receiving course finishes, counter is in 0 state again, waits for the arrival of next start bit.The Synchronization Control that Synchronization Control that serial data sends and serial data receive is similar, and its process is opposite.
1. make up the NiosII embedded system
Adopt Nios processor development and Design must first configuration processor structure, content such as interface is set.That is to say to make up a processor according to the actual requirements, and traditional processor to have fixed interface, ram in slice and external equipment.The required particular hardware design work of system design is as follows:
1) chooses suitable 32 NiosII CPU, memory and peripheral components (as on-chip memory, PIO, chip external memory interface) with SOPC Builder system synthesis software, and customize their function.
2) use QuartusII software to choose EP1C12Q240C8 FPGA device, utilize the SOPC Builder of the altera corp CPU peripheral modules such as making up NiosII flush bonding processor, sdram interface control module, Flash interface control module, Ethernet DM9000a interface control module and timer/counter module, system identifier that develops software, adopt the customization pattern to add the serial bus control logic module simultaneously.The HDL design document that generates by SOPC Builder then; Re-use Quartus II software on the EP1C12Q240C8 the various I/O mouths in the Nios II system being distributed pin, also will carry out the setting of hardware compilation option or temporal constraint as requested in addition.In the process of compiling, Quartus II generates configuration file at last from the comprehensive net table that generates a suitable target devices of HDL source file.
(3) Ethernet protocol and the application software based on embedded system designs, referring to Fig. 5
Software design based on embedded system is divided into two aspects, the firstth, on the basis of NiosII embedded system, adopt protocol handling program such as C language design serial data control program (data that are about to the hardware layer reception are read among the CPU, and the data passes that CPU will be sent arrives hardware layer) and ethernet mac control program, ARP agreement, udp protocol, Transmission Control Protocol; The secondth, on the basis of NiosII embedded system, adopt C language design utility control program, be the protocol process module of the data of universal serial bus by device, fieldbus data is packaged into TCP/IP Frame or UDP message frame, deliver to the Surveillance center of far-end by Ethernet and intergrade switching equipment, otherwise, convert TCP/IP Frame or the UDP message frame sent here to serial data bus by the folding envelope, simultaneity factor also will be finished tasks such as metadata cache and frame collision detection.
Claims (7)
1, based on the Ethernet serial converter of FPGA technology, it is characterized in that: it comprises with FPGA being embedded processing module, serial bus level driver module, ethernet communication module and the power circuit of core;
Described is that the embedded processing module of core is formed by fpga chip and by the peripheral circuit that SDRAM program storage, Flash data storage and series arrangement device constitute with FPGA; The data/address bus of SDRAM program storage, address bus and control bus link to each other with the IO pin of fpga chip respectively; The data/address bus of Flash data storage, address bus and control bus also link to each other with the IO pin of fpga chip respectively; The series arrangement device directly links to each other with the pin of fpga chip, to the fpga chip configuration that powers on;
Described serial bus level driver module is made of the RS232/422/485 chip for driving, the RXD of RS232 chip for driving, TXD signal link to each other with the IO pin of fpga chip respectively, the DI of RS422 chip for driving, RO signal link to each other with the IO pin of fpga chip respectively, the DI of RS485 chip for driving, RO, RE#, DE signal link to each other with the IO pin of fpga chip, and they carry out exporting after the level conversion to the data of sending from fpga chip;
The ethernet mac control module is made of Isolated Pulse Transformer, ethernet mac control chip, the data/address bus of ethernet mac control chip, control bus link to each other with the IO pin of fpga chip respectively, and the TX+ of ethernet mac control chip, TX-, RX+, RX-pin then link to each other with TDP, TDN, RDP, the RDN pin of Isolated Pulse Transformer;
Power circuit is whole transducer power supply.
2, the Ethernet serial converter based on the FPGA technology according to claim 1 is characterized in that: described fpga chip adopts the EP1C12Q240C8 fpga chip.
3, the Ethernet serial converter based on the FPGA technology according to claim 1 is characterized in that: described SDRAM program storage adopts the MT48LC4M32B2 chip.
4, the Ethernet serial converter based on the FPGA technology according to claim 1 is characterized in that: described Flash data storage adopts the AM29LV065D chip.
5, the Ethernet serial converter based on the FPGA technology according to claim 1, it is characterized in that: described RS232/422/485 chip for driving adopts MAX3232 chip, MAX3490 chip and MAX3485 chip respectively.
6, the Ethernet serial converter based on the FPGA technology according to claim 1, it is characterized in that: described ethernet mac control module adopts the DM9000a special chip, it has the SRAM of a general processor interface, EEPROM interface, 10/100PHY and 16KB, adopt single power supply, the I/O interface level of compatibility+3.3V/5V.
7, the Ethernet serial converter based on the FPGA technology according to claim 1 is characterized in that: described Isolated Pulse Transformer adopts HR601680 small size Isolated Pulse Transformer.
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| CN101777034A (en) * | 2010-03-22 | 2010-07-14 | 哈尔滨工业大学 | RS422 asynchronous serial card with hardware timed sending function and communication method thereof |
| CN101882124A (en) * | 2010-06-13 | 2010-11-10 | 昆山五昌新精密电子工业有限公司 | RS422/485 double-use signal converter capable of automatically judging connector |
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| CN102299839A (en) * | 2010-06-24 | 2011-12-28 | 创锐讯通讯技术（上海）有限公司 | MAC (Media Access Control) chip of user side equipment in EOC (Ethernet over Coax) network and realization method thereof |
| CN101917322A (en) * | 2010-08-10 | 2010-12-15 | 西安电子科技大学 | Self-adaptive multibus fusion method |
| CN101917322B (en) * | 2010-08-10 | 2012-07-25 | 西安电子科技大学 | Self-adaptive multibus fusion method |
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| CN107911372B (en) * | 2017-11-24 | 2021-01-26 | 杭州迪普科技股份有限公司 | Method and device for realizing access of serial device to Ethernet based on logic device |
| CN108667701A (en) * | 2018-03-13 | 2018-10-16 | 中国电子科技集团公司第十研究所 | A kind of ether network switch and data transfer device |
| CN111030866A (en) * | 2019-12-18 | 2020-04-17 | 南京品尼科自动化有限公司 | Communication management system |
| CN113452628A (en) * | 2021-06-22 | 2021-09-28 | 中国船舶重工集团公司第七0七研究所 | Multifunctional interface adapter and control method thereof |
| CN114894046A (en) * | 2022-05-23 | 2022-08-12 | 西安微电子技术研究所 | Universal switching value pulse intelligent interface test card |
| CN114894046B (en) * | 2022-05-23 | 2023-11-10 | 西安微电子技术研究所 | Universal switching value pulse intelligent interface test card |
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