RU2686004C1 - Computing module - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to computer engineering, particularly to computing devices with a reconfigurable architecture. Computing module comprises PCI-Express 1 switch, PLD interface 2, a group of computational PLD 3₁, …, 3_N, external PCI-Express port 4, a group of computer VLSI 5₁, …, 5_N, JTAG external monitoring and control port 6, unit 7 of operational configuration of interface PLD 2, memory 8 configuration of interface PLD 2, unit 9 of operational reconfiguration of memory of starting configurations of computational PLD 3₁, …, 3_N, group of start configurations memory 10₁, …, 10_N computational PLD 3₁, …, 3_N, individual monitoring and power control units 11₁, …, 11_N computational VLSI 5₁, …, 5_N, module monitoring module 17, individual tuning units of operating frequencies 12₁, …,12n of computational VLSI 5₁, …, 5_N, individual monitoring units 13₁, …, 13_N, Ethernet network switch 21, random access memory 20₁, …, 20_N, unit for control and power supply of module 14, module interface units with power control and monitoring system 15 and with monitoring system 18, external network port 22, external monitoring port 19, external control and power control port 16.

EFFECT: technical result is higher efficiency of the computing module.

1 cl, 1 dwg

Description

TECHNICAL FIELD

The invention relates to the field of computing, in particular, to computing devices with a tunable architecture, using programmable logic integrated circuits (FPGAs) and custom-made VLSI.

PRIOR ART

A computational module is known (RU # 168565 U1, IPC G06F 15/16, announced on 11/21/2016, published on February 8, 2017, Bulletin No. 4), which contains an external PCI-Express port for information exchange, a PCI-Express switch, an interface and N computing FPGAs , each of which contains a high-speed serial interface PCI-Express, an interface FPGA operational configuration block, a power control and monitoring unit, a monitoring block, an external JTAG monitoring and control port, an FPGA interface configuration memory, a bi-directional common FPGA computing bus, a group ny of VLSI computing N, a group of N memories starting FPGA configurations computing unit operative rearranging memories starting configurations and FPGA computational sync block.

The disadvantages of this computational module are the inefficient use of its computational power in solving computationally complex tasks that require a high intensity of FPGA computing information exchange over the external PCI-Express port, and the uneven power consumption of the module, depending on the nature of the tasks being solved.

The reasons hindering the achievement of the technical result are the use of an external PCI-Express port both for exchanging data and FPGA computational results in the course of performing tasks, and for transmitting information about the state of the module blocks, and the inability of this module to solve tasks at the current time point different exchange rate and different power consumption, which is associated with a single system of synchronization and configuration.

The closest device of the same purpose to the claimed utility model, on the basis of a combination of features, is the computational module adopted as a prototype (RU # 174347 U1, IPC G06F15 / 00, G06F15/177, G06F 17/00, announced on 05/18/2017, published on 11.10.2017 Bulletin # 29) containing an external PCI-Express port for information exchange, a PCI-Express switch, an interface and N computational FPGAs, each of which contains a high-speed PCI-Express serial interface, an online FPGA configuration block, a group of N individual control blocks and control feed e, group of N individual monitoring units, external JTAG monitoring and control port, interface memory FPGA configuration memory, bidirectional common FPGA computing configuration bus, a group of N computational VLSI, a group of N memories of the starting FPGA computing configurations, operative reconfiguration memory section of the starting computation configurations FPGA, a group of N blocks for individual adjustment of operating frequencies of computational VLSI and monitoring unit.

The disadvantages of this computational module are the inefficient use of its computational power in solving computationally complex problems, which require a high intensity of FPGA computing information exchange over the external PCI-Express port, and the relative limitedness of the classes of computationally complex problems to be solved.

The reasons hindering the achievement of the technical result are the use of the external PCI-Express port in this computing module both for exchanging the data and the results of the computational FPGAs in the course of performing tasks, and for transmitting information about the state of the modules of the module, which with large amounts of information and a large number of computing modules in the composition of reconfigurable computing devices, reduces the time of interaction with each individual FPGA, and accordingly reduces the amount of processed yes GOVERNMENTAL. In addition, the use of computational VLSI in this computational module with a direct circuit implementation of the critical sections of labor-intensive fragments of computational algorithms limits the classes of computationally complex problems to be solved.

OBJECTIVE OF THE INVENTION

The problem to which the invention is directed, is to create a high-performance computing module for solving a wide class of computationally complex tasks.

The technical result of the present invention is an increase in computational power when solving computationally complex tasks requiring high intensity of information exchange of computational FPGAs on an external PCI-Express port and the expansion of classes of computationally complex tasks to be solved.

BRIEF DESCRIPTION OF THE INVENTION

This technical result in the implementation of the invention is achieved by the fact that the computing module containing the switch PCI-Express 1, interface FPGA 2, a group of N computing FPGA 3 ₁ , ..., 3 _N , external port PCI-Express 4, a group of N computing VLSI 5 ₁ , ..., 5 _N , external port of control and management of the JTAG 6 module, block 7 of operational configuration of interface FPGA 2, memory 8 of configuration of interface FPGA 2, block 9 of online reconfiguration of memories of starting configurations of computational FPGA 3 ₁ , ..., 3 _N , group from N memories starting figurations 10 _1, ..., 10 _N computing FPGA 3 _1, ..., 3 _N, a group of N individual control and power management units 11 _1, ..., 11 _N computing VLSI 5 _1, ..., 5 _N, the monitoring unit module 17, a group from N blocks of individual tuning of working frequencies 12 ₁ , ..., 12 _N computing VLSI 5 ₁ , ..., 15 _N , a group of N individual monitoring blocks 13 ₁ , ..., 13 _N ,

the ports of the PCI-Express 1 switch are connected by the corresponding high-speed PCI-Express serial interfaces with the external port of module 4, interface 23 with interface FPGA 2 and a group of N 25 interfaces ₁ , ..., 25 _N with N computational FPGAs 3 ₁ , ..., 3 _N , each of which is connected by individual bi-directional information buses 32 ₁ , ..., 32 _N with corresponding computational VLSI 5 ₁ , ..., 5 _N ,

interface FPGA 2 is connected by the corresponding buses to the operational configuration block 7 of the interface FPGA 2, to the operational reconfiguration block 9 of the starting configuration memory 10 ₁ , ..., 10 _N and to the monitoring module of the module 17, and also connected by a bi-directional common configuration bus 24 to N computing FPGA 3 ₁ , ..., 3 _N and a common bus 34 with N blocks of individual tuning of working frequencies 12 ₁ , ..., 12 _N ,

in addition, the block 7 operational configuration of the interface FPGA 2 is connected to the memory 8 of the configuration of the interface FPGA 2 and to the external monitoring and control port of the JTAG 6 module,

The operative reconfiguration of memories 9 is connected by a common bus 26 with N memories of starting configurations 10 ₁ , ..., 10 _N computing FPGA 3 ₁ , ..., 3 _N ,

at that, N computational FPGA 3 ₁ , ..., 3 _{N are} connected to the corresponding N memory of the starting configurations 10 ₁ , ..., 10 _N by a group of N individual reconfiguration tires 28 ₁ , ..., 28 _N and a group of N individual operational reconfiguration tires 27 ₁ , ..., 27 _N , as well as a group of N individual buses 29 ₁ , ..., 29 _N power management and control computing VLSI 5 ₁ , ..., 5 _{N are} connected to a group of N units of individual power control and management 11 ₁ , ..., 11 _N ,

in addition, N blocks of individual tuning of working frequencies 12 ₁ , ..., 12 _{N are} connected by corresponding buses to the same VLSI groups of N computational VLSI 5 ₁ , ..., 5 _N and a group of N individual bus operating frequency settings 31 ₁ , ..., 31 _N with the corresponding computational FPGA 3 ₁ , ..., 3 _N ,

the monitoring unit of the module 17 is connected by a common bus 35 with N individual monitoring units 13 ₁ , ..., 13 _N , each of which is connected to the corresponding computational PLIS 3 ₁ , ..., 3 _{N of the} same name with individual monitoring tires 33 ₁ , ..., 33 _N ,

additionally, an Ethernet network switch 21, a group of N operative memories 20 ₁ , ..., 20 _N , a module 14 power control and management unit, a module interface box with a power management system 15, an interface module module with a monitoring system 18, an external network port module 22, the external monitoring port of module 19, the external monitoring and power control port of module 16,

moreover, a group of N operative memories 20 ₁ , ..., 20 _{N is} connected by the corresponding buses to the same computing VLSI 5 ₁ , ..., 5 _N , which are connected by the corresponding network interfaces 36 ₁ , ..., 36 _N to the Ethernet switch 21, which is also connected to external network port of module 22,

in addition, the control unit and power management module 14 is connected to the interface FPGA 2, as well as the common bus 30 is connected to the N individual power control and management units 11 ₁ , ..., 11 _N computing VLSI 5 ₁ , ..., 5 _N and connected to the unit pairing the module with the power control and management system 15, which is connected to the external power control and control port of the module 16,

the monitoring module of the module 17 is connected to the interface module of the module with the monitoring system 18, which is connected to the external monitoring port of the module 19.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the functional diagram of the computing module.

FIG. 1 and the following abbreviations and notation are used in the text:

VM - computing module;

N is the number of computational FPGAs and VLSI in the VM;

i is a countable variable.

1 - PCI-Express switch;

2 - interface FPGA;

3 ₁ , ..., 3 _N - a group of N computational FPGAs;

4 - high-speed external serial port PCI-Express;

5 ₁ , ..., 5 _N - a group of N computational VLSI;

6 - external monitoring and control port of the JTAG module;

7 - block operational configuration interface FPGA 2;

8 - memory configuration interface FPGA 2;

9 - block of operational reconfiguration of memories of starting configurations 10 ₁ , ..., 10 _N computational FPGA 3 ₁ , ..., 13 _N ;

10 ₁ , ..., 10 _N - a group of N memories of the starting configurations of the computational FPGA 3 ₁ , ..., 13 _N ;

11 ₁ , ..., 11 _N - a group of N blocks of individual power control and management of computational VLSI 5 ₁ , ..., 5 _N ;

12 ₁ , ..., 12 _N - a group of N blocks for individual adjustment of operating frequencies of computational VLSI 5 ₁ , ..., 5 _N ;

13 ₁ , ..., 13 _N - a group of N individual monitoring units of computational FPGA 3 ₁ , ..., 3 _N and VLSI 5 ₁ , ..., 5 _N ;

14 — module power control and management unit;

15 - module interfacing unit with power control and management system;

16 - external port of control and management of power supply of the module;

17 — module monitoring unit;

18 - module interfacing unit with a monitoring system;

19 - external monitoring port of the module;

20 ₁ , ..., 20 _N - a group of N operational memories;

21 - Ethernet network switch;

22 - external network port of the module;

23 - high-speed serial interface PCI-Express between the switch PCI-Express 1 and interface FPGA 2;

24 is a bidirectional common bus for configuring computational FPGAs 3 ₁ , ..., 3 _N ;

25 ₁ , ..., 25 _N - a group of N high-speed PCI-Express serial interfaces between the PCI-Express 1 switch and FPGA 3 ₁ , ..., 3 _N ;

26 - common bus for operational reconfiguration of memories of starting configurations 10 ₁ , ..., 10 _N computational FPGA 3 ₁ , ..., 3 _N ;

27 ₁ , ..., 27 _N - a group of N individual tires of operational reconfiguration of memories of starting configurations 10 ₁ , ..., 10 _N computational FPGA 3 ₁ , ..., 3 _N ;

28 ₁ , ..., 28 _N - a group of N individual bus reconfiguration computing FPGA 3 ₁ , ..., 3 _N ;

29 ₁ , ..., 29 _N - a group of N individual power control and control buses for computational VLSI 5 ₁ , ..., 5 _N ;

30 - common bus control and power management computing VLSI 5 ₁ , ..., 5 _N ;

31 ₁ , ..., 31 _N - a group of N individual buses tuning the operating frequencies of computational VLSI 5 ₁ , ..., 5 _N ;

32 ₁ , ..., 32 _N - a group of N bidirectional information buses between the same-named VLSI 5n 5n computing and FPGA 3 ₁ , ..., 3 _N ;

33 ₁ , ..., 33 _N - a group of N individual FPGA monitoring tires 3 ₁ , ..., 3 _N ;

34 - common bus tuning operating frequency computing VLSI 8 ₁ , ..., 8 _N ;

35 — common module monitoring bus;

36 ₁ , ..., 36 _N - a group of N network interfaces computing VLSI 5 ₁ , ..., 5 _N.

DETAILED DESCRIPTION OF THE INVENTION

The switch PCI-Express 1 is designed to organize information exchange with interface FPGA 2 and with N computing FPGA 3 ₁ , ..., 3 _N via external port 4 and organization of interaction between N computing FPGA 3 ₁ , ..., 3 _N among themselves via PCI-Express interfaces 25 ₁ , ..., 25 _N. The PCI-Express 1 switchboard contains N + 2 high-speed ports that are connected to an external PCI-Express 4 port, from an interface FPGA 2 via a PCI-Express 23 interface, to N computational FPGAs 3 ₁ , ..., 3 _N through N PCI-Express interfaces 25 ₁ , ..., 25 _N.

Computational FPGAs 3 ₁ , ..., 3 _N are intended for the implementation of high-performance preprocessing of incoming input data, the subsequent additional processing of the results of the operation of computational VLSI 5 ₁ , ..., 5 _N , and also ensure the exchange of data and results with computational VLSI 5 ₁ , ..., 5 _N . In addition, computational FPGA 3 ₁ , ..., 3 _N exchange information with individual monitoring units 13 ₁ , ..., 13 _N and individual power control and management units 11 ₁ , ..., 11 _N , thereby ensuring the power management of computational VLSI 5 ₁ , ..., 5 _N and configure the operating frequencies of the computational VLSI 5 ₁ , ..., 5 _N and the configuration itself using its own resources and reconfiguring its own memory of the starting configurations 10 ₁ , ..., 10 _N without using the resources of the interface FPGA 2.

Computational VLSI 5 ₁ , ..., 5 _N can carry out both direct circuitry implementation of critical sections of laborious fragments of computational algorithms, and also perform hardware and software data processing for wider classes of computationally complex tasks using RAM 20 ₁ , ..., 20 _N as for storage of the executed program, and for storage of intermediate results of its execution.

Interface FPGA 2 is designed to organize the exchange of information with the monitoring module of module 17, with block 9 of the online reconfiguration of the memory of the starting configurations of the computational FPGA 3 ₁ , ..., 3 _N , with the control and management module of the module 14 power supply, with blocks for individual setting of working frequencies 12 ₁ , ..., 12 _N computational VLSI 5 ₁ , ..., 5 _N on the common configuration bus 34, as well as for the operational configuration of the computation FPGA 3 ₁ , ..., 3 _N on the bi-directional common configuration bus 24.

Block 7 of the operational configuration of the interface FPGA 2 is designed to organize the configuration of the interface FPGA 2 via the external monitoring and control port of the JTAG 6 module or, when the module is powered up, from the memory 8 of the configuration of the FPGA 2 intended for storing its working configuration.

A group of N memories 10 ₁ , ..., 10 _N starting configurations of computational FPGA 3 ₁ , ..., 3 _{N is} designed to store individual starting configurations of computational FPGA 3 ₁ , ..., 3 _N , which can be both the same and different.

The external port of control and management of the JTAG 6 module is intended for organizing the monitoring and control of the interface FPGA 2 and computational FPGA 3 ₁ , ..., 3 _{N by} means of CAD from an external control computer at the stage of setting up the computation module and for diagnosing faults.

Block 9 online reconfiguration of the memory of the starting configurations of computational FPGA 3 ₁ , ..., 3 _{N is} designed for initial loading from the interface FPGA 2 via the common bus 26 of the starting configurations of computing FPGA 3 ₁ , ..., 3 _N into a group of N memories 10 ₁ , ..., 10 _N.

The power supply monitoring and control unit of the module 14 is designed to control the supply voltage levels and control the switching on of the module power supplies (power supplies in Fig. 1 are not shown) using the common bus 30 and a group of N units 11 ₁ , ..., 11 _N individual control and management powering the computational VLSI 5 ₁ , ..., 5 _N , and interaction with the external power control and control system through the module interface unit with the power control and management system 15 through the external power control and control port of the module 16.

A group of N blocks 11 ₁ , ..., 11 _{N of} individual power control and management of computational VLSI 5 ₁ , ..., 5 _{N is} designed to realize the possibility of independent control and power management of computational VLSI 5 ₁ , ..., 5 _{N of the} same name computational FPGA 3 ₁ , ... , 3 _N , through a group of N individual tires 29 ₁ , ..., 29 _N.

A group of N units 13 ₁ , ..., 13 _{N of} individual monitoring of computational FPGA 3 ₁ , ..., 3 _N , and VLSI 5 ₁ , ..., 5 _{N is} designed to realize the possibility of independent monitoring of the temperature mode of computational FPGA 3 ₁ , ..., 3 _N and computing VLSI 5 ₁ , ..., 5 _N.

The monitoring unit of module 17 and a group of N individual monitoring units 13 ₁ , ..., 13 _N are designed to monitor the temperature mode of N computational FPGAs 3 ₁ , ..., 3 _N and N computational VLSI 5 ₁ , ..., 5 _N over a common monitoring bus of module 35 and on individual tires 33 ₁ , ..., 33 _N monitoring from computational FPGA 3 ₁ , ..., 3 _N , using temperature sensors embedded in computation FPGA 3 ₁ , ..., 3 _N and computational VLSI 5 ₁ , ..., 5 _N ( temperature sensors in Fig. 1 are not shown), Module 17 monitoring module also interacts with external systems oh monitoring through the module interface unit with the monitoring system 18 through the external monitoring port of the module 19.

The tuning blocks of the working frequencies 12 ₁ , ..., 12 _N are designed to provide the required individual working frequencies of the corresponding computational VLSI 5 ₁ , ..., 5 _N with the same name, controlled from the interface FPGA 2 via the common bus for setting the operating frequencies of 34 computing VLSI 5 ₁ , ..., 5 _N , or from the same computing FPGA 3 ₁ , ..., 3 _N on individual buses 31 ₁ , ..., 31 _N settings of the operating frequencies of computational VLSI 5 ₁ , ..., 5 _N.

A group of N operative memories 20 ₁ , ..., 20 _{N is} intended for buffering successive tasks, processed data and obtained results when using custom-made VLSI 5 ₁ , ..., 5 _N with a direct circuit implementation of critical sections of laborious fragments of computational algorithms, and for storing executed programs and intermediate results when using computational VLSI with software implementation of time-consuming fragments of computational algorithms.

The network switch Ethernet 21 is designed to ensure the interaction of computational VLSI 5 ₁ , ..., 5 _N via network interfaces 36 ₁ , ..., 36 _N through the external network port of module 22 with other external computing facilities and among themselves for the exchange of data, results and programs.

The proposed computing module works as follows.

After supplying the primary power to the computing module, the working configuration is loaded into the interface FPGA 2 by the FPGA 7 operational configuration module from the FPGA interface configuration memory 8 and the starting configurations into the FPGA 3 ₁ , ..., 3 _N configurations from the starting configuration memory 10 ₁ , ..., 10 _N , which were initially loaded at the stage of module setup.

The working configuration of the interface FPGA 2 should provide all the necessary control functions, which primarily include the organization of interaction via the external PCI-Express 4 port through high-speed PCI-Express 23 serial interface resources, the organization of interaction with the monitoring module of module 17, the organization of interaction with the module 9 operative rearranging memories starting configurations computing FPGA 3 _1, ..., 3 _N, organization of the interaction with the power control module and the control unit 14 and the groups th of the N individual control and power management units 11 _1, ..., 13 _N, organization of the interaction with a group of N blocks customization of operating frequencies 12 _1, ..., 12 _N computing VLSI 5 _1, ..., 5 _N, and organization operative configuration FPGA 3 ₁ , ..., 3 _N on a bi-directional common bus 24.

Starting configurations of computational FPGAs 3 ₁ , ..., 3 _N should provide interfacing of computational FPGAs 3 ₁ , ..., 3 _N via an external PCI-Express 4 port using high-speed PCI-Express 25 ₁ , ..., 25 _N serial resources, writing to memory starting configurations 10 ₁ , ..., 10 _N working configurations and organizing your own reconfiguration from the memory of starting configurations 10 ₁ , ..., 10 _N.

The working configurations of computational FPGAs 3 ₁ , ..., 3 _N should ensure what the starting configurations do, and also implement the required interfaces of interaction with the same computational VLSI 5 ₁ , ..., 5 _N for the bus group 32 ₁ , ..., 32 _N , with blocks individual setting of VLSI operating frequencies 12 ₁ , ..., 12 _N for a group of tires 31 ₁ , ..., 31 _N , with individual power control and management units 11 ₁ , ..., 11 _N for a group of tires 29 ₁ , ..., 29 _N , with individual monitoring units 13 ₁ , ..., 13 _N computing FPGAs 3 ₁ , ..., 3 _N and VLSI 5 ₁ , ..., 5 _N for a group of tires 33 ₁ , ..., 33 _N , with the aim of fully functional and independent operation of computational FPGA 3 ₁ , ..., 3 _N.

After the operating system is loaded into an external control computer, in the address space of which the proposed computation module is located, the computation FPGA 3 ₁ , ..., 3 _N and VLSI 5 ₁ , ..., 5 _N are distributed among users (tasks) who reconfigure the selected FPGA 3 ₁ , ..., 3 _N through the memory of their starting configurations 10 ₁ , ..., 10 _N working configurations. After that, the computing module is ready to solve user problems.

When solving problems, the exchange of successive data and results between computational FPGA 3 ₁ , ..., 3 _N and the control computer is performed via a high-speed PCI-Express serial interface through an external PCI-Express port 4. Each transaction is accompanied by sending computation FPGA G 3n status words about it complete, to proceed to the next transaction. In each word state computational FPGA 3 ₁ , ..., 3 _N information is mixed about the current temperature state of both the computational FPGA itself and the same computational VLSI 5 ₁ , ..., 5 _N. From the state words of the computational FPGA 3 ₁ , ..., 13 _{N of the} interface FPGA 2, a general state frame of the computation module is formed, which, depending on the monitoring system organization, can either remain in the memory of the control computer, or by means of the interface unit of the module 18 with the monitoring system through The external monitoring port of module 19 is further forwarded for storing, analyzing and deciding on the further management of the computing module. At the same time, In the latter case, the high-speed external port of the PCI-Express 4 serial interface is completely exempt from transmitting monitoring information, which, on average, increases the total interaction time of FPGAs 3 ₁ , ..., 3 _N for data and results exchange by 10-15% performing user tasks on this port, which also increases the computational performance of the module.

The most energy-consuming components of the proposed computational module are computational VLSI 5 ₁ , ..., 5 _N , having a large number of internal components and operating at high frequencies. In this regard, it is of great importance to reduce the energy costs of idling the VLSI 5 ₁ , ..., 5 _N (the time when the VLSI 5 ₁ , ..., 5 _{N is} waiting for the loading of the next data or the unloading of the finished results). On average, depending on the algorithms of the tasks being implemented, this time can reach 15-20% of the computation time (efficient operation) of the SBIS 5 ₁ , ..., 5 _N. Turning off the power from the VLSI 5 ₁ , ..., 5 _N at this time reduces the consumption by more than four times, therefore, on average, energy savings of up to 15% can be expected.

In addition, in the proposed module it is possible to turn off the power not only from the computational VLSI 5 ₁ , ..., 5 _N , but also from the corresponding computational FPGA 3 ₁ , ..., 3 _N , which is performed by the interface FPGA 2 through the module 14 to monitor and control the power supply of the module . This gives an even greater energy gain, but is possible only in the case when the corresponding computational FPGAs 3 ₁ , ..., 3 _{N are} not used to solve user problems.

Application in the proposed computational module computational VLSI 5 ₁ , ..., 5 _N , having in its composition computing resources that support software execution of a set of some labor-intensive algorithms, interaction via an Ethernet network switch 21 and the external network port of module 22 with external computing devices, as well as introduction N operational memories 20 ₁ , ..., 20 _N , connected to computational VLSI 5 ₁ , ..., 5 _N , allows not only to significantly expand the classes of tasks solved by the module due to their software implementation, but also add It is possible to relieve the external port of the PCI-Express 4 serial interface from part of the transactions that can be carried out via the network port of module 22, which also increases the time for efficient operation of computational VLSI 5 ₁ , ..., 5 _N , and accordingly increases the performance of the proposed computational module.

An EXAMPLE of the IMPLEMENTATION of the INVENTION

The proposed computing module can be performed on the following elements:

PCI-Express 1 switch - on the PEX8732 chip manufactured by PLX Technology; interface FPGA 2 and computational FPGA 3 ₁ , ... 3n - on Xilinx XC7A75T-FGG484 microcircuits;

RAM 20 ₁ , ..., 20 _N - on the chips MT46H128M16LFDD-48;

network switch 21 - on the NXP SJA1105 chip;

memory 10 ₁ , ..., 10 _N starting configurations of computational FPGAs - on chips in SPI-memory N25Q064A11EF640;

JTAG 6 monitoring and control port - using a standard MOLEX connector and a CPLD XC2C64A chip;

Memory 8 configuration FPGA - on SPI-memory N25Q032A11EF640;

monitoring units 17 and 13 ₁ , ..., 13 _N - on TMP461AIRUNT and MAX1239EEE microcircuits;

12 ₁ , ..., 12 _N computational VLSI operating frequency tuning blocks - on 570FCA000133DG microcircuits.

The proposed computational module can be implemented either as an expansion card installed in the PCI-Express slots of a universal computer motherboard, as a rule, with N <5, which is related to the allowable dimensions of the expansion cards, and as modules installed in separate enclosures and having PCI-Express input ports. Both in the first and in the second case the primary power supply of the modules, as a rule, + 12V, comes from an external connector and, as a rule, from an independent source, which is connected with a high power consumption of the modules. The only exceptions are expansion cards installed in the PCI-Express slots of universal computers in a limited number and with a small N.

Thus, the proposed computational module, in comparison with the prototype, has a higher computational power when solving computationally complex tasks that require a high intensity of information exchange of computational FPGA 3 ₁ , ..., 3 _N via an external PCI-Express 4 port, which is freed from the need to transfer information about the state of the module, by transmitting this information via the external monitoring port of module 19 and the external monitoring and control port of module 16. Also, the external PCI-Express 4 port is unloaded from the exchange of course th part of the working information, mainly software for the work of computing VLSI 5 ₁ , ..., 5 _N , due to the use for this network switch 21 and the external network port module 22.

In addition, the introduction of operational memory 20 ₁ , ..., 20 _N for buffering data, results and storing intermediate results and running programs provides the ability to use in the proposed module computational VLSI with software implementation of laborious fragments of computational algorithms, which provides an extension of the classes of computationally complex tasks to be solved compared to the prototype.

The above information allows us to conclude that the proposed computational module corresponds to the claimed technical result — an increase in computational power in solving computationally complex problems requiring high intensity of FPGA computing information exchange through an external PCI-Express port and the expansion of classes of computationally complex tasks to be solved.

Claims (1)

Computing module containing a PCI-Express 1 switchboard, interface FPGA 2, a group of N computational FPGAs 3 ₁ , ..., 3 _N , an external port of PCI-Express 4, a group of N computational VLSI 5 ₁ , ..., 5 _N , external port of control and control of the JTAG 6 module, block 7 operational configuration of the interface FPGA 2, memory 8 configuration of the interface FPGA 2, block 9 operational reconfiguration of the memory of the starting configurations of the computing FPGA 3 ₁ , ..., 3 _N , a group of N memories of the starting configurations 10 ₁ , ..., 10 _N FPGA computational 3 _1, ..., 3 _N, a group of N blocks to individual ntrolya and power control 11 _1, ..., 11 _N computing VLSI 5 _1, ..., 5 _N, the monitoring unit module 17, a group of N blocks customization of operating frequencies 12 _1, ..., 12 _N computing VLSI 5 _1, ..., 5 _N , a group of N individual monitoring units 13 ₁ , ..., 13 _N , and the ports of the PCI-Express switch 1 are connected by the corresponding high-speed PCI-Express serial interfaces to the external port of module 4, by the interface 23 to the interface FPGA 2 and by a group of N interfaces 25 ₁ , ..., 25 _N with N computational FPGA 3 ₁ , ..., 3 _N , each of which is connected by an individual and bidirectional information buses 32 ₁ , ..., 32 _N with the corresponding computational VLSI 5 ₁ , ..., 5 _N , interface FPGA 2 are connected by corresponding buses to the operational configuration block 7 of the interface FPGA 2, to the operational configuration reconfiguration block 9 of the starting configuration memory 10 ₁ , ... , 10 _N and with the monitoring module of module 17, as well as connected by a bidirectional common configuration bus 24 with N FPGA computing 3 ₁ , ..., 3 _N and a common bus 34 with N individual tuning frequency blocks 12 ₁ , ..., 12 _N , in addition , block 7 operational configuring the interface FPGA 2 is connected to the memory 8 configuration interface FPGA 2 and an external port control and JTAG 6 module control unit operative rearranging memories 9 is connected to the common bus 26 with N memories starting configurations 10 _1, ..., 10 _N computing FPGA January _3, ... , 3 _N , with N computational FPGAs 3 ₁ , ..., 3 _N connected to the corresponding memory of the same name N starting configurations 10 ₁ , ..., 10 _N group of N individual reconfiguration tires 28 ₁ , ..., 28 _N and a group of N individual tires operational reconfiguration 27 _1, ..., 27 _N, as a group of N individual buses 29 _1, ..., 29 _N of control and power management of computing VLSI 5 _1, ..., 5 _N are connected to a group of N individual control and power management units 11 _1, ..., 11 _N, furthermore, N blocks individual settings of working frequencies 12 ₁ , ..., 12 _{N are} connected by corresponding buses to the same VLSI groups of N computational VLSI 5 ₁ , ..., 5 _N and a group of N individual bus settings of working frequencies 31 ₁ , ..., 31 _N with corresponding computational FPGAs 3 _1, ..., _N 3, monitoring block module 17 is connected to the common bus 35 with N Individuals nymi units monitor 13 _1, ..., 13 _N, each of which is connected to the same corresponding computing FPGA 3 _1, ..., 3 _N individual tire monitor 33 _1, ..., 33 _N, characterized in that it additionally introduced Ethernet network switch 21 , group of N operative memories 20 ₁ , ..., 20 _N , module 14 monitoring and power control unit, module interfacing unit with power monitoring and control system 15, module interfacing unit with monitoring system 18, external network port of module 22, external monitoring port module 19, external control port and power management module 16, with a group of N operational memories 20 ₁ , ..., 20 _N connected to the corresponding buses with the same computing VLSI 5 ₁ , ..., 5 _N , which are connected by the corresponding network interfaces 36 ₁ , ..., 36 _N with an Ethernet switch 21, which is also connected to the external network port of the module 22, in addition, the power control and management unit of the module 14 is connected to the FPGA 2 interface, and the common bus 30 is connected to the N individual power control and management units 11 ₁ , ..., 11 _N VLSI 5 ₁ , ..., 5 _N and connected The module 17 is connected to the module interface to the monitoring system 18, which is connected to the external monitoring port of module 19.

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