CN101211330B - Programmable instruction set computer integrated circuit - Google Patents
Programmable instruction set computer integrated circuit Download PDFInfo
- Publication number
- CN101211330B CN101211330B CN2006101554274A CN200610155427A CN101211330B CN 101211330 B CN101211330 B CN 101211330B CN 2006101554274 A CN2006101554274 A CN 2006101554274A CN 200610155427 A CN200610155427 A CN 200610155427A CN 101211330 B CN101211330 B CN 101211330B
- Authority
- CN
- China
- Prior art keywords
- output
- configuration
- control circuit
- register
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
A programmable instruction set computer integrated circuit relates to a dynamic field programmable integrated circuit capable of partially or completely changing a logic circuit, which solves the difficulty in dynamic reuse of the programmable integrated circuit. A logic unit can be reconfigured during normal operation of FPGA by adding a group of temporary configuration register, a configurationcontrol circuit, a dynamic configuration clock and an allowable configuration register. An output circuit can be controlled by adding a dynamic allowable output control circuit, a dynamic control output clock, an allowable output register and an output register to obviate the influence on the programmable integrated circuit in the reconfiguration process. The integrated circuit can be widely applied in occasions such as image processing, network processors, programmable instruction set computers, grid blade servers, trusted computers and trusted routers.
Description
One, technical field
The present invention relates to a kind of programmable integrated circuit, particularly relate to a kind of at the normal integrated circuit that can dynamically change logical circuit in service.
Two, background technology
The FPGA of present altera corp and the FPGA (field-programmable integrated circuit) of Xilinx company, utilize SRAM (static memory) to be configured, when reconfiguring the logic of FPGA, FPGA quits work, wait to finish all circuit arrangement, after verification was passed through, FPGA carried out work by new configuration logic.
The fpga logic of altera corp partly adopts embedded Array piece (EAB), " Design of Digital System and the Verilog HDL " that can write with reference to Wang Jinming etc., Electronic Industry Press in January, 2002 first published 74-76 page or leaf.
Fig. 1 is a prior art, the inner structure of the FPGA of the Clone of altera corp, 101 are I/O controll block, 102 is PLL (programmable phase-locked loop) module, 103 is the inner block SRAM of FPGA, 104 is EAB (embedded Array piece), utilizes general or local cabling to be connected between the various functional modules, and general or local cabling is to realize by programming.
Two kinds of SRAM are arranged among the FPGA of the Clone series of attention: Altera: configuration SRAM, this SRAM is opaque to the user, and the user can not use, and the program of FPGA promptly is configured among the configuration SRAM.Another is SRAM BLOCK (block SRAM), uses for the user.
It is the main logical resource of synchronizing circuit and combinational circuit that the fpga logic of Xilinx company partly adopts configurable logic block CLB (Configuration Logic Bloack configuration logic)." based on the Embedded System Design of FPGA " that specific description is seen Xu Xin, write in red flag etc., China Machine Press's in January, 2005 first published, 21-23 page or leaf, 47-48 page or leaf." the senior application and the design tactics of Xilinx programmable logic device (PLD) " that Sun Hang writes, Electronic Industry Press in August, 2004 first published 22-26 page or leaf.
The configuration circuit of prior art: the configuration circuit with existing Altera is illustrated, Altera has following several mode that FPGA is configured: passive serial downloading mode, quick passive parallel mode, passive parallel asynchronous system, passive parallel synchronous mode, passive serial asynchronous system, JTAG mode." Altera FPGA/CPLD design " basis piece of writing that can write with reference to Wang Cheng etc., People's Telecon Publishing House's in July, 2005 first published.The 187-213 page or leaf.
The process (state machine) of Altera configuration: see Fig. 3,
FPGA powers on: nSTATUS and CONF_DONE signal step-down, all I/O pins are high resistant, remove the information among all configuration SRAM.
It is low that reset signal is that low level: nSTATUS and CONF_DONE signal remain, and removes the configuration signal among all SRAM.
Configuration SRAM information: nCONFIG or CONF_DONE are high level, and configuration data is written among the configuration SRAM of FPGA.
Initialization: the internal logic circuit initialization, initialization of register, the I/O initialization, input/output driver is effective.
Enter the user and normally use pattern.
Altera download state machine figure sees Fig. 3, and this figure takes from " Altera FPGA/CPLD design " basis piece of writing that Wang Cheng etc. writes, People's Telecon Publishing House's in July, 2005 first published.The 191st page (figure on the book is the English Chinese that has been translated as in the accompanying drawings).
Three, summary of the invention
1, new definition noun:
(1) dynamic-configuration clock (DCCLK Dynamic Configuration Clock): increased a dynamic-configuration circuit clock in the present invention, but the band of this clock synchro control configuration control circuit allows the synchronous d type flip flop of output terminal.
(2) dynamically control the output clock: increase a dynamically control output clock in the present invention, this clock synchronization is controlled the synchronous d type flip flop of the band permission output terminal of all functional units.Dynamic-configuration clock and dynamic control output clock can be same, also can be two different clocks.
(3) functional unit: in the dynamically programmable integrated circuit, can finish the unit of certain function after the configurations such as local cabling, general cabling, embedded Array piece, I/O piece able to programme, SRAM piece, digital signal processing block, multiplier, we claim that it is " functional unit ".
(4) dispensing unit: in the dynamically programmable integrated circuit, all can carry out again the function of configuration logic separately to each " functional unit ", we claim that it is " dispensing unit " configuration circuit of these unit, dispensing unit by the provisional configuration register, allow configuration register, dispose control circuit, be configured SRAM and form.
(5) dynamically programmable integrated circuit (DFPGA Dynamic Field-programmable Gate Array): a kind of field programmable logic circuit, the function of the part of reconfigurable inside " functional unit " when its integrated circuit normally moves, and can preserve intermediate result, other parts still can normally be moved; Or reconfigure whole " functional unit ", and keep the integrated circuit of intermediate result.
2, the problem that will solve
The deficiencies in the prior art: present FPGA can not be when the FPGA operate as normal, a part of circuit of change programmable integrated circuit, and the other parts circuit still can operate as normal.Or whole circuit of change FPGA, and the result of last operation still can normally preserve.
The objective of the invention is for provide a kind of can be at the logical circuit of operate as normal time change programmable integrated circuit.Can change a part of circuit of programmable integrated circuit, also can change whole circuit of programmable integrated circuit.The following one-period of this change partial dynamic configurable clock generator will operate as normal.
3, technical scheme
201 for I/O controll block as shown in Figure 2, and 202 is PLL (PLL module), and 203 is block SRAM, and 204 is EAB (embedded Array piece), more than identical with prior art.
3.1 dynamically programmable integrated circuit configuration state machine:
The present invention's's " dynamically programmable integrated circuit " layoutprocedure state machine (see figure 4) 401 for power on or RESET (low level is effective) effective: remove all configuration datas, input/output module is a high resistant;
402 are the dynamically programmable integrated circuit configuration data first time: FPGA was effective after configurating programmable array block, PLL, I/O controll block, block SRAM finished all configurations, operate as normal.
403 for reconfiguring: when one " dynamic-configuration clock " arrived, the data in the provisional configuration register sent to " dispensing unit " under the effect that allows configuration register and control circuit.Under the effect of configurable clock generator, constantly reconfigure, logical circuit was with regard to the energy operate as normal after the configuration of " dynamic-configuration clock " was finished, and the functional unit that does not reconfigure is operate as normal always.
3.2 dynamic reconfigurable control circuit:
Can constantly reconfigure circuit when the integrated circuit operate as normal in order to reach by demand.The following control module that the present invention increases, 205 for disposing the connecting line of exporting to " dispensing unit ", 206 for reconfiguring control circuit (band allows the synchronous d type flip flop of output control terminal), 207 are configuration permission configuration register output line, 208 for allowing configuration latch, 209 is (dynamic-configuration clock) clock output line, 210 is the dynamic-configuration clock, 211 is EAB logical consequence output line, 212 for allowing output register, and 213 is output control logic circuit (band allows the synchronous d type flip flop of output control terminal), and 215 is dynamic control clock output line, 214 for exporting line as a result, and 216 is that dynamically clock is controlled in output.
As shown in Figure 5, be " dispensing unit " forming circuit:
501 is the provisional configuration register, and 502 are the configuration control circuit, and 503 for allowing configuration register, and 504 is synchronous reconfigurable clock connecting line, and 506 is the dynamic-configuration clock, and 505 are configured SRAM for DFPGA.
502 synchronous d type flip flops for band permission output terminal, 1 pin is the input end of d type flip flop, and 2 pin are the output terminal of d type flip flop, and 3 pin are the input pin of d type flip flop synchronous clock, and 4 pin are the permission output control terminal of d type flip flop.
502 1 pin connects provisional configuration register 501, in FPGA, general cabling, local cabling, embedded Array piece, I/O controll block, multiplier, digital signal processing module is arranged.Write the address to each " dispensing unit " all " provisional configuration register " positions are unified, download to the serial or parallel way in " the provisional configuration register " of each " functional unit ".
502 4 pin connect the permission configuration register, each " dispensing unit " has one to allow configuration register, allow configuration register corresponding one by one with " provisional configuration register ", allow the data configuration of configuration register also to adopt independent addressing, the address of the permission configuration register of each unit is all inequality, downloads to the serial or parallel way in " the permission configuration register " of each " functional unit ".
502 3 pin connect " dynamic-configuration clock ", when the provisional configuration register data is ready to, after the data of permission register also have been ready to, when the rising edge of dynamic-configuration clock arrives, if allowing configuration register is 0 (promptly effective), the data of configuration register output to being configured among the SRAM of dynamically programmable integrated circuit by 2 pin of control circuit promptly under the effect of synchronous clock.
When part allows configuration register data is 0, after arriving, can realize the configurable clock generator rising edge reprogramming to the partial circuit of dynamically programmable integrated circuit, when all dispensing unit positions that allow configuration register are when effective (when allowing the value of configuration register all to be 0), can realize that the dynamically programmable integrated circuit all reconfigures.
Thereby realize when being implemented in dynamically programmable integrated circuit operate as normal the partial circuit of dynamically programmable integrated circuit or the reprogramming of whole circuit.
3.3 output control circuit:
3.3.1 the effect of output control circuit:
(a) because part " functional unit " reconfigures, the uncertain attitude of output of a period of time may occur during disposing, other circuit of the logical and of uncertain attitude connects may produce inscrutable result, may cause the damage of circuit.After having increased output control circuit, part is reshuffled in the unit, data to output latch, its result is constant during whole configuration, therefore phase mutual interference between the different units can not take place, for what whole chips were reconfigured, this output latch can latch intermediate result, uses for reconfiguring the back.
(b) increase the intermediate result that to store " functional unit " output that obtains before reconfiguring behind the output control circuit, increased the dirigibility of system greatly, can realize the programmable instructions set processor.
3.3.2 the realization circuit of output control circuit:
As shown in Figure 6, output control circuit is exported by 601 " functional units ", 602 output control circuits, and 603 is the output connecting line as a result of output control circuit, and 604 for allowing output register, and 605 be the dynamic clock connecting line, and 606 be dynamically to control to export clock.
Among Fig. 6 606 be 506 dynamic-configuration clocks among control output clock and Fig. 5 dynamically, can use same clock, also can be with different clocks.
602 bands allow the synchronous d type flip flop of output terminal, and 1 pin is an input end, and 2 pin are output terminal, and 3 pin are the synchronous clock input end, and 4 pin are for allowing the output register control end.
602 1 pin is connected to " functional unit " output connecting line, and " functional unit " can be the output signal of general cabling, local cabling, embedded Array piece, I/O controll block, digital signal processing block, multiplier, block SRAM piece.
602 2 pin are output pin, are connected to local cabling or general cabling by 603 lines.
602 3 pin are the synchronous clock input pin of d type flip flop, connect dynamically control output clock by clock trees, and are effective when being input as rising edge.
602 4 pin are that d type flip flop allows output pin, are connected to and allow the output register output pin, allow output when allowing register to be output as low level, the last result who carries out of output latch when allowing register to be high level.
604 for allowing output register, and unified addressing is adopted in input, and the method that adopts serial or parallel is to this register assignment, and output terminal is connected to 602 4 pin, and whether control circuit output is effective.
3.4 principle of work:
For fear of realizing dynamically programmable circuit the influencing each other of circuit at circuit part or when all disposing, the present invention has increased output control circuit.When part reconfigured circuit, band allowed the result of the synchronization caching register holds last time of output terminal, reconfigures under the effect of configuration synchronization clock.Pei Zhi circuit still can operate as normal.Whether the circuit to this unit reconfigures the control that is allowed configuration register.All permission configuration bits are all effective, can under the synchronous effect of configurable clock generator, reconfigure all circuit of whole dynamically programmable integrated circuit, the intermediate result of this unit output can be kept in the d type flip flop before the configuration, uses this intermediate result after the configuration of power supply road is finished.
4, beneficial effect
Integrated circuit of the present invention can be when the integrated circuit operate as normal, a part of logical circuit of entire circuit or circuit is reconfigured, and only reconfiguring of whole FPGA needed a configurable clock generator cycle; In layoutprocedure, do not need the circuit that reconfigures still can operate as normal, the circuit that need reconfigure can be preserved last result of calculation.And unlike existing FPGA at configuration device, device logic cisco unity malfunction in layoutprocedure, treating to dispose fully could operate as normal after finishing, and can not preserve last result of calculation.
The present invention can realize dynamically reconfiguring of FPGA, thereby realizes FPGA hardware circuit reconstruct and reuse, and has improved the utilization factor of silicon chip, has improved performance of integrated circuits, and the while has been expanded the purposes of FPGA greatly.
Four, description of drawings
Fig. 1 represents the Clone FPGA circuit structure diagram of prior art altera corp.
Fig. 2 represents the FPGA circuit structure diagram of dynamically programmable integrated circuit of the present invention.
Fig. 3 represents the FPGA configuration state machine of altera corp.
Fig. 4 represents configuration state machine of the present invention.
Fig. 5 represents " dispensing unit " control circuit.
Fig. 6 represents output control circuit.
Fig. 7 represents to dispose the preferred embodiment of different situations of permission control end, the synchronous clock input end of control circuit, output control circuit.
Fig. 8 represents the array configurations circuit.
Fig. 9 represents the array output control circuit.
Five, embodiment
Below by preferred embodiment the present invention is further specified.
1, band allows the permission output control terminal of the synchronous d type flip flop of output terminal, the different preferred embodiments of synchronous input clock:
Briefly, the input end of clock at d type flip flop adds a reverser exactly, can realize, and is effective when clock input signal becomes negative edge by original rising edge is limited; Permission input end at d type flip flop adds a d type flip flop, allows output by original low level, allows output when becoming high level.The d type flip flop circuit of configuration circuit and output control circuit is identical, so this preferred embodiment both had been applicable to that configuration circuit also was applicable to output control circuit.
As shown in Figure 7,701 synchronous d type flip flops for band permission output terminal, 703 are the input connecting line, 705 are the output connecting line, 702 add a reverser for the synchronous clock input end, 704 for allowing output control terminal to add a reverser, and 706 is the synchronous clock connecting line, and 707 for allowing the output connecting line.
3 pin configurable clock generator input ends of " configuration circuit " 502 are connected on the dynamic-configuration clock 506 by 504 among Fig. 5, and when clock was input as rising edge, band allowed the synchronous d type flip flop of output terminal to export synchronously.After 701 3 pin connecting lines increased by 702 reversers, 706 bands during for negative edge allowed the synchronous d type flip flop of output terminal that synchronizing signal output is arranged among Fig. 7.
4 pin of " configuration circuit " 502 are connected to 503 and allow the configuration register output terminal among Fig. 5, and when allowing configuration register to be output as low level, band allows synchronous d type flip flop energy output signal under the effect of synchronous clock of output terminal.The output band allows the synchronous d type flip flop of output terminal invalid when allowing configuration register for high level.Allow the permission output terminal of the synchronous d type flip flop of output terminal to increase a reverser 704 at band among Fig. 7 and can realize that this band allows the synchronous d type flip flop of output terminal effective when 707 are input as high level, this band allows the synchronous d type flip flop of output terminal not send data when 707 are input as low level, but latchs the result who carried out last time.
Output control circuit is identical with the configuration control circuit, no longer narration.
2, dynamic reconfigurable control circuit disposes block SRAM, general cabling, local cabling, embedded Array piece, multiplier, digital signal processing block array configurations circuit:
Briefly: in the practical application, realize a configuration circuit ground function, be not one and just can deal with problems, need the multidigit parallel function of just finishing that combines, identical with regard to the description with 3.2, what only multidigit was parallel simultaneously finishes.
To general cabling, local cabling, block SRAM, embedded Array piece, multiplier, digital signal processing block, I/O piece is not that a configuration bit is just passable, generally needs a plurality of configuration bits.
As shown in Figure 8, be a plurality of configuration bit arrays.
801 is the provisional configuration registers group, and 804 is first control circuit, and 803 is second control circuit, and 802 is n road control circuit, and 805 for being configured registers group, and 806 is the dynamic-configuration clock, and 807 for allowing groups of configuration registers.
801 is the provisional configuration registers group, the provisional configuration registers group adopts step-by-step to address separately or the provisional configuration registers group is addressed as a parallel register, by serial ports or parallel port to the temporary register assignment, the output of registers group is connected respectively to 1 of d type flip flop group control circuit one by one and arrives the n position, and output valve is delivered to the input end that band allows the synchronous d type flip flop group of output terminal.
804,803,802 is the array control circuit, and input end is connected respectively to each position of provisional configuration registers group; 804, the input end of clock of 803,802 control circuit array group links together and is connected on the 806 dynamic-configuration clocks; 804,803,802 output terminal be connected respectively to 805 be configured registers group each the position; 804,803,802 permission output terminal is connected respectively on each position that allows groups of configuration registers.
805 input ends that are configured registers group are connected respectively to the output terminal that control configuration band allows the synchronous d type flip flop group of output terminal.
807 allow groups of configuration registers employing step-by-step addressing or by registers group unified addressing method, utilize the serial or parallel method to carry out assignment to allowing configuration register; Allow groups of configuration registers, output is connected to the permission output terminal that 804,803,802 bands of forming allow the synchronous d type flip flop group of output terminal.
When the dynamic-configuration clock is output as rising edge, allowing the control bit of the correspondence of output register group is 0 o'clock synchronous d type flip flop, and the data of its input are directly exported; Corresponding permission output register is 1 position, and it exports the constant intermediate result that latchs.
3, dynamic reconfigurable control circuit configure generic cabling, local cabling, block SRAM, embedded logic piece, multiplier, digital signal processing block array output control circuit:
Briefly: be exactly by the multidigit output control circuit is formed an array, realize that multi-bit parallel handles simultaneously.
General cabling, local cabling, block SRAM, embedded Array piece, multiplier, digital signal processing block, I/O piece are had plenty of an output, have plenty of multi-bit parallel output.Fig. 9 is for solving the preferred embodiment that multidigit is exported simultaneously.
901 is multidigit functional unit output register group as shown in Figure 9,904 is first via output control circuit, 903 is the second road output control circuit, 902 is n road output control circuit, 905 are first via output line, and 908 is the second tunnel output line, and 909 is n road output line, 906 is that dynamically clock is exported in control, and 907 for allowing the output register group.
901 multidigit functional unit output register groups are connected to the parallel control output array of controls of forming such as 904,903,902 respectively.
904,903,902 for utilizing band to allow the output array of controls of the synchronous d type flip flop composition of output terminal.Input pin is connected respectively to each position in 901.Input end of clock links together and is connected to dynamic control output clock.Allow input end to be connected respectively to each position of 907 permission output register groups.
904,903,902 output terminal 905,908,909 is connected respectively on local cabling or the general cabling.
907 for allowing the output register group, allow the output register group to adopt step-by-step addressing or the as a whole addressing of registers group separately, configuration allows the output register data under the employing serial mode that step-by-step addresses separately, by the employing parallel mode data download of registers group unified addressing.The output circuit of permission output register group is connected respectively to the permission output control terminal of synchronous d type flip flop array.
Claims (1)
1. programmable instruction set computer integrate circuit, comprise: local cabling, general cabling, embedded Array piece, input/output module able to programme, digital dock manager or programmable phase-locked loop, block storage, multiplier, digital signal processor module is characterized in that:
Each dispensing unit of local cabling in programmable integrated circuit, general cabling, embedded Array piece, I/O piece, multiplier, digital signal processing block, block SRAM increases the configuration control circuit: allow synchronous d type flip flop, the dynamic-configuration clock circuit of output terminal to form by provisional configuration register, permission configuration register, band;
Each output unit increase output control circuit of local cabling in programmable integrated circuit, general cabling, embedded Array piece, I/O piece, multiplier, digital signal processing block, block SRAM: allow the synchronous d type flip flop of output terminal, dynamic control to export clock by functional unit output, permission output register, band and form;
Annexation in the configuration control circuit that increases in each dispensing unit: the dynamic-configuration clock circuit is connected to the synchronous clock input end that the band that disposes control circuit allows the synchronous d type flip flop of output terminal; Adopt unified addressing in each dispensing unit of provisional configuration register, the way by serial or parallel is to this provisional configuration register assignment; The provisional configuration register is directly connected to the input end that the band that disposes control circuit allows the synchronous d type flip flop of output terminal; In a slice programmable instruction set computer integrate circuit all allow the configuration register unified addressing, utilize the way of serial or parallel to carry out assignment to allowing configuration register, the permission configuration register directly connects the permission output terminal that the band that disposes control circuit allows the synchronous d type flip flop of output terminal; The band of configuration control circuit allows the output terminal of the synchronous d type flip flop of output terminal to connect the SRAM that is configured of integrated circuit;
Annexation in the output control circuit that increases in each output unit: the functional unit of output control circuit is output as the output terminal of local cabling, general cabling, input/output module, multiplier, digital signal processing module, block SRAM, and its band that is connected output control circuit allows the input end of the synchronous d type flip flop of output terminal; The band of output control circuit allows the output terminal of the synchronous d type flip flop of output terminal to be connected to other functional unit by general or local cabling; In a slice integrated circuit, allow output register to adopt unified addressing, utilize the way of serial or parallel that this permission output register is carried out assignment, the band that allows the output terminal of output register to be connected to output control circuit allows the permission output terminal of the synchronous d type flip flop of output terminal; The band that dynamic control output clock is connected to output control circuit allows the synchronous clock input end of the synchronous d type flip flop of output terminal;
The course of work of configuration control circuit: when the provisional configuration register data is ready to, after the data of permission configuration register also have been ready to, when the rising edge of dynamic-configuration clock arrives, if allow configuration register effective, the data of provisional configuration register promptly under the effect of synchronous clock, allow the output terminal of the synchronous d type flip flop of output terminal to output to being configured among the SRAM of integrated circuit by the control circuit band;
The course of work of output control circuit: when allowing output register to be output as low level, allow output, the last result who carries out of output latch when allowing output register to be high level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101554274A CN101211330B (en) | 2006-12-25 | 2006-12-25 | Programmable instruction set computer integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101554274A CN101211330B (en) | 2006-12-25 | 2006-12-25 | Programmable instruction set computer integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101211330A CN101211330A (en) | 2008-07-02 |
| CN101211330B true CN101211330B (en) | 2010-10-13 |
Family
ID=39611364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101554274A Expired - Fee Related CN101211330B (en) | 2006-12-25 | 2006-12-25 | Programmable instruction set computer integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101211330B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010034167A1 (en) * | 2008-09-28 | 2010-04-01 | 北京大学深圳研究生院 | Processor structure of integrated circuit |
| CN101727434B (en) * | 2008-10-20 | 2012-06-13 | 北京大学深圳研究生院 | Integrated circuit structure special for specific application algorithm |
| CZ302549B6 (en) * | 2009-07-03 | 2011-07-07 | Cesnet | Circuit arrangement for quick modification of configuration content of circuits fitted with logic arrays connected directly to computer communication interface |
| CN105278394B (en) * | 2014-07-18 | 2019-01-25 | 京微雅格（北京）科技有限公司 | Parallel deployment circuit and method based on FPGA |
| CN104750481B (en) * | 2015-03-10 | 2018-04-17 | 深圳大学 | A kind of FPGA output pins multiplex circuit, method and apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6481000B1 (en) * | 1997-10-16 | 2002-11-12 | Altera Corporation | Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits |
| CN1881804A (en) * | 2005-05-19 | 2006-12-20 | 英飞凌科技股份公司 | Circuit arrangement for supplying configuration data in FGPA devices |
| CN201004227Y (en) * | 2006-12-25 | 2008-01-09 | 顾士平 | Dynamic programmable integration circuit |
-
2006
- 2006-12-25 CN CN2006101554274A patent/CN101211330B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6481000B1 (en) * | 1997-10-16 | 2002-11-12 | Altera Corporation | Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits |
| CN1881804A (en) * | 2005-05-19 | 2006-12-20 | 英飞凌科技股份公司 | Circuit arrangement for supplying configuration data in FGPA devices |
| CN201004227Y (en) * | 2006-12-25 | 2008-01-09 | 顾士平 | Dynamic programmable integration circuit |
Non-Patent Citations (2)
| Title |
|---|
| CN 201004227 Y,权利要求1-10. |
| JP特开平8-330945A 1996.12.13 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101211330A (en) | 2008-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7518396B1 (en) | Apparatus and method for reconfiguring a programmable logic device | |
| US10693469B2 (en) | Multiplier-accumulator circuit, logic tile architecture for multiply-accumulate, and IC including logic tile array | |
| US8575959B2 (en) | Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics | |
| CN105279133A (en) | VPX parallel DSP signal processing board card based on SoC online reconstruction | |
| US9584130B1 (en) | Partial reconfiguration control interface for integrated circuits | |
| CN101211330B (en) | Programmable instruction set computer integrated circuit | |
| US7765382B2 (en) | Propagating reconfiguration command over asynchronous self-synchronous global and inter-cluster local buses coupling wrappers of clusters of processing module matrix | |
| JPH09181599A (en) | Time-multiplexed write enabled logic circuit | |
| Iturbe et al. | Methods and mechanisms for hardware multitasking: Executing and synchronizing fully relocatable hardware tasks in Xilinx FPGAs | |
| EP3223430B1 (en) | Systems and methods for configuring an sopc without a need to use an external memory | |
| CN110989417B (en) | Period detection system adaptive to FPGA local reconstruction | |
| Gericota et al. | Run-time management of logic resources on reconfigurable systems | |
| US20020010825A1 (en) | Memory resource arbitrator for multiple gate arrays | |
| Paulsson et al. | Implementation of a virtual internal configuration access port (JCAP) for enabling partial self-reconfiguration on Xilinx Spartan III FPGAs | |
| Figuli et al. | A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion | |
| CN201004227Y (en) | Dynamic programmable integration circuit | |
| US11960734B2 (en) | Logic fabric based on microsector infrastructure with data register having scan registers | |
| RU2686004C1 (en) | Computing module | |
| Tsuruta et al. | Accelerator-in-switch: a framework for tightly coupled switching hub and an accelerator with FPGA | |
| Schuck et al. | An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex‐FPGAs for Organic Computing | |
| Möller et al. | A NoC-based infrastructure to enable dynamic self reconfigurable systems | |
| US9672307B2 (en) | Clock placement for programmable logic devices | |
| CN107526707A (en) | Programmable system on chip | |
| JP2006303730A (en) | Semiconductor integrated circuit device, and design apparatus for semiconductor integrated circuit device | |
| US7356454B2 (en) | Method and apparatus for emulation of logic circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101013 Termination date: 20151225 |
|
| EXPY | Termination of patent right or utility model |