CN103678751A - Processor chip simulation debugging system - Google Patents
Processor chip simulation debugging system Download PDFInfo
- Publication number
- CN103678751A CN103678751A CN201210362757.6A CN201210362757A CN103678751A CN 103678751 A CN103678751 A CN 103678751A CN 201210362757 A CN201210362757 A CN 201210362757A CN 103678751 A CN103678751 A CN 103678751A
- Authority
- CN
- China
- Prior art keywords
- user
- data
- program
- reset
- development environment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a processor chip simulation debugging system which comprises a simulator and an integrated development environment module on a user computer. The simulator comprises a simulation management module, a simulation chip and a program data storage unit, the integrated development environment module is connected with the simulation management module of the simulator through a communication channel, the simulation management module is connected with the program data storage unit and the simulation chip through a data/address bus, and the integrated development environment module is provided with a data information initialization configuration window. A target data configuration file and a target address are required to be downloaded at the same time when downloading of a user program is configured by a user, and the target data configuration file and the target address are required to be downloaded again when resetting of the simulator is configured by the user. The processor chip simulation debugging system can automatically complete downloading of configured data information according to the configuration conditions of the user.
Description
Technical field
The present invention relates to a kind of processor chips emulation debugging system.
Background technology
The user program that has User Exploitation in processor chips, in the writing and debug of user program, the instrument using is generally the debugging software on processor chips emulator and user computer---Integrated Development Environment, the artificial debugging of both interactive communication completing user programs.In Integrated Development Environment, be download, the software platform of debug user programs and the interface of debugging operations, can completing user code download in emulator, control emulator reset, in the watch window of data field download data files to operations such as emulators.
Different from actual product chip, in order to guarantee versatility and to meet the data modification requirement in user's debugging, consider the factors such as serviceable life, access speed simultaneously, in emulator, typically use volatile memory (for example SRAM) storer in equivalent substitute products chip (comprising program, data-carrier store) function.
In actual work, before using emulator debug user program, first to download in the program storage of emulator by Integrated Development Environment completing user code.Some initialized configuration data needs user manually to complete in Integrated Development Environment to download to assigned address in emulator data-carrier store.While restarting to debug, downloaded after personal code work, these initial configuration data all need again to download once at every turn; Some initialized configuration data not only need to be downloaded once to data field after having downloaded personal code work, after also need to controlling user emulator and user program by Integrated Development Environment and resetting, and external factor (reset signal, make mistakes automatically reset etc.) triggers after emulator and user program reset and all again downloads once described configuration data.For example, the data such as dealing money of smartcard processor chip in public transport application, in the debugging of user program, download user code again at every turn, restarting needs to download in a dealing money data to data storer (mass transit card enters the original state before transaction) before debugging; In debug process, when emulator and user program reset (debugging, user program operation or card reader make a mistake to trigger and reset), user also wishes, according to the needs of debugging, to select download initializes dealing money data again sometimes.
In existing emulation debugging system, after above-mentioned configuration data information all needs user artificially to judge the download of user program code or after user program reset, whether to download, and in Integrated Development Environment, manually complete down operation, not only affect debugging efficiency, also easily caused careless omission and mistake.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of processor chips emulation debugging system, can automatically according to user's configuring condition, complete the download of configuration data information.
For solving the problems of the technologies described above, processor chips emulation debugging system of the present invention, comprising: the Integrated Development Environment module on emulator and user computer; Described emulator comprises simulation management module, emulation chip and program data memory; Described Integrated Development Environment module is connected with the simulation management module of emulator by communication channel; Described simulation management module is connected by data/address bus with emulation chip with program data memory;
In described Integrated Development Environment module, there is data message initial configuration window, while being downloaded by user's configure user program, target data configuration file and the destination address that need to download simultaneously, and while resetting (comprising reset that user initiates from Integrated Development Environment module, the reset that user program is initiated and the reset that triggers from the external reset signal emulator) by user's configuring simulator, target data configuration file and the destination address that need to again download.
When the external reset signal from outside emulator inputs to emulation chip, require emulation chip and user program to reset, or user program is carried out while initiating emulation chip and user program reset, described emulation chip is to a reseting mark signal of simulation management module output, simulation management module is informed Integrated Development Environment module by communication channel, and emulator and user program reset.
The destination address of user program code, target data configuration file and download that described Integrated Development Environment module is downloaded needs by communication channel passes to simulation management module; Described simulation management module is written to user program code or target data configuration file in the program area or data area of assigned address in program data memory by data/address bus; Described emulation chip reads user program and data from program data memory by data/address bus.
Adopt the present invention, only need user to complete once configuration, will be when personal code work be downloaded, and after emulator and user program reset, automatically according to user's configuring condition, complete the download of configuration data information.Contribute to user efficiently, debug user programs reliably.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Accompanying drawing is processor chips emulation debugging system structural representation.
Embodiment
Shown in accompanying drawing, described processor chips emulation debugging system, comprises in the present embodiment: the Integrated Development Environment module 5 on emulator 1 and user computer.
Described emulator comprises simulation management module 3, emulation chip 2 and program data memory 4.Described Integrated Development Environment module 5 is connected with the simulation management module 3 of emulator 1 by communication channel 7.Described simulation management module 3 is connected by data/address bus 8 with program data memory 4, and described data/address bus 8 is connected with emulation chip 2 simultaneously.
In described program data memory 4, deposit user program and user data.Described emulation chip 2 can be to a reseting mark signal 9 of simulation management module 3 outputs.The input end of emulation chip 2 has the external reset signal 10 from emulator 1 outside input.In described Integrated Development Environment module 5, there is data message initial configuration window 6, while being downloaded by user's configure user program, target data configuration file and the destination address that need to download simultaneously, and while resetting (comprising reset that user initiates from Integrated Development Environment 5, the reset that user program is initiated and the reset that triggers from the external reset signal 10 emulator 1) by user's configuring simulator 1, target data configuration file and the destination address that need to again download.
Like this, when user's download user program code, first described Integrated Development Environment module 5 passes to simulation management module 3 by communication channel 7 user program code and destination address, by simulation management module 3, by data/address bus 8, is written to the user program region in program data memory 4.Then, if Integrated Development Environment module 5 is according to the user's configuration in data message initial configuration window 6, find that there is the target data configuration file that need to simultaneously download, by communication channel 7, target data configuration file and the destination address of user's appointment in data message initial configuration window 6 are passed to simulation management module 3 again, by simulation management module 3, by data/address bus 8, be written to the user data area in program data memory 4; Need to be after user program have not been downloaded, then by the manual download configuration data message in Integrated Development Environment module 5 of user.The downloading process of above-mentioned data configuration information is sightless for user.
If user initiates the reset operation to emulator 1 and user program in described Integrated Development Environment module 5, Integrated Development Environment module 5 can be according to user's configuration, by communication channel 7, the target data configuration file that needs again to download after the reset of user's appointment in data message initial configuration window 6 and destination address are passed to simulation management module 3, by simulation management module 3, by data/address bus 8, be written to the user data area in program data memory 4, do not need user after emulator 1 and user program reset, manual download configuration data message in Integrated Development Environment module 5.
If have from the external reset signal 10 outside emulator 1 and input to emulation chip 2, require emulation chip 1 and user program to reset, or user program is carried out while initiating emulation chip 1 and user program reset, emulation chip 1 is to a reseting mark signal 9 of simulation management module 3 outputs, simulation management module 3 is informed Integrated Development Environment module 5 by communication channel 7, and emulator 1 and user program reset.Integrated Development Environment module 5 can be according to user's configuration, by communication channel 7, the target data configuration file that needs again to download after the reset of user's appointment in data message initial configuration window 6 and destination address are passed to simulation management module 3, by simulation management module 3, by data/address bus 8, be written to the user data area in program data memory 4.This process does not need the artificial judgement of user completely and manually completes the down operation again of configuration data information.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. a processor chips emulation debugging system, comprising: the Integrated Development Environment module on emulator and user computer; Described emulator comprises simulation management module, emulation chip and program data memory; Described Integrated Development Environment module is connected with the simulation management module of emulator by communication channel; Described simulation management module is connected by data/address bus with emulation chip with program data memory;
It is characterized in that: in described Integrated Development Environment module, there is data message initial configuration window, while being downloaded by user's configure user program, target data configuration file and the destination address that need to download simultaneously, and while being resetted by user's configuring simulator, target data configuration file and the destination address that need to again download.
2. the system as claimed in claim 1, is characterized in that: described reset comprises reset, the reset that user program is initiated and the reset triggering from the external reset signal outside emulator that user initiates from Integrated Development Environment module.
3. the system as claimed in claim 1, it is characterized in that: when the external reset signal from outside emulator inputs to emulation chip, require emulation chip and user program to reset, or user program is carried out while initiating emulation chip and user program reset, described emulation chip is to a reseting mark signal of simulation management module output, simulation management module is informed Integrated Development Environment module by communication channel, and emulator and user program reset.
4. the system as described in as arbitrary in claim 1-3, is characterized in that: the destination address of user program code, target data configuration file and download that described Integrated Development Environment module is downloaded needs by communication channel passes to simulation management module; Described simulation management module is written to user program code or target data configuration file in the program area or data area of assigned address in program data memory by data/address bus; Described emulation chip reads user program and data from program data memory by data/address bus.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210362757.6A CN103678751B (en) | 2012-09-25 | 2012-09-25 | Processor chips emulation debugging system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210362757.6A CN103678751B (en) | 2012-09-25 | 2012-09-25 | Processor chips emulation debugging system |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103678751A true CN103678751A (en) | 2014-03-26 |
CN103678751B CN103678751B (en) | 2018-04-27 |
Family
ID=50316294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210362757.6A Active CN103678751B (en) | 2012-09-25 | 2012-09-25 | Processor chips emulation debugging system |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN103678751B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104077204A (en) * | 2014-07-22 | 2014-10-01 | 无锡中微爱芯电子有限公司 | Reconfigurable 8-bit RSIC (reduced instruction set computer) SCM (Single Chip Microcomputer) simulator |
CN106354966A (en) * | 2016-09-06 | 2017-01-25 | 芯海科技(深圳)股份有限公司 | Method for converting chip IDE project files and rapidly configuring simulation debugging environment |
CN107391077A (en) * | 2017-07-11 | 2017-11-24 | 苏州顺芯半导体有限公司 | A kind of programmable audio A/D conversion chip and its implementation |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1690976A (en) * | 2004-04-24 | 2005-11-02 | 鸿富锦精密工业(深圳)有限公司 | Automatic test system and method for mainboard |
CN101136036A (en) * | 2006-10-12 | 2008-03-05 | 中兴通讯股份有限公司 | Combined on site programmable gate array verification device |
CN101162440A (en) * | 2007-11-20 | 2008-04-16 | 杭州中天微系统有限公司 | Design method for built-in processor high speed on-line download straight-through channel |
US7693699B2 (en) * | 2005-08-19 | 2010-04-06 | Opnet Technologies, Inc. | Incremental update of virtual devices in a modeled network |
CN101968763A (en) * | 2009-07-27 | 2011-02-09 | 上海华虹集成电路有限责任公司 | High-speed processor chip simulator |
-
2012
- 2012-09-25 CN CN201210362757.6A patent/CN103678751B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1690976A (en) * | 2004-04-24 | 2005-11-02 | 鸿富锦精密工业(深圳)有限公司 | Automatic test system and method for mainboard |
US7693699B2 (en) * | 2005-08-19 | 2010-04-06 | Opnet Technologies, Inc. | Incremental update of virtual devices in a modeled network |
CN101136036A (en) * | 2006-10-12 | 2008-03-05 | 中兴通讯股份有限公司 | Combined on site programmable gate array verification device |
CN101162440A (en) * | 2007-11-20 | 2008-04-16 | 杭州中天微系统有限公司 | Design method for built-in processor high speed on-line download straight-through channel |
CN101968763A (en) * | 2009-07-27 | 2011-02-09 | 上海华虹集成电路有限责任公司 | High-speed processor chip simulator |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104077204A (en) * | 2014-07-22 | 2014-10-01 | 无锡中微爱芯电子有限公司 | Reconfigurable 8-bit RSIC (reduced instruction set computer) SCM (Single Chip Microcomputer) simulator |
CN104077204B (en) * | 2014-07-22 | 2016-01-27 | 无锡中微爱芯电子有限公司 | Reconfigurable 8 RSIC singlechip emulators |
CN106354966A (en) * | 2016-09-06 | 2017-01-25 | 芯海科技(深圳)股份有限公司 | Method for converting chip IDE project files and rapidly configuring simulation debugging environment |
CN106354966B (en) * | 2016-09-06 | 2019-11-08 | 芯海科技(深圳)股份有限公司 | The method of the conversion of chip id E project file and rapid configuration artificial debugging environment |
CN107391077A (en) * | 2017-07-11 | 2017-11-24 | 苏州顺芯半导体有限公司 | A kind of programmable audio A/D conversion chip and its implementation |
Also Published As
Publication number | Publication date |
---|---|
CN103678751B (en) | 2018-04-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105573800B (en) | A kind of veneer or multi-slab and online updating method based on ZYNQ | |
CN104360883B (en) | A kind of configuration Raid method and system | |
CN101344899B (en) | Simulation test method and system of on-chip system | |
CN104077204B (en) | Reconfigurable 8 RSIC singlechip emulators | |
CN101937349A (en) | Wireless communication terminal and software upgrading method thereof | |
CN103197943A (en) | Online single-chip microcomputer upgrading method and system | |
CN102053850A (en) | Method for on-line FPGA logic upgrade | |
US8296119B2 (en) | Saving and restarting discrete event simulations | |
CN102117243A (en) | Method for high efficiently debugging by using software breakpoint in Flash memory | |
CN104461859B (en) | A kind of emulator and method for supporting the soft debugging breakpoints of NVM | |
CN104133705A (en) | System and method for loading PowerPC system guide file through serial port | |
CN104077166A (en) | EPCS and EPCQ storer online upgrading method based on IP core in FPGA | |
CN102467446A (en) | Processor chip emulator capable of setting program pointer value | |
CN103678751A (en) | Processor chip simulation debugging system | |
CN115951966A (en) | System and method for verifying power cycling of emulated PCIe-based storage devices | |
CN104035757A (en) | MIPS-based (microprocessor without interlocked piped stages-based) U-boot (universal boot loader) transplantation implementing method | |
CN108694052B (en) | Firmware upgrading method, firmware upgrading device and firmware upgrading system | |
CN113986257A (en) | Cloud platform front-end management interface deployment method and device and storage medium | |
CN106485020B (en) | Processor chips emulator with nonvolatile memory | |
CN104680059A (en) | Emulator for protecting chip firmware program and method thereof | |
CN109426511A (en) | Soft core update method and system | |
CN101206613A (en) | High speed basic input/output system debug card | |
CN104679535A (en) | Server and identification code synchronization method | |
CN211878599U (en) | Simulation verification system applied to field editable gate array FPGA | |
CN105573924B (en) | Analogue system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |