CN102053850A

CN102053850A - Method for on-line FPGA logic upgrade

Info

Publication number: CN102053850A
Application number: CN2010105984992A
Authority: CN
Inventors: 白宗元; 张磊; 李静; 刘朝辉; 刘灿
Original assignee: TIANJIN SUGON COMPUTER INDUSTRY Co Ltd
Current assignee: TIANJIN SUGON COMPUTER INDUSTRY Co Ltd
Priority date: 2010-12-17
Filing date: 2010-12-17
Publication date: 2011-05-11

Abstract

The invention provides a method for on-line FPGA (Field Programmable Gate Array) logic upgrade. A device adopting the method comprises a remote terminal, a control terminal, an FPGA programmable logic gate circuit and a PROM (Programmable Read-Only Memory). The method comprises the following steps: a download bus interface of an FPGA is connected with a CPU (Central Processing Unit) through a PCIE (Peripheral Component Interconnect Express); to-be-upgraded logical files and logical information which include version numbers and upgrade time information are written into a nonvolatile memory device through a PCIE bus; and after writing, upgrade logic in the FPGA checks content written in the nonvolatile memory device to ensure the writing accuracy; after the writing is finished, automatic loading instruction is actuated to achieve loading without cutting off and re-starting an interface card, the logic upgrade can be finished only through warm reset, and the logic loading can be finished only through electrification and restart after power-off. The method provided by the invention can be conveniently used to solve the upgrade problems without requiring power-off and restart under the condition that staff can not conveniently write logic on site in complicated environments, the logic writing can be finished so long as warm reset of the system is carried out after automatic loading instead of power-off and restart. The method can be realized remotely with less effort and materials, and the operation is simple and convenient.

Description

A kind of method of online upgrading fpga logic

Technical field

The present invention relates to the integrated circuit board logical update, be specifically related to a kind of method of online upgrading fpga logic.

Background technology

Require to be not suitable for the staff and to go the programming logic to the scene in some environment more complicated, confidentiality, adopt traditional private cable programming load mode obviously can not meet the demands than under the condition with higher; In the present circumstance, the mode that the staff adopts private cable at the scene logic to be upgraded more makes that the enforceability of work is relatively more difficult.

CN200610156169.1 discloses the method for automatic download of a kind of FPGA of realization and online upgrading, wherein, realizes that the method that FPGA downloads automatically comprises the steps: the download bus interface of FPGA is connected with the general programmable input/output interface of CPU; The downloading mode of FPGA is set; CPU will download from nonvolatile semiconductor memory member by the Flash bus and read; Downloading that CPU will read writes among the FPGA by general programmable input/output interface signal bus, finishes until download.

This method the upgrading process in, need CPU from nonvolatile semiconductor memory member, to read to download to be written to then among the FPGA, and being power down, FPGA promptly loses logic, each upgrading also needs the participation of CPU, make efficient not high, and after repeatedly upgrading, can not well write down the information of upgrade logic.

Summary of the invention

The method that the object of the invention is to propose a kind of online upgrading fpga logic solves some and is not suitable for staff's local logical update of working.

The method of a kind of online upgrading FPGA comprises remote terminal, control end, and FPGA FPGA (Field Programmable Gate Array) gate circuit and PROM, step is as follows:

A, the download bus interface of FPGA is realized being connected by the PCIE bus interface with CPU;

B, land the login remote machine by the windows remote desktop, the control remote terminal writes logical file and the logical message that will upgrade by the PCIE bus in nonvolatile semiconductor memory member, comprise version number, update time information;

C, the upgrade logic that writes among the FPGA that finishes will carry out verification to the content of write non-volatile memory spare, with the correctness that guarantees to write;

D, write end after, carry out automatic load instructions, finish loading procedure, do not need the integrated circuit board power-off restarting, only need the hot reset can the completion logic escalation process, only need power on after the power down and restart also the process that can completion logic loads.

First kind of optimal technical scheme of the present invention is: described control end logs on remote terminal by the windows remote desktop.

Second kind of optimal technical scheme of the present invention is: described FPGA FPGA (Field Programmable Gate Array) gate circuit is connected with remote terminal by the PCIE bus, is connected with PROM by the IO interface.

The third optimal technical scheme of the present invention is: earlier upgrade file is downloaded to remote terminal during upgrading, control end control remote terminal writes PROM by FPGA FPGA (Field Programmable Gate Array) gate circuit with file then.

The present invention in some environment more complicated, be not suitable for the staff and go under the situation of programming logic to on-the-spot, adopt this method can solve upgrade problem very easily, and do not need power-off restarting, automatically loading the back only need can finish system's hot reset, but operated from a distance, use manpower and material resources sparingly, simple to operation.

Description of drawings

Fig. 1 is a principle of work of the present invention

Specific embodiments

The present invention is implemented in systems programming PROM chip, and do not realize by downloading line, therefore we adopt the logic in the PROM chip to be written are write scheme among the PROM by upper layer software (applications) by the PCIe interface, and Fig. 1 has briefly described the implementation procedure of whole proposal.

1, the download bus interface with FPGA realizes being connected by the PCIE bus interface with CPU;

2, land the login remote machine by the windows remote desktop, the control remote terminal writes logical file and the logical message that will upgrade by the PCIE bus in nonvolatile semiconductor memory member, comprise version number, update time information;

3, the upgrade logic that writes among the FPGA that finishes will carry out verification to the content of write non-volatile memory spare, with the correctness that guarantees to write;

4, write end after, carry out automatic load instructions, finish loading procedure, do not need the integrated circuit board power-off restarting, only need the hot reset can the completion logic escalation process, only need power on after the power down and restart also the process that can completion logic loads.

Claims

1. the method for an online upgrading FPGA, it is characterized in that: the device in the described method comprises remote terminal, control end, FPGA FPGA (Field Programmable Gate Array) gate circuit and PROM;

Described method comprises the steps:

2. a kind of according to claim 1 method of online upgrading fpga logic, it is characterized in that: described control end logs on remote terminal by the windows remote desktop.

3. a kind of according to claim 1 method of online upgrading fpga logic, it is characterized in that: described FPGA FPGA (Field Programmable Gate Array) gate circuit is connected with remote terminal by the PCIE bus, is connected with PROM by the IO interface.

4. a kind of as claimed in claim 1 or 2 method of online upgrading fpga logic is characterized in that: earlier upgrade file is downloaded to remote terminal during upgrading, control end control remote terminal writes PROM by FPGA FPGA (Field Programmable Gate Array) gate circuit with file then.

5. as the method for a kind of online upgrading fpga logic as described in the claim 3, it is characterized in that: earlier upgrade file is downloaded to remote terminal during upgrading, control end control remote terminal writes PROM by FPGA FPGA (Field Programmable Gate Array) gate circuit with file then.

6. a kind of according to claim 1 device of online upgrading fpga logic is characterized in that: earlier upgrade file is downloaded to remote terminal during upgrading, control end control remote terminal writes PROM by FPGA FPGA (Field Programmable Gate Array) gate circuit with file then.