CN108228221A

CN108228221A - A kind of programmable logic online upgrading method based on 1553B buses

Info

Publication number: CN108228221A
Application number: CN201611153202.5A
Authority: CN
Inventors: 李翠娟; 楚要钦; 吴翼虎; 陈川; 闫昆; 高�浩
Original assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Current assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Priority date: 2016-12-14
Filing date: 2016-12-14
Publication date: 2018-06-29

Abstract

The present invention is to solve the problems, such as shooting missile-borne computer fpga logic online upgrading, proposes to carry out online upgrading to missile-borne computer inside FPGA by the external 1553B bus interface of guided missile.Belong to missile-borne computer fpga logic online upgrading technical field.This method effectively prevents the problem of maintenance cost caused by removing guided missile increases, guided missile reliability reduces.

Description

A kind of programmable logic online upgrading method based on 1553B buses

Technical field

The invention belongs to missile-borne computer fpga logic online upgrading technical fields.

Background technology

Guided missile volume is limited, and the compact-sized size of on-board electronics is small, is solidified as a whole after guided missile is packed into guided missile, is led to It cannot often dismantle, dismounting usually requires to return factory's progress, of high cost, and guided missile reliability can be caused to reduce, service life decline, no Conducive to the permanent storage and maintenance of guided missile.In addition, guided missile has a storage life requirement, and general 16 years to 21 years, certain guided missile storages Time is longer, and turning over the phase in head can be to having initial workpiece or wearing detail to replace, to having the storage chip of data hold time again Carry out programming.The configuration of field programmable gate array (FPGA) is manufactured with PROM generally use CMOS NOR FLASH techniques, is had Data hold time requirement, then must programming again more than data hold time.It can be by the jtag interface of PROM chips to it The logical versions of storage carry out online upgrading, but guided missile externally provides 1553B bus interface at present, does not provide internal unit Jtag interface.Therefore, how to be realized under the conditions of guided missile is not torn open aobvious to the online upgrading of missile-borne computer fpga logic and detection It obtains particularly important.

Invention content

The present invention is to solve the problems, such as shooting missile-borne computer fpga logic online upgrading, propose to pass through The external 1553B bus interface of guided missile carries out online upgrading to missile-borne computer inside FPGA.

It is as follows to implement step：

First, in the air under state, missile-borne computer is established by missile-borne 1553B bus interface and external detection equipment to be connected It connects, waits fpga logic online upgrading order to be received；

Secondly, missile-borne computer receives fpga logic online upgrading order, and missile-borne computer is connect by processor GPIO Mouth control FPGA carries out logic switch, and switching fpga logic is basic logic；

Again, processor receives function logic object code to be upgraded by 1553B buses；

Then, processor, will be to be upgraded by the PROM jtag interface control logics inside local bus access FPGA Function logic code is by the programming of PROM jtag interfaces into Memory inside PROM；

Then, the PROM jtag interfaces control logic that processor is accessed by local bus inside FPGA is read in PROM Portion Memory cures information, is verified；

Then, if verified successfully, programming success, processor is upgraded by 1553B bus feedbacks to be completed, and otherwise report rises Grade failure；

Finally, system reset, the function logic automatic running after upgrading.

As previously mentioned, used PROM chips are Xilinx companies XCFP PROM or domestic compatible chips, it is used FGPA chip Xilinx company's chips or compatible chip, the fpga logic object code that missile-borne computer receives are IEEE Std 1149.1Boundary-Scan (JTAG) Serial Vector Format (SVF) file.

Description of the drawings

Fig. 1 is a kind of programmable logic online upgrading method schematic based on 1553B buses.

Specific embodiment

Secondly, missile-borne computer receives fpga logic online upgrading order, controls PROM chip EX_EXT_SEL# signals For low, REV_SEL [0] signal be low, REV_SEL [1] signal it is low, and enabled fpga chip PROG_G signals are low, are started FPGA is reloaded, and switching fpga logic is determined function logic online upgrading for basic logic；

Finally, system reset, the function logic automatic running after upgrading.

In one embodiment of the present of invention, certain model missile-borne computer project, processor uses Power PC Processor, FPGA uses the XC2V3000 of Xilinx companies production, PROM to use XCF32P, and 1553B bus control protocols are real using logic Existing, 1553B interface drivers use 1553 transceiver of HKA32201 binary channels, and data transmission rate supports 1Mbps and 2Mbps.Through Overtesting verifies that system run all right is reliable.

Claims

1. the programmable logic online upgrading method based on 1553B buses, it is characterised in that comprise the steps of：

Step 1：In the air under state, missile-borne computer is established by missile-borne 1553B bus interface and external detection equipment and connected, Etc. fpga logic online upgrading order to be received；

Step 2：Missile-borne computer receives fpga logic online upgrading order, and missile-borne computer passes through processor GPIO interface control FPGA processed carries out logic switch, and switching fpga logic is basic logic；

Step 3：Processor receives function logic object code to be upgraded by 1553B buses；

Step 4：Processor accesses the PROM jtag interface control logics inside FPGA by local bus, by work(to be upgraded Can logical code by the programming of PROM jtag interfaces into Memory inside PROM；

Step 5：The PROM jtag interfaces control logic that processor accesses inside FPGA by local bus is read inside PROM Memory cures information, is verified；

Step 6：If verified successfully, programming success, processor is upgraded by 1553B bus feedbacks to be completed, otherwise report upgrading Failure；

Step 7：System reset, the function logic automatic running after upgrading.

2. the programmable logic online upgrading method according to claim 1 based on 1553B buses, it is characterised in that：Institute The PROM chips used is Xilinx companies XCFP PROM or domestic compatible chips, used FGPA chips Xilinx companies Chip or compatible chip, the fpga logic object code that missile-borne computer receives are IEEE Std 1149.1Boundary-Scan (JTAG) Serial Vector Format (SVF) file.