CN104199707A - System and method for upgrading FPGAs - Google Patents
System and method for upgrading FPGAs Download PDFInfo
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- CN104199707A CN104199707A CN201410462141.5A CN201410462141A CN104199707A CN 104199707 A CN104199707 A CN 104199707A CN 201410462141 A CN201410462141 A CN 201410462141A CN 104199707 A CN104199707 A CN 104199707A
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Abstract
The invention discloses a system and method for upgrading FPGAs (field programmable gate arrays). The system comprises a computer, an SPI flash memory and the FPGAs, and the system is characterized by further comprising an ARM processor. The communicating end of the computer is connected with the signal input end of the ARM processor. The SPI communication interface of the ARM processor is connected with the SPI communication interface of the SPI flash memory through an SPI bus. The SPI communication interfaces of the FPGAs are connected with the SPI bus. By the system, upgrading of different programs of multiple FPGAs can be performed at the same time, overall upgrading efficiency of the FPGAs is increased, and upgrading cost of the FPGAs is lowered.
Description
Technical field
The present invention relates to FPGA (Field-Programmable Gate Array, field programmable gate array) technical field, refer to particularly a kind of system and method that FPGA is upgraded.
Background technology
The existing system that FPGA is upgraded as described in Figure 1, comprise computer, JTAG (Joint Test Action Group, joint test behavior tissue, a kind of international standard test protocol) cd-rom recorder, SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) bus, SPI class flash memory and FPGA.The working forms of this system is that the hardware operation interface routine providing by IDE (Integrated Development Environment, Integrated Development Environment) writes spi bus through JTAG cd-rom recorder, then notifies FPGA to load the program on SPI flash memory.There are the following problems for this form:
1, the computer that carries out updating operation must be installed IDE and JTAG driving, could upgrade to the software in FPGA; Because only have and just have the Pin pin of pair interface of SPI flash drive and SPI device chip operation-interface in IDE, and must use JTAG cd-rom recorder.
2, a computer can only move an IDE, between computer and FPGA, can only upgrade by JTAG one to one, and a computer multiple FPGA that can not simultaneously upgrade, efficiency is very low.
3, long (during upgrading because IDE operation consumes resources causes the time cost longer) consuming time in FPGA escalation process, and between computer and SPI kind equipment, must maintain JTAG linking status (can cause cd-rom recorder or the damage of SPI chip if pull out JTAG cd-rom recorder in escalation process).
Summary of the invention
Object of the present invention is exactly that a kind of system and method that FPGA is upgraded will be provided, and this system and method can carry out the upgrading of distinct program simultaneously to multiple FPGA, has improved the whole efficiency of FPGA upgrading, has reduced the cost of FPGA upgrading.
For realizing this object, the system that FPGA is upgraded that the present invention is designed, it comprises computer, SPI class flash memory and field programmable gate array, it is characterized in that: it also comprises arm processor, the communication ends of described computer connects the signal input part of arm processor, the SPI communication interface of described arm processor connects the SPI communication interface of SPI class flash memory by spi bus, the SPI communication interface of described field programmable gate array accesses above-mentioned spi bus.
Further, described field programmable gate array has multiple, and the SPI communication interface of each field programmable gate array all connects above-mentioned spi bus.
Further, described SPI class flash memory has multiple, and the SPI communication interface of each SPI class flash memory all connects above-mentioned spi bus.
Further, the number of described SPI class flash memory equates with the number of field programmable gate array.
A method of FPGA being upgraded based on system described in claim 1, is characterized in that, it comprises the steps:
Step 1: computer sends User Datagram Protoco (UDP) to arm processor, makes arm processor be mounted on computer by Ethernet;
Step 2: computer sends packet to arm processor, notice arm processor field programmable gate array will be upgraded;
Step 3:ARM processor copies out the firmware binaries program that the pre-stored field programmable gate array in computer inside is upgraded required from computer by Ethernet;
Step 4:ARM processor operates the bus extender on SPI class flash memory by application program, makes SPI class flash memory in can programming pattern;
Step 5:ARM processor formats processing to SPI class flash memory;
Step 6:ARM processor writes to SPI class flash memory the firmware binaries program that above-mentioned field programmable gate array is upgraded required by system call, after the firmware binaries program that field programmable gate array is upgraded required is written in SPI class flash memory completely, arm processor control SPI class flash memory is closed programming pattern and SPI class flash memory is switched to reading mode;
Step 7: described field programmable gate array reads by spi bus the firmware binaries program that the field programmable gate array that writes in SPI class flash memory is upgraded required, field programmable gate array moves above-mentioned firmware binaries program and realizes upgrading.
Beneficial effect of the present invention:
1) in computer of the present invention, do not need to install IDE and JTAG and drive, saved system resource;
2) in the present invention, adopt the alternative JTAG cd-rom recorder of arm processor obviously to reduce the cost of system, in addition, computer can disconnect and being connected of arm processor after the firmware binaries program that field programmable gate array is upgraded required copies 15 seconds in arm processor to, the safety stability coefficient that can improve so compared to existing technology system (must maintain JTAG linking status between computer and SPI kind equipment in prior art, can cause cd-rom recorder or SPI chip to damage if pull out JTAG cd-rom recorder in escalation process, and there is not this problem in the present invention, improve the security and stability of system).
3) in the present invention, can on spi bus, hang multiple field programmable gate arrays simultaneously, upgrading when can realizing multiple field programmable gate array, in prior art, computer can only field programmable gate array of respective upgrades, need to adopt multiple independently systems to multiple field programmable gate arrays, the present invention has significantly improved the efficiency that multiple field programmable gate arrays are upgraded in contrast to this.
4) in the present invention, can on spi bus, hang multiple field programmable gate arrays one to one and SPI kind equipment, can realize simultaneously each field programmable gate array is carried out to different types of program upgrade, existing system does not possess this function simultaneously.
Brief description of the drawings
Fig. 1 is the structured flowchart of the existing system that FPGA is upgraded;
Fig. 2 is structured flowchart of the present invention.
Wherein, 1-computer, 2-SPI class flash memory, 3-field programmable gate array, 4-arm processor, 5-spi bus.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail:
The system of as shown in Figure 2 FPGA being upgraded, it comprises computer 1, SPI class flash memory 2 (Micron magnesium light series storage chip), field programmable gate array 3 (A5 series), arm processor 4 (V4 series), the communication ends of described computer 1 connects the signal input part of arm processor 4, the SPI communication interface of described arm processor 4 connects the SPI communication interface of SPI class flash memory 2 (model is n25q256a13esf40f) by spi bus 5, the SPI communication interface of described field programmable gate array 3 accesses above-mentioned spi bus 5.
In technique scheme, described field programmable gate array 3 has multiple, and the SPI communication interface of each field programmable gate array 3 all connects above-mentioned spi bus 5.This structure can realize the upgrading of multiple field programmable gate arrays 3 being carried out simultaneously to same program.
In technique scheme, described SPI class flash memory 2 has multiple, and the SPI communication interface of each SPI class flash memory 2 all connects above-mentioned spi bus 5, and the number of described SPI class flash memory 2 equates with the number of field programmable gate array 3.This structure can realize simultaneously carries out different types of program upgrade to each field programmable gate array.
In technique scheme, on arm processor 4, operation is through the built-in Linux operating system of cutting.
A method of FPGA being upgraded based on said system, it comprises the steps:
Step 1: computer 1 sends User Datagram Protoco (UDP) to arm processor 4, makes arm processor 4 be mounted to (being the file that arm processor 4 is shared on computer 1) on computer 1 by Ethernet;
Step 2: computer 1 sends packet to arm processor 4, notice arm processor 4 field programmable gate arrays 3 will be upgraded;
Step 3:ARM processor 4 copies out pre-stored firmware binaries program of upgrading required at the field programmable gate array 3 of computer 1 inside from computer 1 by Ethernet; What arm processor 4 copied firmware binaries program that field programmable gate array 3 upgrades required from computer 1 after completing can disconnect for 15 seconds and be connected (being disconnecting between computer 1 and arm processor 4) of arm processor 4, between computer 1 and field programmable gate array 3, power down can not lost program yet like this, can improve compared to existing technology the safety stability coefficient of system;
Step 4:ARM processor 4 by application program to the bus extender (gpio on SPI class flash memory 2, General Purpose Input Output, universal input/output or claim bus extender) operate, make SPI class flash memory 2 in can programming pattern;
Step 5:ARM processor 4 formats processing to SPI class flash memory 2;
Step 6:ARM processor 4 writes to SPI class flash memory 2 the firmware binaries program that above-mentioned field programmable gate array 3 is upgraded required by system call, when the firmware binaries program that field programmable gate array 3 is upgraded required be written to completely SPI class flash memory 2 interior after, arm processor 4 is controlled SPI class flash memory 2 and is closed programming pattern and SPI class flash memory 2 is switched to reading mode;
Step 7: described field programmable gate array 3 reads by spi bus 5 the firmware binaries program that the field programmable gate array 3 that writes in SPI class flash memory 2 is upgraded required, field programmable gate array 3 moves above-mentioned firmware binaries program and realizes upgrading (realized programmable gate array 3 burning programs after self-starting).
In the step 5 of technique scheme, arm processor 4 is by system call, and the method that uses memory techniques equipment library (Memory Technology Device memory techniques equipment) to provide formats processing to SPI class flash memory 2.
SPI class flash memory 2 and the field programmable gate array 3 of technique scheme all have multiple one to one; Can realize simultaneously each field programmable gate array is carried out to different types of program upgrade like this, concrete step difference is as follows:
Described step 3:ARM processor 4 copies out pre-stored firmware binaries program of upgrading required at all field programmable gate arrays 3 of computer 1 inside from computer 1 by Ethernet;
Described step 4:ARM processor 4 operates the bus extender on each SPI class flash memory 2 by application program, makes all SPI class flash memories 2 in can programming pattern;
Described step 5:ARM processor 4 formats respectively processing to each SPI class flash memory 2;
Described step 6:ARM processor 4 writes to each SPI class flash memory 2 the firmware binaries program that the field programmable gate array 3 corresponding with this SPI class flash memory 2 upgraded required by system call, when the firmware binaries program that all field programmable gate arrays 3 are upgraded required be written to completely corresponding SPI class flash memory 2 interior after, arm processor 4 is controlled each SPI class flash memory 2 and is closed programming pattern and SPI class flash memory 2 is switched to reading mode;
Described step 7: described each field programmable gate array 3 reads by spi bus 5 the firmware binaries program that the field programmable gate array 3 that writes in corresponding SPI class flash memory 2 is upgraded required, each field programmable gate array 3 moves the corresponding firmware binaries program of obtaining separately and realizes upgrading.
The present invention has broken away from the FPGA upgrading of JTAG burning mode by such scheme, meet the object that factory mass is produced.
The content that this instructions is not described in detail belongs to the known prior art of professional and technical personnel in the field.
Claims (7)
1. the system that FPGA is upgraded, it comprises computer (1), SPI class flash memory (2) and field programmable gate array (3), it is characterized in that: it also comprises arm processor (4), the communication ends of described computer (1) connects the signal input part of arm processor (4), the SPI communication interface of described arm processor (4) connects the SPI communication interface of SPI class flash memory (2) by spi bus (5), the SPI communication interface of described field programmable gate array (3) accesses above-mentioned spi bus (5).
2. the system that FPGA is upgraded according to claim 1, it is characterized in that: described field programmable gate array (3) has multiple, the SPI communication interface of each field programmable gate array (3) all connects above-mentioned spi bus (5).
3. the system that FPGA is upgraded according to claim 2, is characterized in that: described SPI class flash memory (2) has multiple, and the SPI communication interface of each SPI class flash memory (2) all connects above-mentioned spi bus (5).
4. the system that FPGA is upgraded according to claim 3, is characterized in that: the number of described SPI class flash memory (2) equates with the number of field programmable gate array (3).
5. a method of based on system described in claim 1, FPGA being upgraded, is characterized in that, it comprises the steps:
Step 1: computer (1) sends User Datagram Protoco (UDP) to arm processor (4), and arm processor (4) is mounted on computer (1) by Ethernet;
Step 2: computer (1) sends packet to arm processor (4), notice arm processor (4) field programmable gate array (3) will be upgraded;
Step 3:ARM processor (4) copies out pre-stored firmware binaries program of upgrading required at the inner field programmable gate array (3) of computer (1) from computer (1) by Ethernet;
Step 4:ARM processor (4) operates the bus extender on SPI class flash memory (2) by application program, makes SPI class flash memory (2) in can programming pattern;
Step 5:ARM processor (4) formats processing to SPI class flash memory (2);
Step 6:ARM processor (4) writes to SPI class flash memory (2) the firmware binaries program that above-mentioned field programmable gate array (3) is upgraded required by system call, after the firmware binaries program that field programmable gate array (3) is upgraded required is written in SPI class flash memory (2) completely, arm processor (4) is controlled SPI class flash memory (2) and is closed programming pattern and SPI class flash memory (2) is switched to reading mode;
Step 7: described field programmable gate array (3) reads by spi bus (5) the firmware binaries program that the field programmable gate array (3) that writes in SPI class flash memory (2) is upgraded required, field programmable gate array (3) moves above-mentioned firmware binaries program and realizes upgrading.
6. the method that FPGA is upgraded according to claim 5, it is characterized in that: in described step 5, arm processor (4) is by system call, and the method that uses memory techniques equipment library to provide formats processing to SPI class flash memory (2).
7. the method that FPGA is upgraded according to claim 5, is characterized in that: described SPI class flash memory (2) and field programmable gate array (3) all have multiple one to one;
Described step 3:ARM processor (4) copies out pre-stored firmware binaries program of upgrading required at the inner all field programmable gate arrays (3) of computer (1) from computer (1) by Ethernet;
Described step 4:ARM processor (4) operates the bus extender on each SPI class flash memory (2) by application program, makes all SPI class flash memories (2) in can programming pattern;
Described step 5:ARM processor (4) formats respectively processing to each SPI class flash memory (2);
Described step 6:ARM processor (4) writes to each SPI class flash memory (2) the firmware binaries program that the field programmable gate array (3) corresponding with this SPI class flash memory (2) upgraded required by system call, after in the firmware binaries program that all field programmable gate arrays (3) are upgraded required is written to corresponding SPI class flash memory (2) completely, arm processor (4) is controlled each SPI class flash memory (2) and is closed programming pattern and SPI class flash memory (2) is switched to reading mode;
Described step 7: described each field programmable gate array (3) reads by spi bus (5) the firmware binaries program that the field programmable gate array (3) that writes in corresponding SPI class flash memory (2) is upgraded required, the corresponding firmware binaries program that each field programmable gate array (3) operation is obtained separately realizes upgrading.
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| CN201410462141.5A CN104199707A (en) | 2014-09-12 | 2014-09-12 | System and method for upgrading FPGAs |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104935786A (en) * | 2015-05-28 | 2015-09-23 | 武汉精测电子技术股份有限公司 | Image signal source based on soft processors and method for processing image signals thereof |
| CN106445565A (en) * | 2015-07-21 | 2017-02-22 | 杭州海康威视数字技术股份有限公司 | Field programmable gate array (FPGA) upgrading method and device |
| CN106528234A (en) * | 2016-11-10 | 2017-03-22 | 深圳市紫光同创电子有限公司 | Remote upgrading method and apparatus |
| CN106998260A (en) * | 2016-01-22 | 2017-08-01 | 中国航天科工集团第四研究院指挥自动化技术研发与应用中心 | A kind of FPGA device upgrade method and system based on ethernet link |
| CN107122206A (en) * | 2017-04-12 | 2017-09-01 | 昆山龙腾光电有限公司 | Measurement jig and test system |
| CN108572835A (en) * | 2018-04-26 | 2018-09-25 | 南京国电南自维美德自动化有限公司 | A kind of FPGA configuration file online upgrade system |
| CN117171097A (en) * | 2023-08-31 | 2023-12-05 | 中科驭数（北京）科技有限公司 | Remote loading method and system for field programmable gate array |
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| CN203588252U (en) * | 2013-11-30 | 2014-05-07 | 成都天奥信息科技有限公司 | Upgrading circuit for FPGA (Field Programmable Gate Array) configuration program |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104935786A (en) * | 2015-05-28 | 2015-09-23 | 武汉精测电子技术股份有限公司 | Image signal source based on soft processors and method for processing image signals thereof |
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| CN106445565A (en) * | 2015-07-21 | 2017-02-22 | 杭州海康威视数字技术股份有限公司 | Field programmable gate array (FPGA) upgrading method and device |
| CN106998260A (en) * | 2016-01-22 | 2017-08-01 | 中国航天科工集团第四研究院指挥自动化技术研发与应用中心 | A kind of FPGA device upgrade method and system based on ethernet link |
| CN106528234A (en) * | 2016-11-10 | 2017-03-22 | 深圳市紫光同创电子有限公司 | Remote upgrading method and apparatus |
| CN106528234B (en) * | 2016-11-10 | 2019-09-13 | 深圳市紫光同创电子有限公司 | A kind of remote upgrade method and device |
| CN107122206A (en) * | 2017-04-12 | 2017-09-01 | 昆山龙腾光电有限公司 | Measurement jig and test system |
| CN108572835A (en) * | 2018-04-26 | 2018-09-25 | 南京国电南自维美德自动化有限公司 | A kind of FPGA configuration file online upgrade system |
| CN117171097A (en) * | 2023-08-31 | 2023-12-05 | 中科驭数（北京）科技有限公司 | Remote loading method and system for field programmable gate array |
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