CN105278976A - FPGA (Field Programmable Gate Array) reconstruction device, system and method - Google Patents

FPGA (Field Programmable Gate Array) reconstruction device, system and method Download PDF

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Publication number
CN105278976A
CN105278976A CN201410322231.4A CN201410322231A CN105278976A CN 105278976 A CN105278976 A CN 105278976A CN 201410322231 A CN201410322231 A CN 201410322231A CN 105278976 A CN105278976 A CN 105278976A
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fpga
program
fpga chip
processor
district
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CN105278976B (en
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杨卫峰
粟爱军
肖家博
周学勋
蒋国涛
陆琦
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CRRC Zhuzhou Institute Co Ltd
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CSR Zhuzou Institute Co Ltd
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Abstract

The invention discloses an FPGA (Field Programmable Gate Array) reconstruction device, system and method. The reconstruction device comprises an FPGA chip, wherein the FPGA chip comprises an FPGA program unit and a memory, and the memory comprises a program storage sector A used as a boot sector, and a program storage sector B where an application program is stored. When the FPGA chip is powered on, a file is firstly downloaded from the program storage sector A to be operated, and an FPGA program unit is generated; and when the operation of the FPGA chip is finished, an indication signal is emitted to an external processor, the processor controls the FPGA chip to be restarted, and the FPGA chip downloads the application program from the program storage sector B to cause the application program to be operated. Risks in a process that the FPGA program is updated through the processor can be effectively eliminated, and the process that the FPGA program is updated through the processor can be guaranteed to be still finished under certain unpredictable abnormal conditions including wrong operation, sudden outage and the like in the updating process.

Description

A kind of FPGA reconfiguration device, system and method
Technical field
The present invention relates to electronic circuit technology field, especially relate to a kind of the FPGA reconfiguration device, the system and method that are applied to programmable logic device (PLD).
Background technology
Along with programmable logic technology, the especially development of FPGA technology and growth, nearly all product all can use fpga chip, is therefore difficult to avoid FPGA program to need to be realized by circuit reconfiguration the renewal of application program due to design defect.The essence of circuit reconfiguration utilizes FPGA able to programme to have the characteristic that can repeatedly configure, call different configuration files as required to change the logical organization of circuit, thus make system have flexible, simple and direct, hardware resource is reusable, be easy to the multiple premium properties such as upgrading.Reconfigurable system reconfigures FPGA usually in both cases: one is that fpga logic function needs conversion, as the mistake on algorithm improvement or discovery design; Two is that FPGA configuration data makes a mistake and the disabler caused.
The SPARTAN3AN Series FPGA chip of XILINX company carries inner SPIFLASH as FPGA program storage, when the product needed using this chip development is by update processor FPGA program, if at no point in the update process, when occurring that the unpredictable reason of such as power-off suddenly, program error code etc. causes renewal unsuccessful, then not only upgrade unsuccessful, also can damage the program stored inside original SPIFLASH, fpga chip can not normally be run.Simultaneously, the inner SPI controller realized by logical language of FPGA is caused not exist further, processor also just cannot connect with the SPIFLASH of fpga chip inside, thus again by the application program of update processor FPGA, and can only can not be downloaded applications in SPIFLASH by the JTAG mouth of fpga chip.
Prior art normally carries out the renewal of FPGA application program at products application scene, and the process of on-the-spot program updates is a huge and engineering for arduousness.Traditional method is all upgrade FPGA program by jtag interface, and first this need the shell taking product apart, then utilizes special FPGA Program download to be downloaded in the program storage of fpga chip by the jtag interface of fpga chip.This method very poor efficiency, the major part working time is all wasted on dismounting, completed knocked down products, in order to solve the inefficiency problem of this traditional FPGA method for updating program, new is constantly occurred by the method for update processor FPGA program, but in actual implementation process, proceed to half once refresh routine and make mistakes, then again cannot pass through update processor FPGA program, still need to dismantle product, still upgrade FPGA program by jtag interface, thoroughly cannot solve the technical matters that traditional F PGA method for updating program exists.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of FPGA reconfiguration device, system and method, effectively can solve the risk by existing in update processor FPGA program process, even if guarantee, at no point in the update process due under some unpredictable abnormal conditions of operation, power-off suddenly etc. of mistake, still can complete the process by update processor FPGA program.
In order to realize foregoing invention object, the present invention specifically provides a kind of technic relization scheme of FPGA reconfiguration system, and a kind of FPGA reconfiguration device, comprising: fpga chip, and described fpga chip comprises FPGA program element and storer.The program that described storer comprises as boot section stores A district, and the program storing application program stores B district.When described fpga chip powers on, first store A district download file from described program to run, and generate FPGA program element, after described fpga chip has run, processor externally sends indicator signal, control described fpga chip by described processor to restart, described fpga chip stores down load application program B district from program and runs.
Preferably, described FPGA program element comprises application program unit and reconstruct trigger element, and described application program unit comprises port controller.Described program stores the program storing in A district and generate described reconstruct trigger element and port controller, after described fpga chip has run, generate described reconstruct trigger element and port controller, described processor accesses described storer by described port controller.Under accidental conditions, after described fpga chip has run, processor externally sends indicator signal, sends trigger pip, control described fpga chip and restart after described indicator signal arrives by described processor to the reconstruct trigger element of described FPGA program element.
Preferably, under FPGA program updates operating mode, after described fpga chip has run, processor externally sends indicator signal, described processor upgrades the application program that described program stores the described fpga chip in B district after described indicator signal arrives, send trigger pip by described processor to the reconstruct trigger element of described FPGA program element after having upgraded, control described fpga chip and restart.
Preferably, described reconstruct trigger element comprises command word r/w cell and inner configuration access unit, described command word r/w cell is to described inner configuration access unit write command word, control the duty of described inner configuration access unit, described inner configuration access unit is for controlling described storer to described FPGA program element loading configuration file.
Preferably, described fpga chip is connected by the processor of spi bus with described outside.
Preferably, described storer is the SPIFLASH of described fpga chip inside, and described port controller is SPI controller.
The present invention also specifically provides a kind of technic relization scheme of FPGA reconfiguration system in addition, and a kind of FPGA reconfiguration system, comprising: FPGA reconfiguration device as above, and the processor be connected with described FPGA reconfiguration device.
Preferably, under accidental conditions, described processor wait for described fpga chip run after indicator signal, and after described indicator signal arrives, the reconstruct trigger element to described FPGA program element sends trigger pip.
Preferably, under FPGA program updates operating mode, described processor wait for described fpga chip run after indicator signal, described processor upgrades the application program that described program stores the described fpga chip in B district after described indicator signal arrives, and sends trigger pip after having upgraded by described processor to the reconstruct trigger element of described FPGA program element.
The present invention also specifically provides a kind of technic relization scheme of FPGA reconstructing method in addition, and FPGA reconfiguration device comprises fpga chip, and described fpga chip comprises FPGA program element and storer; The program that described storer comprises as boot section stores A district, and the program storing application program stores B district; Said method comprising the steps of:
S10: when fpga chip powers on, first stores A district download file from the program of storer and runs, and generate FPGA program element;
S20: after described fpga chip has run, processor externally sends indicator signal, controls described fpga chip restart by described processor, and described fpga chip stores down load application program B district from the program of described storer and runs.
Preferably, described FPGA program element comprises application program unit and reconstruct trigger element, and described application program unit comprises port controller; Described program stores the program storing in A district and generate described reconstruct trigger element and port controller, after described fpga chip has run, generate described reconstruct trigger element and port controller, described processor accesses described storer by described port controller.
Preferably, under accidental conditions, described step S20 comprises further:
Described processor waits for that described fpga chip completes postrun indicator signal, and after described indicator signal arrives, the reconstruct trigger element to described fpga chip sends trigger pip, controls described fpga chip and restarts.
Preferably, under FPGA program updates operating mode, described step S20 comprises further:
Described processor waits for that described fpga chip completes postrun indicator signal, described processor upgrades the application program that described program stores the described fpga chip in B district after described indicator signal arrives, send trigger pip by described processor to the reconstruct trigger element of described FPGA program element after having upgraded, control described fpga chip and restart.
By implementing FPGA reconfiguration device, system and method that the invention described above provides, there is following technique effect:
(1) when the present invention uses the storer of fpga chip inside as FPGA program storage area, the FPGA program in outside update processor storer can be taked highly reliably, even if make mistakes at no point in the update process, what damage is also the program that program stores B district, and the boot that program stores A district can not be damaged always, the FPGA program that program stores A district still can be used; Still can store the FPGA program in A district by working procedure after fpga chip re-powers, processor still can store interface controller access storer inside A district program by program;
(2) the present invention can solve the risk by existing in update processor FPGA program process effectively, even if guarantee, at no point in the update process due under some unpredictable abnormal conditions of operation, power-off suddenly etc. of mistake, still can complete the process by update processor FPGA program.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the system architecture diagram of a kind of embodiment of FPGA reconfiguration system of the present invention;
Fig. 2 is the program flow diagram of fpga chip under accidental conditions of a kind of embodiment of FPGA reconstructing method of the present invention;
Fig. 3 is the program flow diagram of processor under accidental conditions of a kind of embodiment of FPGA reconstructing method of the present invention;
Fig. 4 is the program flow diagram of fpga chip under FPGA program updates operating mode of a kind of embodiment of FPGA reconstructing method of the present invention;
Fig. 5 is the program flow diagram of processor under FPGA program updates operating mode of a kind of embodiment of FPGA reconstructing method of the present invention;
In figure: 1-processor, 2-FPGA chip, 3-FPGA program element, 4-storer, 31-application program unit, 32-reconstructs trigger element, 311-port controller, 321-command word r/w cell, the inner configuration access unit of 322-, 41-program stores A district, and 42-program stores B district.
Embodiment
For the purpose of quoting and know, by the technical term hereinafter used, write a Chinese character in simplified form or abridge and be described below:
XILINX: the company being a design, manufacture, sale fpga chip;
SPARTAN3AN: the model being XILINX company fpga chip;
CPU:CentralProcessingUnit, the abbreviation of CPU (central processing unit);
FPGA:FieldProgrammableGateArray, the abbreviation of field programmable gate array;
SPI:SerialPeripheralInterface, the abbreviation of Serial Peripheral Interface;
FLASH: the abbreviation of flash memory;
ICAP:InternalConfigurationAccessPort, the abbreviation of inner configuration access port.
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, clear, complete description is carried out to the technical scheme in the embodiment of the present invention.Obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As shown in accompanying drawing 1 to accompanying drawing 5, give the specific embodiment of FPGA reconfiguration device of the present invention, system and method, below in conjunction with the drawings and specific embodiments, the invention will be further described.
As shown in Figure 1, a kind of specific embodiment of FPGA reconfiguration device, FPGA reconfiguration device comprises: fpga chip 2, and fpga chip 2 comprises FPGA program element 3 and storer 4.The program that storer 4 comprises as boot section stores A district 41, and the program storing application program (i.e. the configurator of fpga chip 2) stores B district 42.When fpga chip 2 powers on, first store A district 41 download file from program to run, and generate FPGA program element 3, after fpga chip 2 has run, processor 1(CPU externally) send indicator signal, control fpga chip 2 by processor 1 to restart, fpga chip 2 stores down load application program B district 42 from program and runs.
As a kind of typical specific embodiment of the present invention, fpga chip 2 is connected with the processor 1 of outside further by spi bus.Storer 4 is the SPIFLASH of fpga chip 2 inside, and port controller 311 is SPI controller further, and the port controller 311 of fpga chip 2 is connected with storer 4 further by spi bus.Certainly, other interface can also be taked to substitute SPI interface and to build FPGA reconfiguration device.
As a kind of typical specific embodiment of the present invention, FPGA program element 3 comprises application program unit 31 and reconstruct trigger element 32 further, and application program unit 31 comprises port controller 311.Program stores the program storing in A district 41 and generate reconstruct trigger element 32 and port controller 311, and after fpga chip 2 has run, generate reconstruct trigger element 32 and port controller 311, processor 1 accesses storer 4 by port controller 311.Processor 1 is connected with fpga chip 2 by SPI interface, fpga chip 2 is connected with inner SPIFLASH by inner SPI controller.The SPI controller of fpga chip 2 inside is realized by FPGA program, if do not have FPGA program or program corruption, cannot establish a connection with the SPIFLASH of inside.
The SPIFLASH of fpga chip 2 inside is divided into two memory blocks by the specific embodiment of the invention: program stores A district 41 and program stores B district 42.Wherein, program stores A district 41 as boot section, and program stores B district 42 as main program area.The program that program storage A district 41 stores only includes following function: reconstruct trigger element 32 and SPI controller two parts.The Main Function that program stores A district 41 is used to provide a SPI controller, as the interface channel of the SPIFLASH of processor 1 and fpga chip 2 inside, trigger fpga chip 2 to restart simultaneously, store B district 42 download configuration file (i.e. application program) from program and run.And the program that program storage B district 42 stores is application program, do not comprise the program generating reconstruct trigger element 32 and SPI controller.
The FPGA reconfiguration device that the specific embodiment of the invention describes is under accidental conditions, after fpga chip 2 has run, processor 1 externally sends indicator signal, after indicator signal arrives, send trigger pip by processor 1 to the reconstruct trigger element 32 of FPGA program element 3, control fpga chip 2 and restart.
The FPGA reconfiguration device that the specific embodiment of the invention describes is under FPGA program updates operating mode, after fpga chip 2 has run, processor 1 externally sends indicator signal, is stored the application program of the fpga chip 2 in B district 42 after indicator signal arrives by processor 1 refresh routine.Now, processor 1 can access storer 4 by port controller 311, after application program update completes, send trigger pip by processor 1 to the reconstruct trigger element 32 of FPGA program element 3, controls fpga chip 2 and restarts.
As a kind of typical specific embodiment of the present invention, reconstruct trigger element 32 comprises command word r/w cell 321 and inner configuration access unit 322 further.Command word r/w cell 321 internally configuration access unit 322 writes command word, controls the duty of inner configuration access unit 322.And inner configuration access unit 322(ICAP:InternalConfigurationAccessPort), as module intrinsic in fpga chip 2, for control store 4 to FPGA program element 3 loading configuration file.
A specific embodiment for FPGA reconfiguration system, comprising: FPGA reconfiguration device as above, and the processor 1 be connected with FPGA reconfiguration device.
Under accidental conditions, processor 1 wait for fpga chip 2 run after indicator signal, and indicator signal arrive after, the reconstruct trigger element 32 to FPGA program element 3 sends trigger pip.
Under FPGA program updates operating mode, processor 1 wait for fpga chip 2 run after indicator signal, processor 1 refresh routine after indicator signal arrives stores the application program of the fpga chip 2 in B district 42, sends trigger pip after having upgraded by processor 1 to the reconstruct trigger element 32 of FPGA program element 3.
The FPGA reconfiguration system that the specific embodiment of the invention describes upgrades by CPU the risk existed in FPGA program process in order to solve, the SPIFLASH of fpga chip 2 inside is divided into two regions: program stores A district 41 and program stores B district 42, its Program stores A district 41 as boot section, program stores B district 42 as main program area, when carrying out FPGA program updates, a refresh routine stores the program in B district 42, even if this ensures that there at no point in the update process due to the operation of mistake, under some unpredictable abnormal conditions of unexpected power-off etc., what damage is also the FPGA program that program stores B district 42, and the FPGA program that program stores in A district 41 still can be used.After fpga chip 2 re-powers, fpga chip 2 can store FPGA program in A district 41 by working procedure, and processor 1 still can store the SPIFLASH of SPI controller access fpga chip 2 inside in the boot in A district 41 by program.No matter under what circumstances the FPGA reconfiguration device that this makes the specific embodiment of the invention describe, can guarantee to upgrade FPGA program by CPU, even if when makeing mistakes at no point in the update process, also by processor 1(CPU) application program again in remote update FPGA.
A specific embodiment for FPGA reconstructing method, FPGA reconfiguration device comprises fpga chip 2, and fpga chip 2 comprises FPGA program element 3 and storer 4.The program that storer 4 comprises as boot section stores A district 41, and the program storing application program stores B district 42.FPGA reconstructing method comprises the following steps:
S10: when fpga chip 2 powers on, first stores A district 41 download file from the program of storer 4 and runs, and generate FPGA program element 3;
S20: after fpga chip 2 has run, processor 1 externally sends indicator signal, controls fpga chip 2 restart by processor 1, and fpga chip 2 stores down load application program B district 42 from the program of storer 4 and runs.
FPGA program element 3 comprises application program unit 31 and reconstruct trigger element 32, and application program unit 31 comprises port controller 311.Program stores the program storing in A district 41 and generate reconstruct trigger element 32 and port controller 311, and after fpga chip 2 has run, generate reconstruct trigger element 32 and port controller 311, processor 1 accesses storer 4 by port controller 311.
Under accidental conditions, step S20 comprises further:
Processor 1 waits for that fpga chip 2 completes postrun indicator signal, and after indicator signal arrives, the reconstruct trigger element 32 to fpga chip 2 sends trigger pip, controls fpga chip 2 and restarts.
Under FPGA program updates operating mode, step S20 comprises further:
Processor 1 waits for that fpga chip 2 completes postrun indicator signal, processor 1 refresh routine after indicator signal arrives stores the application program of the fpga chip 2 in B district 42, send trigger pip by processor 1 to the reconstruct trigger element 32 of FPGA program element 3 after having upgraded, control fpga chip 2 and restart.As shown in Figure 2, be a kind of embodiment of the program operational scheme of fpga chip 2 under accidental conditions, specifically comprise the following steps:
(1) after fpga chip 2 powers at every turn, first fpga chip 2 always stores A district 41 download configuration file from the program of the SPIFLASH of inside and runs;
(2) when fpga chip 2 runs successfully, generate reconstruct trigger element 32 and port controller 311, processor 1 can access storer 4 by port controller 311, and fpga chip 2 provides indicator signal notification processor 1; If run unsuccessful, then continue to store A district 41 download configuration file from the program of SPIFLASH and run;
(3) fpga chip 2 waits for the trigger pip that processor 1 sends to the reconstruct trigger element 32 of fpga chip 2;
(4) if receive the trigger pip that processor 1 sends, then fpga chip 2 restarts; If do not receive the trigger pip that processor 1 sends, then continue the trigger pip waiting for that processor 1 sends;
(5) fpga chip 2 stores B district 42 download configuration file (i.e. application program) operation from the program of the SPIFLASH of inside.
As shown in Figure 3, be a kind of embodiment of the program operational scheme of processor 1 under accidental conditions, specifically comprise the following steps:
(1) processor 1 waits for that fpga chip 2 has run indicator signal;
(2) processor 1 sends trigger pip to fpga chip 2 after indicator signal arrives.
As shown in Figure 4, be a kind of embodiment of the program operational scheme of fpga chip 2 under FPGA program updates operating mode, specifically comprise the following steps:
(1) after fpga chip 2 powers at every turn, first fpga chip 2 always stores A district 41 download configuration file from the program of the SPIFLASH of inside and runs;
(2) when fpga chip 2 runs successfully, generate reconstruct trigger element 32 and port controller 311, processor 1 can access storer 4 by port controller 311, and fpga chip 2 provides indicator signal notification processor 1; If run unsuccessful, then continue to store A district 41 download configuration file from the program of SPIFLASH and run;
(3) fpga chip 2 waits for the trigger pip that processor 1 sends to the reconstruct trigger element 32 of fpga chip 2;
(4) if receive the trigger pip that processor 1 sends, then fpga chip 2 restarts; If do not receive the trigger pip that processor 1 sends, then continue the trigger pip waiting for that processor 1 sends;
(5) fpga chip 2 stores B district 42 download configuration file (i.e. application program) operation from the program of the SPIFLASH of inside.
As shown in Figure 5, be a kind of embodiment of the program operational scheme of processor 1 under FPGA program updates operating mode, specifically comprise the following steps:
(1) processor 1 waits for that fpga chip 2 has run indicator signal;
(2) processor 1 upgrades the FPGA program in the program storage B district 42 of the SPIFLASH of fpga chip 2 inside after indicator signal arrives, now processor 1 can access storer 4 by port controller 311, thus the program upgrading SPIFLASH stores the FPGA program in B district 42;
(3) processor 1 sends trigger pip to fpga chip 2.
By implementing FPGA reconfiguration device, system and method that the specific embodiment of the invention describes, following technique effect can be produced:
(1) when the technical scheme that the specific embodiment of the invention describes uses the storer of fpga chip inside as FPGA program storage area, the FPGA program in outside update processor storer can be taked highly reliably, even if make mistakes at no point in the update process, what damage is also the program that program stores B district, and the boot that program stores A district can not be damaged always, the FPGA program that program stores A district still can be used; Still can store the FPGA program in A district by working procedure after fpga chip re-powers, processor still can store interface controller access storer inside A district program by program;
(2) technical scheme that the specific embodiment of the invention describes can solve the risk by existing in update processor FPGA program process effectively, even if guarantee, at no point in the update process due under some unpredictable abnormal conditions of operation, power-off suddenly etc. of mistake, still can complete the process by update processor FPGA program.
In this instructions, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, when not departing from Spirit Essence of the present invention and technical scheme, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent replacement, equivalence change and modification, all still belongs in the scope of technical solution of the present invention protection.

Claims (13)

1. a FPGA reconfiguration device, is characterized in that: comprise fpga chip (2), and described fpga chip (2) comprises FPGA program element (3) and storer (4); The program that described storer (4) comprises as boot section stores A district (41), and the program storing application program stores B district (42); When described fpga chip (2) powers on, first store A district (41) download file from described program to run, and generate FPGA program element (3), after described fpga chip (2) has run, processor (1) externally sends indicator signal, control described fpga chip (2) by described processor (1) to restart, described fpga chip (2) stores down load application program B district (42) from program and runs.
2. a kind of FPGA reconfiguration device according to claim 1, is characterized in that: described FPGA program element (3) comprises application program unit (31) and reconstruct trigger element (32), and described application program unit (31) comprises port controller (311); Described program stores the program storing in A district (41) and generate described reconstruct trigger element (32) and port controller (311), after described fpga chip (2) has run, generate described reconstruct trigger element (32) and port controller (311), described processor (1) accesses described storer (4) by described port controller (311); Under accidental conditions, after described fpga chip (2) has run, processor (1) externally sends indicator signal, after described indicator signal arrives, send trigger pip by described processor (1) to the reconstruct trigger element (32) of described FPGA program element (3), control described fpga chip (2) and restart.
3. a kind of FPGA reconfiguration device according to claim 2, it is characterized in that: under FPGA program updates operating mode, after described fpga chip (2) has run, processor (1) externally sends indicator signal, described processor (1) upgrades the application program that described program stores the described fpga chip (2) in B district (42) after described indicator signal arrives, send trigger pip by described processor (1) to the reconstruct trigger element (32) of described FPGA program element (3) after renewal completes, control described fpga chip (2) and restart.
4. a kind of FPGA reconfiguration device according to Claims 2 or 3, it is characterized in that: described reconstruct trigger element (32) comprises command word r/w cell (321) and inner configuration access unit (322), described command word r/w cell (321) is to described inner configuration access unit (322) write command word, control the duty of described inner configuration access unit (322), described inner configuration access unit (322) is for controlling described storer (4) to described FPGA program element (3) loading configuration file.
5. a kind of FPGA reconfiguration device according to claim 4, is characterized in that: described fpga chip (2) is connected with the processor (1) of described outside by spi bus.
6. according to a kind of FPGA reconfiguration device in claim 1,2,3,5 described in arbitrary claim, it is characterized in that: described storer (4) is the SPIFLASH of described fpga chip (2) inside, and described port controller (311) is SPI controller.
7. a FPGA reconfiguration system, is characterized in that, comprising: the FPGA reconfiguration device as described in claim arbitrary in claim 1 to 6, and the processor (1) be connected with described FPGA reconfiguration device.
8. a kind of FPGA reconfiguration system according to claim 7, it is characterized in that: under accidental conditions, described processor (1) wait for described fpga chip (2) run after indicator signal, and after described indicator signal arrives, the reconstruct trigger element (32) to described FPGA program element (3) sends trigger pip.
9. a kind of FPGA reconfiguration system according to claim 7, it is characterized in that: under FPGA program updates operating mode, described processor (1) wait for described fpga chip (2) run after indicator signal, described processor (1) upgrades the application program that described program stores the described fpga chip (2) in B district (42) after described indicator signal arrives, and sends trigger pip after having upgraded by described processor (1) to the reconstruct trigger element (32) of described FPGA program element (3).
10. a FPGA reconstructing method, is characterized in that, FPGA reconfiguration device comprises fpga chip (2), and described fpga chip (2) comprises FPGA program element (3) and storer (4); The program that described storer (4) comprises as boot section stores A district (41), and the program storing application program stores B district (42); Said method comprising the steps of:
S10: when fpga chip (2) powers on, first stores A district (41) download file from the program of storer (4) and runs, and generate FPGA program element (3);
S20: after described fpga chip (2) has run, processor (1) externally sends indicator signal, control described fpga chip (2) by described processor (1) to restart, described fpga chip (2) stores down load application program B district (42) from the program of described storer (4) and runs.
11. a kind of FPGA reconstructing methods according to claim 10, it is characterized in that: described FPGA program element (3) comprises application program unit (31) and reconstruct trigger element (32), and described application program unit (31) comprises port controller (311); Described program stores the program storing in A district (41) and generate described reconstruct trigger element (32) and port controller (311), after described fpga chip (2) has run, generate described reconstruct trigger element (32) and port controller (311), described processor (1) accesses described storer (4) by described port controller (311).
12. a kind of FPGA reconstructing methods according to claim 11, it is characterized in that, under accidental conditions, described step S20 comprises further:
Described processor (1) waits for that described fpga chip (2) completes postrun indicator signal, and after described indicator signal arrives, reconstruct trigger element (32) to described fpga chip (2) sends trigger pip, controls described fpga chip (2) and restarts.
13. a kind of FPGA reconstructing methods according to claim 11 or 12, it is characterized in that, under FPGA program updates operating mode, described step S20 comprises further:
Described processor (1) waits for that described fpga chip (2) completes postrun indicator signal, described processor (1) upgrades the application program that described program stores the described fpga chip (2) in B district (42) after described indicator signal arrives, send trigger pip by described processor (1) to the reconstruct trigger element (32) of described FPGA program element (3) after renewal completes, control described fpga chip (2) and restart.
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