CN105278976B - A kind of FPGA reconstruct device, system and method - Google Patents
A kind of FPGA reconstruct device, system and method Download PDFInfo
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- CN105278976B CN105278976B CN201410322231.4A CN201410322231A CN105278976B CN 105278976 B CN105278976 B CN 105278976B CN 201410322231 A CN201410322231 A CN 201410322231A CN 105278976 B CN105278976 B CN 105278976B
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Abstract
The invention discloses a kind of FPGA to reconstruct device, system and method, and reconstruct device includes fpga chip, and fpga chip includes FPGA program unit and memory.Memory includes the program storage area A as boot section, and is stored with the program storage area B of application program.When fpga chip powers on, first running paper is downloaded from the program storage area A, and generate FPGA program unit, after the completion of fpga chip operation, indication signal is issued to external processor, by processor control fpga chip restarting, fpga chip downloading application program operation from the program storage area B.The present invention can be efficiently solved through risk present in update processor FPGA program process, ensure even if at no point in the update process due to can still complete the process by update processor FPGA program under some unpredictable abnormal conditions of the operation of mistake, unexpected power-off etc..
Description
Technical field
The present invention relates to electronic circuit technology fields, more particularly, to a kind of FPGA weight applied to programmable logic device
Structure device, system and method.
Background technique
With the development and growth of programmable logic technology, especially FPGA technology, almost all of product can all be used
Fpga chip, therefore, it is difficult to avoid FPGA program from needing to realize application program more by circuit reconfiguration due to design defect
Newly.The essence of circuit reconfiguration is that have the characteristic that can repeatedly configure using programmable FPGA, calls different configurations as needed
File changes the logical construction of circuit, so that system be made to have, flexible, simple and direct, hardware resource is reusable, easily scalable etc. more
Kind excellent performance.Reconfigurable system usually in both cases reconfigures FPGA: first is that fpga logic function needs
Conversion, such as the mistake on algorithm improvement or discovery design；Second is that function is lost caused by mistake occurs for FPGA configuration data
Effect.
The included internal SPI FLASH of the SPARTAN3AN Series FPGA chip of XILINX company is stored as FPGA program
Device, when the product for using this chip development is needed through update processor FPGA program, if at no point in the update process, out
When now such as power-off suddenly, the unpredictable reason of program error code etc. cause to update unsuccessful, then not only update it is unsuccessful, also
The program stored inside original SPI FLASH can be damaged, so that fpga chip is not normally functioning.Meanwhile it further resulting in
It has not been existed inside FPGA by the SPI controller that logical language is realized, processor also just can not be with the SPI inside fpga chip
FLASH establishes connection, to cannot can only pass through fpga chip again through the application program of update processor FPGA
JTAG mouthfuls download applications into SPI FLASH.
The prior art is usually the update in products application scene progress FPGA application program, and the mistake that live program updates
Journey is a huge and arduous engineering.Traditional method is all to update FPGA program by jtag interface, this is firstly the need of tearing open
The shell of product is opened, program is then downloaded to FPGA by the jtag interface of fpga chip using dedicated FPGA Program download
In the program storage of chip.This method is very inefficient, and most of working time is all wasted in disassembly, on completed knocked down products, is
The inefficiency problem of this traditional FPGA method for updating program of solution, the new method by update processor FPGA program is not
It is disconnected to occur, however in the actual implementation process, it, then can not be again by processing when more new procedures proceed to half and malfunction
Device updates FPGA program, still needs to dismantle product, FPGA program is still updated by jtag interface, can not thoroughly solve to pass
System FPGA method for updating program.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of FPGA to reconstruct device, system and method, can effectively solve
Certainly pass through risk present in update processor FPGA program process, it is ensured that though at no point in the update process due to the operation of mistake,
Suddenly under some unpredictable abnormal conditions of power-off etc., the mistake by update processor FPGA program can be still completed
Journey.
In order to achieve the above-mentioned object of the invention, the present invention specifically provides a kind of technic relization scheme of FPGA reconfiguration system,
A kind of FPGA reconstruct device, comprising: fpga chip, the fpga chip include FPGA program unit and memory.The storage
Device includes the program storage area A as boot section, and is stored with the program storage area B of application program.When the fpga chip
When powering on, running paper first is downloaded from the described program storage area A, and generate FPGA program unit, when the fpga chip is run
After the completion, indication signal is issued to external processor, the fpga chip is controlled by the processor and is restarted, it is described
Fpga chip downloading application program operation from the program storage area B.
Preferably, the FPGA program unit includes application program unit and reconstruct trigger unit, the application program list
Member includes port controller.Described program storage is stored with the journey for generating the reconstruct trigger unit and port controller in the area A
Sequence, after the completion of fpga chip operation, generating the reconstruct trigger unit and port controller, the processor can pass through
The port controller accesses the memory.Under accidental conditions, after the completion of fpga chip operation, to outside
Processor issue indication signal, the reconstruct from from the processor to the FPGA program unit after indication signal arrival
Trigger unit issues trigger signal, controls the fpga chip restarting.
Preferably, it in the case where FPGA program updates operating condition, after the completion of fpga chip operation, is sent out to external processor
Indication signal out, the processor update the fpga chip in the described program storage area B after indication signal arrival
Application program, after the completion of update from the processor to the reconstruct trigger unit of the FPGA program unit issue triggering letter
Number, control the fpga chip restarting.
Preferably, the reconstruct trigger unit includes command word r/w cell and internal configuration access unit, the command word
R/w cell controls the working condition of the internal configuration access unit, institute to the internal configuration access unit writing commands word
Internal configuration access unit is stated for controlling the memory to the FPGA program unit loading configuration file.
Preferably, the fpga chip is connected by spi bus with the processor of the outside.
Preferably, the memory is the SPI FLASH inside the fpga chip, and the port controller is SPI control
Device processed.
In addition the present invention also specifically provides a kind of technic relization scheme of FPGA reconfiguration system, a kind of FPGA reconstruct system
System, comprising: FPGA as described above reconstructs device, and the processor being connected with FPGA reconstruct device.
Preferably, under accidental conditions, the instruction after the completion of the processor waits the fpga chip to run is believed
Number, and after indication signal arrival, the reconstruct trigger unit of Xiang Suoshu FPGA program unit issues trigger signal.
Preferably, in the case where FPGA program updates operating condition, the processor waits the finger after the completion of the fpga chip operation
Show that signal, the processor update answering for the fpga chip in the described program storage area B after indication signal arrival
With program, trigger signal is issued from the processor to the reconstruct trigger unit of the FPGA program unit after the completion of update.
In addition the present invention also specifically provides a kind of technic relization scheme of FPGA reconstructing method, FPGA reconstruct device includes
Fpga chip, the fpga chip include FPGA program unit and memory；The memory includes the program as boot section
The area A is stored, and is stored with the program storage area B of application program；It the described method comprises the following steps:
S10: when fpga chip powers on, running paper first is downloaded from the program of the memory storage area A, and generate FPGA journey
Sequence unit；
S20: after the completion of fpga chip operation, indication signal is issued to external processor, by the processor
The fpga chip restarting is controlled, the fpga chip downloads application program from the program of the memory storage area B
Operation.
Preferably, the FPGA program unit includes application program unit and reconstruct trigger unit, the application program list
Member includes port controller；Described program storage is stored with the journey for generating the reconstruct trigger unit and port controller in the area A
Sequence, after the completion of fpga chip operation, generating the reconstruct trigger unit and port controller, the processor can pass through
The port controller accesses the memory.
Preferably, under accidental conditions, the step S20 further comprises:
The processor waits the fpga chip to complete postrun indication signal, and arrives in the indication signal
Afterwards, the reconstruct trigger unit of Xiang Suoshu fpga chip issues trigger signal, controls the fpga chip restarting.
Preferably, in the case where FPGA program updates operating condition, the step S20 further comprises:
The processor waits the fpga chip to complete postrun indication signal, and the processor is believed in the instruction
Number arrive after update described program storage the area B in the fpga chip application program, by the processor after the completion of update
Trigger signal is issued to the reconstruct trigger unit of the FPGA program unit, controls the fpga chip restarting.
Device, system and method are reconstructed by implementing the FPGA that aforementioned present invention provides, is had the following technical effect that
(1) it when the present invention uses the memory inside fpga chip as FPGA program storage area, can highly reliably adopt
The FPGA program in external update processor memory is taken, even if malfunctioning at no point in the update process, damage is also that program is deposited
The program in the area B is stored up, and the bootstrap in the program storage area A will not be damaged always, the FPGA program in the program storage area A still may be used
With；Fpga chip can still run the FPGA program in the program storage area A after re-powering, processor can still pass through program
It stores the interface controller inside the area A program and accesses memory；
(2) present invention can be efficiently solved through risk present in update processor FPGA program process, it is ensured that i.e.
Make at no point in the update process due to the operation of mistake, power-off etc. suddenly, still can be complete under some unpredictable abnormal conditions
At the process for passing through update processor FPGA program.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of system structure diagram of specific embodiment of FPGA reconfiguration system of the present invention；
Fig. 2 is a kind of journey of the fpga chip of specific embodiment of FPGA reconstructing method of the present invention under accidental conditions
Program flow diagram；
Fig. 3 is a kind of program of the processor of specific embodiment of FPGA reconstructing method of the present invention under accidental conditions
Flow chart；
Fig. 4 is that a kind of fpga chip of specific embodiment of FPGA reconstructing method of the present invention updates under operating condition in FPGA program
Program flow diagram；
Fig. 5 is that a kind of processor of specific embodiment of FPGA reconstructing method of the present invention updates under operating condition in FPGA program
Program flow diagram；
In figure: 1- processor, 2-FPGA chip, 3-FPGA program unit, 4- memory, 31- application program unit, 32-
Reconstruct trigger unit, 311- port controller, 321- command word r/w cell, the inside 322- configuration access unit, the storage of 41- program
The area A, 42-programs store the area B.
Specific embodiment
For the sake of quoting and understanding, will hereafter used in technical term, write a Chinese character in simplified form or abridge and be described below:
XILINX: being a design, manufacture, the company for selling fpga chip；
SPARTAN3AN: being a model of XILINX company fpga chip；
CPU:Central Processing Unit, the abbreviation of central processing unit；
FPGA:Field Programmable Gate Array, the abbreviation of field programmable gate array；
SPI:Serial Peripheral Interface, the abbreviation of Serial Peripheral Interface；
FLASH: the abbreviation of flash memory；
ICAP:Internal Configuration Access Port, the abbreviation of internal configuration access port.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the technical scheme in the embodiment of the invention is clearly and completely described.Obviously, described embodiment is only
It is only a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, the common skill in this field
Art personnel every other embodiment obtained without creative efforts belongs to the model that the present invention protects
It encloses.
As shown in attached drawing 1 to attached drawing 5, the specific embodiment that FPGA of the present invention reconstructs device, system and method is given, under
The invention will be further described with reference to the drawings and specific embodiments in face.
As shown in Fig. 1, a kind of specific embodiment of FPGA reconstruct device, it includes: fpga chip 2 that FPGA, which reconstructs device,
Fpga chip 2 includes FPGA program unit 3 and memory 4.Memory 4 includes the program storage area A 41 as boot section, and
It is stored with the program storage area B 42 of application program (i.e. the configurator of fpga chip 2).When fpga chip 2 powers on, first from journey
Sequence stores the area A 41 and downloads running paper, and generates FPGA program unit 3, after the completion of the operation of fpga chip 2, to external place
Manage device 1(CPU) indication signal is issued, fpga chip 2 is controlled by processor 1 and is restarted, fpga chip 2 stores the area B from program
Application program operation is downloaded in 42.
As a kind of typical specific embodiment of the present invention, fpga chip 2 further passes through spi bus and external processing
Device 1 is connected.Memory 4 is the SPI FLASH inside fpga chip 2, and port controller 311 is further SPI controller, FPGA
The port controller 311 of chip 2 is further connected by spi bus with memory 4.It is, of course, also possible to take other interfaces
It substitutes SPI interface building FPGA and reconstructs device.
As a kind of typical specific embodiment of the present invention, FPGA program unit 3 further comprises application program unit 31
With reconstruct trigger unit 32, application program unit 31 includes port controller 311.Program storage is stored with generation weight in the area A 41
The program of structure trigger unit 32 and port controller 311 generates reconstruct 32 He of trigger unit after the completion of the operation of fpga chip 2
Port controller 311, processor 1 can access memory 4 by port controller 311.Processor 1 passes through SPI interface and FPGA
Chip 2 is connected, fpga chip 2 is connected by internal SPI controller with internal SPI FLASH.Inside fpga chip 2
SPI controller be to be realized by FPGA program, if will be unable to and internal without FPGA program or program corruption
SPI FLASH establishes a connection.
SPI FLASH inside fpga chip 2 is divided into two memory blocks by the specific embodiment of the invention: program stores A
Area 41 and program store the area B 42.Wherein, the program storage area A 41 is used as boot section, and the program storage area B 42 is used as main program area.
The program that the program storage area A 41 is stored only includes following function: reconstruct two parts of trigger unit 32 and SPI controller.Journey
The main function that sequence stores the area A 41 is for providing a SPI controller, as the SPI inside processor 1 and fpga chip 2
The interface channel of FLASH, while triggering fpga chip 2 and restarting, 42 download configuration file of the area B (i.e. application program) is stored from program
Operation.And the program that the program storage area B 42 is stored is application program, does not include generating reconstruct trigger unit 32 and SPI control
The program of device processed.
The FPGA reconstruct device of specific embodiment of the invention description is under accidental conditions, when fpga chip 2 has been run
Cheng Hou issues indication signal to external processor 1, from processor 1 to the weight of FPGA program unit 3 after indication signal arrival
Structure trigger unit 32 issues trigger signal, and control fpga chip 2 restarts.
The FPGA reconstruct device of specific embodiment of the invention description is in the case where FPGA program updates operating condition, when fpga chip 2 is transported
After the completion of row, indication signal is issued to external processor 1, stores the area B by the more new procedures of processor 1 after indication signal arrival
The application program of fpga chip 2 in 42.At this point, processor 1 can access memory 4 by port controller 311, applying
Trigger signal is issued from processor 1 to the reconstruct trigger unit 32 of FPGA program unit 3 after the completion of program update, controls FPGA core
Piece 2 restarts.
As a kind of typical specific embodiment of the present invention, reconstruct trigger unit 32 further comprises command word r/w cell
321 and internal configuration access unit 322.The internally 322 writing commands word of configuration access unit of command word r/w cell 321, control
The working condition of internal configuration access unit 322.And internal configuration access unit 322(ICAP:Internal
Configuration Access Port), as module intrinsic in fpga chip 2, for controlling memory 4 to FPGA journey
3 loading configuration file of sequence unit.
A kind of specific embodiment of FPGA reconfiguration system, comprising: FPGA as described above reconstructs device, and heavy with FPGA
The connected processor 1 of structure device.
Under accidental conditions, processor 1 waits the indication signal after the completion of the operation of fpga chip 2, and believes in instruction
Number arrive after, to the reconstruct trigger unit 32 of FPGA program unit 3 issue trigger signal.
In the case where FPGA program updates operating condition, processor 1 waits the indication signal after the completion of the operation of fpga chip 2, processor 1
The application program of fpga chip 2 after indication signal arrival in the more new procedures storage area B 42, by processor 1 after the completion of update
Trigger signal is issued to the reconstruct trigger unit 32 of FPGA program unit 3.
The FPGA reconfiguration system of specific embodiment of the invention description is deposited to solve to update in FPGA program process by CPU
Risk, the SPI FLASH inside fpga chip 2 is divided into two regions: program stores the area A 41 and program stores the area B 42,
Wherein program storage the area A 41 be used as boot section, program store the area B 42 be used as main program area, carry out the update of FPGA program when
The program for waiting the only more new procedures storage area B 42 is ensured that in this way even if at no point in the update process due to the operation of mistake, disconnected suddenly
Under some unpredictable abnormal conditions of electricity etc., damage also be program storage the area B 42 FPGA program, and program store
FPGA program in the area A 41 still can be used.After fpga chip 2 re-powers, fpga chip 2 can run the program storage area A
FPGA program in 41, the SPI controller that processor 1 can be still stored by program in the bootstrap in the area A 41 access
SPI FLASH inside fpga chip 2.No matter this FPGA that specific embodiment of the invention is described reconstruct device is in which kind of feelings
Under condition, it can ensure that FPGA program can be updated by CPU, even if can also pass through processing in the case where malfunctioning at no point in the update process
Device 1(CPU) again remotely update FPGA in application program.
A kind of specific embodiment of FPGA reconstructing method, it includes fpga chip 2 that FPGA, which reconstructs device, and fpga chip 2 includes
FPGA program unit 3 and memory 4.Memory 4 includes the program storage area A 41 as boot section, and is stored with using journey
The program of sequence stores the area B 42.FPGA reconstructing method the following steps are included:
S10: when fpga chip 2 powers on, running paper first is downloaded from the program of the memory 4 storage area A 41, and generate
FPGA program unit 3；
S20: after the completion of the operation of fpga chip 2, indication signal is issued to external processor 1, is controlled by processor 1
Fpga chip 2 restarts, the downloading application program operation from the program of the memory 4 storage area B 42 of fpga chip 2.
FPGA program unit 3 includes application program unit 31 and reconstruct trigger unit 32, and application program unit 31 includes end
Mouth controller 311.Program storage is stored with the program for generating reconstruct trigger unit 32 and port controller 311 in the area A 41, when
After the completion of fpga chip 2 is run, port controller can be passed through by generating reconstruct trigger unit 32 and port controller 311, processor 1
311 access memories 4.
Under accidental conditions, step S20 further comprises:
Processor 1 waits fpga chip 2 to complete postrun indication signal, and after indication signal arrival, to FPGA core
The reconstruct trigger unit 32 of piece 2 issues trigger signal, and control fpga chip 2 restarts.
In the case where FPGA program updates operating condition, step S20 further comprises:
Processor 1 waits fpga chip 2 to complete postrun indication signal, and processor 1 updates after indication signal arrival
Program stores the application program of the fpga chip 2 in the area B 42, the reconstruct after the completion of update from processor 1 to FPGA program unit 3
Trigger unit 32 issues trigger signal, and control fpga chip 2 restarts.As shown in Fig. 2, it is normally being transported for fpga chip 2
A kind of embodiment of program operational process under row operating condition, specifically includes the following steps:
(1) after fpga chip 2 powers on every time, fpga chip 2 is always first from the program storage of internal SPI FLASH
The operation of 41 download configuration file of the area A；
(2) after fpga chip 2 is run successfully, reconstruct trigger unit 32 and port controller 311 are generated, processor 1 can
To access memory 4 by port controller 311, fpga chip 2 provides indication signal notifier processes device 1；If operation not at
Function then continues from storage 41 download configuration file of the area the A operation of the program of SPI FLASH；
(3) trigger signal that fpga chip 2 waits processor 1 to issue to the reconstruct trigger unit 32 of fpga chip 2；
(4) if receiving the trigger signal of the sending of processor 1, fpga chip 2 restarts；If not receiving processing
The trigger signal that device 1 issues then continues waiting for the trigger signal of the sending of processor 1；
(5) fpga chip 2 stores 42 download configuration file of the area B (i.e. application program) from the program of internal SPI FLASH
Operation.
It as shown in Fig. 3, is a kind of embodiment of program operational process of the processor 1 under accidental conditions, specifically
The following steps are included:
(1) processor 1 waits the operation of fpga chip 2 to complete indication signal；
(2) processor 1 issues trigger signal to fpga chip 2 after indication signal arrival.
As shown in Fig. 4, a kind of implementation of the program operational process under operating condition is updated in FPGA program for fpga chip 2
Example, specifically includes the following steps:
(1) after fpga chip 2 powers on every time, fpga chip 2 is always first from the program storage of internal SPI FLASH
The operation of 41 download configuration file of the area A；
(2) after fpga chip 2 is run successfully, reconstruct trigger unit 32 and port controller 311 are generated, processor 1 can
To access memory 4 by port controller 311, fpga chip 2 provides indication signal notifier processes device 1；If operation not at
Function then continues from storage 41 download configuration file of the area the A operation of the program of SPI FLASH；
(3) trigger signal that fpga chip 2 waits processor 1 to issue to the reconstruct trigger unit 32 of fpga chip 2；
(4) if receiving the trigger signal of the sending of processor 1, fpga chip 2 restarts；If not receiving processing
The trigger signal that device 1 issues then continues waiting for the trigger signal of the sending of processor 1；
(5) fpga chip 2 stores 42 download configuration file of the area B (i.e. application program) from the program of internal SPI FLASH
Operation.
As shown in Fig. 5, a kind of embodiment of the program operational process under operating condition is updated in FPGA program for processor 1,
Specifically includes the following steps:
(1) processor 1 waits the operation of fpga chip 2 to complete indication signal；
(2) program that processor 1 updates the SPI FLASH inside fpga chip 2 after indication signal arrival stores the area B 42
In FPGA program, at this time processor 1 can by port controller 311 access memory 4, to update SPI FLASH's
Program stores the FPGA program in the area B 42；
(3) processor 1 issues trigger signal to fpga chip 2.
FPGA by implementing specific embodiment of the invention description reconstructs device, system and method, can generate following skill
Art effect:
(1) technical solution of specific embodiment of the invention description uses the memory inside fpga chip as FPGA program
When memory block, the FPGA program in external update processor memory can be highly reliably taken, even if at no point in the update process
Error, damage also be program storage the area B program, and program storage the area A bootstrap will not damage always, program is deposited
The FPGA program in the storage area A still can be used；Fpga chip can still run the FPGA program in the program storage area A after re-powering,
The interface controller that processor can still be stored inside the area A program by program accesses memory；
(2) technical solution of specific embodiment of the invention description can be efficiently solved through update processor FPGA program
Existing risk in the process, it is ensured that even if at no point in the update process since the operation of mistake, unexpected power-off etc. are some unpredictable
Abnormal conditions under, can still complete the process by update processor FPGA program.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.Though
So the present invention is disclosed as above with preferred embodiment, and however, it is not intended to limit the invention.It is any to be familiar with those skilled in the art
Member, in the case where not departing from Spirit Essence of the invention and technical solution, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications or equivalent example modified to equivalent change to technical solution of the present invention.Therefore,
Anything that does not depart from the technical scheme of the invention are made to the above embodiment any simple according to the technical essence of the invention
Modification, equivalent replacement, equivalence changes and modification, all of which are still within the scope of protection of the technical scheme of the invention.
Claims (9)
1. a kind of FPGA reconstructs device, it is characterised in that: including fpga chip (2), the fpga chip (2) includes FPGA program
Unit (3) and memory (4)；The memory (4) includes the program storage area A (41) as boot section, and is stored with and answers
The area B (42) are stored with the program of program；When the fpga chip (2) powers on, first stores from described program and publish papers under the area A (41)
Part operation, and FPGA program unit (3) are generated, after the completion of the fpga chip (2) operation, sent out to external processor (1)
Indication signal out controls the fpga chip (2) by the processor (1) and restarts, and the fpga chip (2) is deposited from program
Store up downloading application program operation in the area B (42)；The FPGA program unit (3) includes application program unit (31) and reconstruct triggering
Unit (32), the application program unit (31) include port controller (311)；It is stored in the described program storage area A (41)
The program for generating reconstruct trigger unit (32) and port controller (311), after the completion of the fpga chip (2) operation,
The reconstruct trigger unit (32) and port controller (311) are generated, the processor (1) can pass through the port controller
(311) memory (4) is accessed；Under accidental conditions, after the completion of the fpga chip (2) operation, to outside
Processor (1) issues indication signal, by the processor (1) Xiang Suoshu FPGA program unit after indication signal arrival
(3) reconstruct trigger unit (32) issues trigger signal, controls the fpga chip (2) restarting；It is updated in FPGA program
Under operating condition, after the completion of the fpga chip (2) operation, indication signal, the processor are issued to external processor (1)
(1) application program that the fpga chip (2) in the described program storage area B (42) is updated after indication signal arrival, updates
Trigger signal, control are issued by the reconstruct trigger unit (32) of the processor (1) Xiang Suoshu FPGA program unit (3) after the completion
Fpga chip (2) restarting.
2. a kind of FPGA according to claim 1 reconstructs device, it is characterised in that: the reconstruct trigger unit (32) includes
Command word r/w cell (321) and internal configuration access unit (322), the command word r/w cell (321) configure to the inside
Access unit (322) writing commands word controls the working condition of the internal configuration access unit (322), the internal configuration
Access unit (322) is for controlling the memory (4) Xiang Suoshu FPGA program unit (3) loading configuration file.
3. a kind of FPGA according to claim 1 or 2 reconstructs device, it is characterised in that: the fpga chip (2) passes through
Spi bus is connected with the processor (1) of the outside.
4. a kind of FPGA according to claim 3 reconstructs device, it is characterised in that: the memory (4) is the FPGA
The internal SPI FLASH of chip (2), the port controller (311) are SPI controller.
5. a kind of FPGA reconfiguration system characterized by comprising such as the described in any item FPGA reconstruct dresses of Claims 1-4
It sets, and the processor (1) being connected with FPGA reconstruct device.
6. a kind of FPGA reconfiguration system according to claim 5, it is characterised in that: under accidental conditions, the place
The indication signal after the completion of device (1) waits the fpga chip (2) to run is managed, and after indication signal arrival, Xiang Suoshu
The reconstruct trigger unit (32) of FPGA program unit (3) issues trigger signal.
7. a kind of FPGA reconfiguration system according to claim 5 or 6, it is characterised in that: in the case where FPGA program updates operating condition,
The processor (1) waits the indication signal after the completion of fpga chip (2) operation, and the processor (1) is in the instruction
Signal updates the application program of the fpga chip (2) in the described program storage area B (42) after arriving, by institute after the completion of update
The reconstruct trigger unit (32) for stating processor (1) Xiang Suoshu FPGA program unit (3) issues trigger signal.
8. a kind of FPGA reconstructing method, which is characterized in that it includes fpga chip (2) that FPGA, which reconstructs device, the fpga chip (2)
Including FPGA program unit (3) and memory (4)；The memory (4) includes the program storage area A (41) as boot section,
And it is stored with the program storage area B (42) of application program；It the described method comprises the following steps:
S10: when fpga chip (2) powers on, running paper first is downloaded from the program of memory (4) the storage area A (41), and generate
FPGA program unit (3)；
S20: after the completion of the fpga chip (2) operation, indication signal is issued to external processor (1), by the processing
Device (1) controls fpga chip (2) restarting, and the fpga chip (2) stores the area B from the program of the memory (4)
(42) downloading application program operation in；
The FPGA program unit (3) includes application program unit (31) and reconstruct trigger unit (32), the application program list
First (31) include port controller (311)；It is stored in the described program storage area A (41) and generates the reconstruct trigger unit (32)
The reconstruct trigger unit (32) is generated after the completion of the fpga chip (2) operation with the program of port controller (311)
With port controller (311), the processor (1) can access the memory (4) by the port controller (311)；
In the case where FPGA program updates operating condition, the step S20 further comprises:
The processor (1) waits the fpga chip (2) to complete postrun indication signal, and the processor (1) is indicating
Signal updates the application program of the fpga chip (2) in the described program storage area B (42) after arriving, by institute after the completion of update
The reconstruct trigger unit (32) for stating processor (1) Xiang Suoshu FPGA program unit (3) issues trigger signal, controls the FPGA core
Piece (2) restarting.
9. a kind of FPGA reconstructing method according to claim 8, which is characterized in that under accidental conditions, the step
Rapid S20 further comprises:
The processor (1) waits the fpga chip (2) to complete postrun indication signal, and arrives in the indication signal
Afterwards, the reconstruct trigger unit (32) of Xiang Suoshu fpga chip (2) issues trigger signal, controls the fpga chip (2) and opens again
It is dynamic.
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| CN108536458A (en) * | 2018-04-13 | 2018-09-14 | 北京和普威视科技股份有限公司 | A kind of FPGA online upgradings method, apparatus, equipment and storage medium |
| CN110311707B (en) * | 2019-07-02 | 2020-12-29 | 沈阳理工大学 | Multi-criterion constraint-based composite dimension information transmission reconstruction method |
| CN113238985A (en) * | 2021-05-21 | 2021-08-10 | 北京轩宇空间科技有限公司 | FPGA (field programmable Gate array) on-orbit reconstruction control system and method |
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