CN103617056A - FPGA logical code online updating method and device - Google Patents
FPGA logical code online updating method and device Download PDFInfo
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Abstract
The invention provides an FPGA logical code online updating method and device. The method includes the following steps that a first data channel is connected and a second data channel is disconnected when an FPGA is powered on and initialized; initialization configuration data of a configuration memory are loaded to the FPGA; after loading of the initialization configuration data is finished, the second data channel is connected and the first data channel is disconnected; FPGA updating data received remotely are updated to the configuration memory; after the updating data are updated, the first data channel is connected and the second data channel is disconnected; low-level pulses output by a monostable trigger triggers the FPGA to load the updating data from the configuration memory. According to the FPGA logical code online updating method and device, the low-level pulses output by the monostable trigger triggers the FPGA to load the updating data from the configuration memory, so that an MCU is not needed, cost is low and a system is reliable.
Description
Technical field
The present invention relates to electronic circuit technology field, particularly relate to a kind of online upgrading method and apparatus of fpga logic code.
Background technology
FPGA(Field-Programmable Gate Array, field programmable gate array) be at PAL(Programming Array Logic, programmable logic array), GAL(Generic Array Logic, generic array logic), CPLD(Complex Programmable Logic Device, CPLD) etc. the product that further develops on the basis of programming device.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, has overcome again the limited shortcoming of original programming device gate circuit number.
Traditional FPGA online upgrading circuit, as shown in Figure 1, comprises FPGA, MCU(Micro Control Unit, micro-control unit), analog switch, config memory (for example Flash).The course of work is as follows:
When carrying out FPGA power-up initializing, the SEL pin of MCU analog switch is set to low level, and the B1 mouth of analog switch is just communicated with A mouth, and namely the pin of FPGA is communicated with Flash, and FPGA loads initial configuration data from Flash;
After completing the loading of initial configuration data, the SEL pin of MCU analog switch is set to high level, the B2 mouth of analog switch is just communicated with A mouth, and namely the pin of MCU is communicated with Flash, and the upgrade data of the long-range described FPGA receiving is updated to Flash;
After completing upgrade data renewal, the MCU again SEL pin of analog switch is set to low level, the B1 mouth of analog switch is just communicated with A mouth, then MCU drags down certain hour (being greater than for 500 nanoseconds) by the PROGRAM_B pin of FPGA, described FPGA loads described upgrade data from described config memory, impels FPGA to reconfigure.
This traditional online upgrading circuit, needs the cooperation of MCU just can complete, thereby has following shortcoming:
1, MCU need to have developer to remove to develop and safeguard the code of itself, has increased human cost;
2, relative other common components and parts of MCU, price is relatively high, has increased hardware cost;
3, MCU is micro-control unit device, and thrashing probability is large, needs to add other components and parts simultaneously and forms complete control circuit, such as components and parts such as crystal oscillators, the dimensional space of circuit board be there are certain requirements etc.
Summary of the invention
Based on this, be necessary for the problems referred to above, the online upgrading method and apparatus of a kind of low cost and highly reliable fpga logic code is provided.
An online upgrading method for fpga logic code, comprises step:
When carrying out FPGA power-up initializing, the first data channel of the analog switch between FPGA configuration pin and config memory is communicated with, and the second data channel of the described analog switch between the general pin of described FPGA and described config memory disconnects;
The initial configuration data of described config memory are loaded into described FPGA;
After completing the loading of initial configuration data, described the second data channel is communicated with, described the first data channel disconnects;
The upgrade data of the long-range described FPGA receiving is updated to described config memory;
After completing upgrade data renewal, described the first data channel is communicated with, described the second data channel disconnects;
The low level pulse of monostalbe trigger output triggers described FPGA and loads described upgrade data from described config memory.
An online upgrading device for fpga logic code, comprising:
FPGA, for loading the initial configuration data of config memory when the power-up initializing, or completes the upgrade data that loads described config memory after upgrade data upgrades;
Input end is connected with the IO mouth of described FPGA, and output terminal holds with the PROGRAM_B of described FPGA the monostalbe trigger being connected, and for FPGA described in output low level trigger action, from described config memory, loads described upgrade data;
Analog switch between described FPGA and config memory, be used for when carrying out FPGA power-up initializing or complete after upgrade data renewal, to be communicated with the first data channel between config memory in FPGA configuration pin, the second data channel between the general pin of described FPGA and described config memory disconnects; Or after completing the loading of initial configuration data, described the first data channel is disconnected, described the second data channel is communicated with;
The config memory being connected with described analog switch, for the upgrade data of store initialization configuration data or the long-range described FPGA receiving.
The online upgrading method and apparatus of above-mentioned fpga logic code, the function of the general pin simulation SPI interface read-write config memory of described FPGA, the low level pulse of described monostalbe trigger output triggers described FPGA and loads described upgrade data from described config memory, no longer needs MCU.And monostalbe trigger belongs to general function device, being all better than MCU aspect price, development and maintenance, size etc., reduced thrashing probability simultaneously, make system more reliable.
Accompanying drawing explanation
Fig. 1 is prior art FPGA online upgrading circuit diagram;
Fig. 2 is the schematic flow sheet of the inventive method embodiment;
Fig. 3 is the online upgrading circuit diagram of embodiment of the present invention fpga logic code;
Fig. 4 is the online upgrading working timing figure of embodiment of the present invention fpga logic code;
Fig. 5 is the structural representation of apparatus of the present invention embodiment.
Embodiment
Below in conjunction with accompanying drawing, the embodiment of the inventive method is described in detail.
As shown in Figure 2, a kind of online upgrading method of fpga logic code, comprises step:
S100, when carrying out FPGA power-up initializing, the first data channel of the analog switch between FPGA configuration pin and config memory is communicated with, and the second data channel of the described analog switch between the general pin of described FPGA and described config memory disconnects;
S110, the initial configuration data of described config memory are loaded into described FPGA;
S120, after completing initial configuration data and loading, described the second data channel is communicated with to described the first data channel disconnection;
S130, the upgrade data of the long-range described FPGA receiving is updated to described config memory;
S140, after completing upgrade data and upgrading, described the first data channel is communicated with to described the second data channel disconnection;
The low level pulse (being greater than for 500 nanoseconds) of S150, monostalbe trigger output triggers described FPGA and loads described upgrade data from described config memory.
The present invention's config memory used can be non-volatile EPROM, EEPROM or flash memory, and Flash is for example used for storing the initial configuration data of FPGA or upgrade data etc.When the configuration pin CFG_DONE signal of described FPGA sets high again, described upgrade data has loaded.
As an embodiment, described the first data channel is communicated with in step S100 or step S140, the step that described the second data channel disconnects comprises: by described analog switch enable control end (OE) and switch selecting side (SEL) is set to low level; Described the second data channel is communicated with in step S120, the step that described the first data channel disconnects comprises: will described in enable that control end (OE) is set to low level, described switch selecting side (SEL) is set to high level.
As an embodiment, the input end of the described monostalbe trigger being connected with the IO mouth of described FPGA is clear terminal, negative edge trigger end or rising edge trigger end, and the described monostalbe trigger output low level pulse in step S150 comprises:
If described input end is clear terminal, described IO mouth is become to high level from low level, described negative edge trigger end is set to low level, and described rising edge trigger end is set to high level; Or,
If described input end is negative edge trigger end, described IO mouth is become to low level from high level, described clear terminal and described rising edge trigger end are all set to high level; Or,
If described input end is rising edge trigger end, described IO mouth is become to high level from low level, described clear terminal is set to high level, and described negative edge trigger end is set to low level.
As an embodiment, in step S100 when carrying out FPGA power-up initializing, under pull down resistor effect, described the first data channel is communicated with, described the second data channel disconnects.Also can make by other means the switch selecting side (SEL) of described analog switch in low level, described the first data channel is communicated with, described the second data channel disconnects.
In order to understand more clearly the inventive method, below in conjunction with the online upgrading circuit diagram of fpga logic code, in the mode of a specific embodiment, the embodiment of the inventive method is described in detail.
As shown in Figure 3, the 2nd IO mouth (CFG_SEL) of described FPGA is connected with the switch selecting side (SEL) of described analog switch, and the control end (OE) that enables of described analog switch is set to low level.The described IO mouth (RE_CONFIG) of described FPGA is connected with the negative edge trigger end (A#) of described monostalbe trigger, described rising edge trigger end (B) and described clear terminal (RD#) are set to high level, and described negative pulse output terminal (Q#) is connected with described PROGRAM_B.
When carrying out FPGA power-up initializing, under the effect of pull down resistor (4.7k-10k), the SEL pin original levels of analog switch is low level, as shown in table 1, described the first data channel (A mouth-B1 mouth) is communicated with, the configuration pin of described FPGA: clock (CFG_CCLK), sheet choosing (CFG_CSO_B), configuration data output (CFG_MOSI), configuration data input (CFG_MISO), be communicated with Flash, described FPGA loads initial configuration data from Flash.
Table 1 analog switch function signal table
After completing the loading of initial configuration data, the SEL pin of the described analog switch of described FPGA is set to high level, as shown in table 1, described the second data channel (A mouth-B2 mouth) is communicated with, the general pin of described FPGA: SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS, be communicated with Flash, the upgrade data of the long-range described FPGA receiving is updated to described config memory.
After completing upgrade data renewal, the SEL pin of the described analog switch of described FPGA is set to low level, as shown in table 1, described the first data channel (A mouth-B1 mouth) is communicated with, then described FPGA becomes RE_CONFIG pin into low level (negative edge) from high level, as shown in table 2, the Q# pin of described monostalbe trigger produces the low level pulse that a pulse width was greater than for 500 nanoseconds, wherein pulse width can be by regulating outside capacitance resistance to realize, described low level pulse is input to described PROGRAM_B pin, trigger described FPGA and load described upgrade data from described config memory, reconfigure, when the signal that CFG_DONE detected as described FPGA sets high, described FPGA online upgrading and configuration complete, its working timing figure as shown in Figure 4.
Table 2 monostalbe trigger function signal table
Table is noted: H: high level; L: low level; X: any level; ↑: rising edge; ↓: negative edge;
high level pulse;
low level pulse
Based on same inventive concept, the present invention also provides a kind of online upgrading device of fpga logic code, below in conjunction with accompanying drawing, the embodiment of contrive equipment is described in detail.
As shown in Figure 5, a kind of online upgrading device of fpga logic code, comprising:
FPGA100, for load the initial configuration data of config memory when carrying out power-up initializing, or completes the upgrade data that loads described config memory after upgrade data upgrades;
Input end is connected with the IO mouth of described FPGA, and output terminal holds with the PROGRAM_B of described FPGA the monostalbe trigger 200 being connected, and for FPGA100 described in output low level trigger action, from described config memory 400, loads described upgrade data;
The config memory 400 being connected with described analog switch, for the upgrade data of store initialization configuration data or the long-range described FPGA100 receiving.
The present invention's config memory used can be non-volatile EPROM, EEPROM or flash memory, and Flash is for example used for storing the initial configuration data of FPGA or upgrade data etc.When the configuration pin CFG_DONE signal of described FPGA100 sets high again, described upgrade data has loaded.
As an embodiment, described analog switch 300 enable control end and switch selecting side is set to low level, make that described the first data channel is communicated with, the second data channel disconnects; Described analog switch 300 enable that control end is set to low level, switch selecting side is set to high level, make that described the second data channel is communicated with, the first data channel disconnects.
As an embodiment, the input end of described monostalbe trigger 200 is clear terminal, negative edge trigger end or rising edge trigger end;
If described input end is clear terminal, described FPGA100 becomes described IO mouth into high level from low level, the described negative edge trigger end of described monostalbe trigger 200 is set to low level, described rising edge trigger end is set to high level, described monostalbe trigger 200 output low level pulses; Or,
If described input end is negative edge trigger end, described FPGA100 becomes described IO mouth into low level from high level, described monostalbe trigger 200 is all set to high level by described clear terminal and described rising edge trigger end, described monostalbe trigger 200 output low level pulses; Or,
If described input end is rising edge trigger end, described FPGA100 becomes described IO mouth into high level from low level, the described clear terminal of described monostalbe trigger 200 is set to high level, described negative edge trigger end is set to low level, described monostalbe trigger 200 output low level pulses.
As an embodiment, described analog switch 300, for when carrying out FPGA power-up initializing, under pull down resistor effect, is communicated with described the first data channel, and described the second data channel disconnects.Also can make by other means the switch selecting side (SEL) of described analog switch 300 in low level, described the first data channel is communicated with, described the second data channel disconnects.
The above embodiment has only expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (8)
1. an online upgrading method for fpga logic code, is characterized in that, comprises step:
When carrying out FPGA power-up initializing, the first data channel of the analog switch between FPGA configuration pin and config memory is communicated with, and the second data channel of the described analog switch between the general pin of described FPGA and described config memory disconnects;
The initial configuration data of described config memory are loaded into described FPGA;
After completing the loading of initial configuration data, described the second data channel is communicated with, described the first data channel disconnects;
The upgrade data of the long-range described FPGA receiving is updated to described config memory;
After completing upgrade data renewal, described the first data channel is communicated with, described the second data channel disconnects;
The low level pulse of monostalbe trigger output triggers described FPGA and loads described upgrade data from described config memory.
2. the online upgrading method of fpga logic code according to claim 1, it is characterized in that, described the first data channel is communicated with, and the step that described the second data channel disconnects comprises: described analog switch enable control end and switch selecting side is set to low level; Described the second data channel is communicated with, and the step that described the first data channel disconnects comprises: described in enable that control end is set to low level, described switch selecting side is set to high level.
3. the online upgrading method of fpga logic code according to claim 1, it is characterized in that, the input end of the described monostalbe trigger being connected with the IO mouth of described FPGA is clear terminal, negative edge trigger end or rising edge trigger end, and the step of described monostalbe trigger output low level pulse comprises:
If described input end is clear terminal, described IO mouth is become to high level from low level, described negative edge trigger end is set to low level, and described rising edge trigger end is set to high level; Or,
If described input end is negative edge trigger end, described IO mouth is become to low level from high level, described clear terminal and described rising edge trigger end are all set to high level; Or,
If described input end is rising edge trigger end, described IO mouth is become to high level from low level, described clear terminal is set to high level, and described negative edge trigger end is set to low level.
4. according to the online upgrading method of the fpga logic code described in claims 1 to 3 any one, it is characterized in that, when carrying out FPGA power-up initializing, under pull down resistor effect, described the first data channel is communicated with, described the second data channel disconnects.
5. an online upgrading device for fpga logic code, is characterized in that, comprising:
FPGA, for loading the initial configuration data of config memory when the power-up initializing, or completes the upgrade data that loads described config memory after upgrade data upgrades;
Input end is connected with the IO mouth of described FPGA, and output terminal holds with the PROGRAM_B of described FPGA the monostalbe trigger being connected, and for FPGA described in output low level trigger action, from described config memory, loads described upgrade data;
Analog switch between described FPGA and config memory, be used for when carrying out FPGA power-up initializing or complete after upgrade data renewal, to be communicated with the first data channel between config memory in FPGA configuration pin, the second data channel between the general pin of described FPGA and described config memory disconnects; Or after completing the loading of initial configuration data, described the first data channel is disconnected, described the second data channel is communicated with;
The config memory being connected with described analog switch, for the upgrade data of store initialization configuration data or the long-range described FPGA receiving.
6. the online upgrading device of fpga logic code according to claim 5, is characterized in that, described analog switch enable control end and switch selecting side is set to low level, make that described the first data channel is communicated with, the second data channel disconnects; Described analog switch enable that control end is set to low level, switch selecting side is set to high level, make that described the second data channel is communicated with, the first data channel disconnects.
7. the online upgrading device of fpga logic code according to claim 5, is characterized in that, the input end of described monostalbe trigger is clear terminal, negative edge trigger end or rising edge trigger end;
If described input end is clear terminal, described FPGA becomes described IO mouth into high level from low level, the described negative edge trigger end of described monostalbe trigger is set to low level, described rising edge trigger end is set to high level, the pulse of described monostalbe trigger output low level; Or,
If described input end is negative edge trigger end, described FPGA becomes described IO mouth into low level from high level, and described monostalbe trigger is all set to high level by described clear terminal and described rising edge trigger end, the pulse of described monostalbe trigger output low level; Or,
If described input end is rising edge trigger end, described FPGA becomes described IO mouth into high level from low level, the described clear terminal of described monostalbe trigger is set to high level, described negative edge trigger end is set to low level, the pulse of described monostalbe trigger output low level.
8. according to the online upgrading device of the fpga logic code described in claim 5 to 7 any one, it is characterized in that, described analog switch is for when carrying out FPGA power-up initializing, under pull down resistor effect, described the first data channel is communicated with, and described the second data channel disconnects.
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| CN109525276A (en) * | 2018-10-30 | 2019-03-26 | 航天恒星科技有限公司 | A kind of multimode data catenary system having external download function and method |
| CN109525276B (en) * | 2018-10-30 | 2020-11-20 | 航天恒星科技有限公司 | Multimode data link system and method with external downloading function |
| CN110096300A (en) * | 2019-04-08 | 2019-08-06 | 上海赛治信息技术有限公司 | A kind of fpga program file backup management system, operation method and upgrade method |
| CN110265992A (en) * | 2019-06-03 | 2019-09-20 | 深圳市华讯方舟微电子科技有限公司 | A kind of false-touch prevention protection circuit, wireless data transmission module and unmanned plane |
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Address after: Kezhu road high tech Industrial Development Zone, Guangzhou city of Guangdong Province, No. 233 510670 Patentee after: Wei Chong group Limited by Share Ltd Address before: 510663 Guangzhou province high tech Industrial Development Zone, Guangdong, Cai road, No. 6, No. Patentee before: Guangdong Weichuangshixun Science and Technology Co., Ltd. |
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