CN206209364U - Control circuit device based on DSP Yu FPGA - Google Patents
Control circuit device based on DSP Yu FPGA Download PDFInfo
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- CN206209364U CN206209364U CN201621342754.6U CN201621342754U CN206209364U CN 206209364 U CN206209364 U CN 206209364U CN 201621342754 U CN201621342754 U CN 201621342754U CN 206209364 U CN206209364 U CN 206209364U
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Abstract
The utility model provides a kind of control circuit device based on DSP Yu FPGA.The control circuit device includes DSP unit, FPGA unit and resistance unit, and FPGA unit includes the first FPGA module, and resistance unit includes first resistor and second resistance.Control circuit device of the present utility model, it is not necessary to reconfigured to FPGA after each system electrification, can overcome the deficiencies in the prior art.
Description
Technical field
The utility model is related to circuit engineering, more particularly to a kind of control circuit device based on DSP Yu FPGA.
Background technology
At present in the automation equipments such as power electronics, the control system being combined with DSP+FPGA is increasingly becoming market master
Stream.FPGA prices based on RAM are relatively inexpensive, but due to the problem of data disappearance after SRAM power down, after each system electrification, are both needed to
FPGA is reconfigured.
Utility model content
It has been given below on brief overview of the present utility model, to provide on some sides of the present utility model
The basic comprehension in face.It should be appreciated that this general introduction is not on exhaustive general introduction of the present utility model.It is not intended to really
Fixed crucial or pith of the present utility model, nor intended limitation scope of the present utility model.Its purpose is only with letter
The form of change provides some concepts, in this, as the preamble in greater detail discussed after a while.
In consideration of it, the utility model provides a kind of control circuit device based on DSP Yu FPGA, at least to solve at present
FPGA based on RAM needs to carry out again FPGA after each system electrification due to data disappear after SRAM power down
The problem of configuration.
According to one side of the present utility model, there is provided a kind of control circuit device based on DSP Yu FPGA, control electricity
Road device includes DSP unit, FPGA unit and resistance unit, and FPGA unit includes the first FPGA module, and resistance unit includes the
One resistance and second resistance；Wherein, I/O mouthfuls of DATA0 pin of the first FPGA module of connection of the 0th of DSP unit, DSP unit
The nSTATUS pins of the first I/O mouthfuls of the first FPGA module of connection, DSP unit the 2nd I/O mouthful connect first FPGA module
NCONFIG pins, DSP unit the 3rd I/O mouthfuls connection the first FPGA module CONF_DONE pins, the 4th I/ of DSP unit
The O mouthfuls of DCLK pin of the first FPGA module of connection；One end of first resistor and one end connection predetermined positive voltage of second resistance, the
The first I/O mouthful of the other end connection DSP unit of one resistance, the other end of second resistance connects the 3rd I/O mouthfuls of DSP unit；
The MSEL0 pins of the first FPGA module, MSEL1 pins and nCE pins ground connection.
Further, the nCE0 pins of the first FPGA module are vacant.
Further, FPGA unit also includes the second FPGA module；0th I/O mouthfuls of the 2nd FPGA mould of connection of DSP unit
The DATA0 pins of block, DSP unit the first I/O mouthfuls connection the second FPGA module nSTATUS pins, the 2nd I/ of DSP unit
O mouthfuls connection the second FPGA module nCONFIG pins, DSP unit the 3rd I/O mouthful connect the second FPGA module CONF_
DONE pins, DSP unit the 4th I/O mouthfuls connection the second FPGA module DCLK pins；The nCE0 pins of the first FPGA module
The nCE pins of the second FPGA module are connected, MSEL0 pins and the MSEL1 pins of the second FPGA module are grounded.
Further, DSP unit uses TMS320F28335 chips.
Control circuit device based on DSP and FPGA of the present utility model belongs to circuit-level bottom functional module, the control
Circuit arrangement provides hardware layer to deposit the target of the configuration data of FPGA using FLASH spaces idle in DSP subsystems
The practicable ways in face, it is right after thus not needing each system electrification in the case of using control circuit device of the present utility model
FPGA is reconfigured.By experimental verification, simulate special EPROM by DSP (such as TMS320F28335) is carried out to FPGA
Configuration, can reduce hardware cost and realize the online upgrading of FPGA.
By the detailed description below in conjunction with accompanying drawing to most preferred embodiment of the present utility model, it is of the present utility model these with
And other advantages will be apparent from.
Brief description of the drawings
The utility model can be better understood by reference to below in association with the description given by accompanying drawing, wherein
Same or analogous reference has been used in all of the figs to represent same or similar part.The accompanying drawing is together with
The detailed description in face is included in this manual and forms the part of this specification together, and for further illustrating
Bright preferred embodiment of the present utility model and explanation principle and advantage of the present utility model.In the accompanying drawings：
Fig. 1 is to schematically show an example based on DSP Yu the control circuit device of FPGA of the present utility model
Structural representation；
Fig. 2 shows a structural representation for example based on DSP Yu the control circuit device of FPGA of the present utility model
Figure；
Fig. 3 shows that the structure of another example of the control circuit device based on DSP and FPGA of the present utility model is shown
It is intended to.
It will be appreciated by those skilled in the art that element in accompanying drawing is just for the sake of showing for the sake of simple and clear,
And be not necessarily drawn to scale.For example, the size of some elements may be exaggerated relative to other elements in accompanying drawing, with
Just it is favorably improved the understanding to the utility model embodiment.
Specific embodiment
One exemplary embodiment of the present utility model is described hereinafter in connection with accompanying drawing.Rise for clarity and conciseness
See, all features of actual implementation method are not described in the description.It should be understood, however, that developing any this reality
Many decisions specific to implementation method must be made during embodiment, to realize the objectives of developer, example
Such as, those restrictive conditions related to system and business are met, and these restrictive conditions may be with implementation method not
Change together.Additionally, it also should be appreciated that, although development is likely to be extremely complex and time-consuming, but to having benefited from
For those skilled in the art of present disclosure, this development is only routine task.
Herein, in addition it is also necessary to which explanation is a bit, in order to avoid having obscured the utility model because of unnecessary details, attached
Be illustrate only in figure with according to the closely related apparatus structure of scheme of the present utility model and/or process step, and eliminated
The other details little with the utility model relation.
Embodiment of the present utility model provides a kind of control circuit device based on DSP Yu FPGA, control circuit device
Including DSP unit, FPGA unit and resistance unit, FPGA unit includes the first FPGA module, and resistance unit includes first resistor
And second resistance；Wherein, the I/O mouthfuls of DATA0 pin of the first FPGA module of connection of the 0th of DSP unit, an I/ of DSP unit
O mouthfuls connection the first FPGA module nSTATUS pins, DSP unit the 2nd I/O mouthful connect the first FPGA module nCONFIG
Pin, DSP unit the 3rd I/O mouthfuls connection the first FPGA module CONF_DONE pins, DSP unit the 4th I/O mouthful connect
The DCLK pins of the first FPGA module；One end of first resistor and one end connection predetermined positive voltage of second resistance, first resistor
The first I/O mouthful of other end connection DSP unit, the other end of second resistance connects the 3rd I/O mouthfuls of DSP unit；First
The MSEL0 pins of FPGA module, MSEL1 pins and nCE pins ground connection.
Fig. 1 shows the electrical schematic diagram based on DSP Yu the control circuit device of FPGA of the present utility model, and Fig. 2 shows
The structural representation of one example.
As shown in figure 1, in this example, the control circuit device 100 based on DSP and FPGA include DSP unit 110,
FPGA unit 120 and resistance unit.
DSP unit 110 is realized for example with TMS320F28335 chips.Hereinafter, mainly with TMS320F28335 chips
It is described as an example, it should be noted that, DSP unit is not limited to TMS320F28335 chips, it would however also be possible to employ can break even
The other types dsp chip of utility model scheme.
Wherein, FPGA unit 120 includes the first FPGA module 120-1, and resistance unit includes the electricity of first resistor R1 and second
Resistance R2.
0th I/O mouthfuls of GPIO0 of DSP unit 110 connects the DATA0 pins of the first FPGA module 120-1, DSP unit 110
I/O mouthfuls of GPIO1 connect the nSTATUS pins of the first FPGA module 120-1, the 2nd I/O mouthfuls of GPIO2 of DSP unit 110
The nCONFIG pins of the first FPGA module 120-1 are connected, the 3rd I/O mouthfuls of GPIO3 of DSP unit 110 connects the first FPGA module
The CONF_DONE pins of 120-1, the DCLK of the 4th I/O mouthfuls of the first FPGA module 120-1 of GPIO4 connections of DSP unit 110 is managed
Pin.
Thus, DSP unit 110 using 5 I/O pin (i.e. the 0th I/O mouthfuls of GPIO0, I/O mouthfuls of GPIO1, the 2nd I/O mouthfuls
GPIO2, the 3rd I/O mouthfuls of GPIO3 and the 4th I/O mouthfuls of GPIO4) it is connected with FPGA, it is achieved that the hard of passive series (PS) mode
Part is connected, and concrete signal is shown in Table 1 (sense is from terms of side).
Table 1
Additionally, as depicted in figs. 1 and 2, one end of first resistor R1 and one end of second resistance R2 connect predetermined positive voltage
(such as 3.3V), the other end of first resistor R1 connects an I/O mouthfuls of GPIO1 of DSP unit 110, the other end of second resistance R2
Connect the 3rd I/O mouthfuls of GPIO3 of DSP unit 110；The MSEL0 pins of the first FPGA module 120-1, MSEL1 pins and nCE pipe
Pin is grounded.
The nCE0 pins of the first FPGA module for example can be with vacant.
Fig. 3 shows that the structure of another example of the control circuit device based on DSP and FPGA of the present utility model is shown
It is intended to.
As shown in figure 3, FPGA unit 120 also includes the second FPGA module 120-2.
0th I/O mouthfuls of GPIO0 of DSP unit 110 connects the DATA0 pins of the second FPGA module 120-2, DSP unit 110
I/O mouthfuls of GPIO1 connect the nSTATUS pins of the second FPGA module 120-2, the 2nd I/O mouthfuls of GPIO2 of DSP unit 110
The nCONFIG pins of the second FPGA module 120-2 are connected, the 3rd I/O mouthfuls of GPIO3 of DSP unit 110 connects the second FPGA module
The CONF_DONE pins of 120-2, the DCLK of the 4th I/O mouthfuls of the second FPGA module 120-2 of GPIO4 connections of DSP unit 110 is managed
Pin.
Additionally, as shown in figure 3, the nCE0 pins of the first FPGA module 120-1 connect the nCE of the second FPGA module 120-2
Pin, MSEL0 pins and the MSEL1 pins of the second FPGA module 120-2 are grounded.
By above description, the control circuit device based on DSP and FPGA of the present utility model belongs to circuit-level bottom
Layer function module, the control circuit device is that the configuration data of FPGA is deposited using FLASH spaces idle in DSP subsystems
Target provides the practicable ways of hardware view.By experimental verification, simulated by DSP (such as TMS320F28335) special
EPROM is configured to FPGA, can be reduced hardware cost and be realized the online upgrading of FPGA.
Describe of the present utility model based on DSP's and FPGA as the example of DSP unit using TMS320F28335 below
One application example of control circuit device.
The characteristics of FPGA based on RAM is due to SRAM techniques, data can disappear after power down.Therefore, after each system electrification,
FPGA is configured by DSP.FPGA for Altera, the design is carried out using PS (passive series) modes to FPGA
Configuration, is based on consideration following aspects：PS mode lines are most simple；Can be with Configuration EPROM modes
It is compatible；Compared with parallel deployment, the probability of maloperation is small, and reliability is high.
For example, using the control circuit device based on DSP Yu FPGA of the present utility model, can be right as follows
The I/O mouth lines of TMS320F28335 are operated, to complete the follow-up configuration to FPGA：
1.nCONFIG=" 0 ", DCLK=" 0 ", keep more than 2 μ S.
2. nSTATUS is detected, if " 0 ", shows that FPGA has responded configuration requirement, configuration can be proceeded by.Otherwise report
It is wrong.Under normal circumstances, nSTATUS will be " 0 " to nCONFIG=" 0 " in 1 μ S afterwards.
3.nCONFIG=" 1 ", and wait 5 μ S.
Data (LSB first), DCLK=" 1 ", time delay are placed on 4.Data0.
5.DCLK=" 0 ", and nSTATUS is detected, if " 0 ", show that FPGA configurations are wrong, then should return to step 1 weight
Newly start.
6. prepare next bit data, and repeat step 4,5, untill all data are sent out.
7. now Conf_done strains into " 1 ", shows that the configuration of FPGA has been completed.After if all data are sent out,
Conf_done is not " 1 ", it is necessary to reconfigured (since step 1).
8. after the completion of configuring, then 10 DCLK in cycle are sent out, so that FPGA completes initialization.
Online upgrading
The online upgrading of veneer FPGA is can be achieved on using great advantage of the present utility model.
Hardware requirement
Online upgrading is realized, single board design must take into consideration following problem：
The startup of TMS320F28335 must not rely on FPGA, i.e. TMS320F28335 subsystems should be configured in FPGA
Before can independent operating and access needed for resource.
(or in configuration process) must assure that the equipment of control is in non-operation or does not influence other to set before FPGA configurations
The stable state of standby work.
In order to realize the online upgrading of FPGA, the memory device for depositing FPGA configuration data must be that TMS320F28335 can
Rewrite, and this memory should be non-volatile, after ensureing that veneer is powered off, FPGA data is not required to be regained from backstage.
Technical indicator
The configuration to FPGA is completed using TMS320F28335.
The design of this module completes checking under TMS320F28335 and FPGA environment, and the FPGA for Altera is fitted
With.
By taking TMS320F28335 mini systems as an example, the RBF files that we will can convert as binary file, directly
Connect the certain FLASH regions write and marked by dummy order in TMS320F28335.Due to the initial address and length of this segment data
Degree is all known, and corresponding software programming is very easily.
Additionally, after each system electrification, DSP can automatically call the configuration process of FPGA when initialization program is run,
On the premise of complete reliable communicating is set up, the configuration of FPGA is completed.
Cost is expected
Compared with Configuration EPROM modes, the design of this module eliminates the hard of Configuration EPROM
Part cost.Meanwhile, using existing resource, do not increase hardware cost.
Performance
The design of this module is carried out in strict accordance with the PS configuration flows of FPGA, and the monitoring shape all the time in configuration process
State, under sophisticated software cooperation, can correct as above electric order causes to configure the mistake such as abnormal.Therefore, using the method pair
FPGA is configured, and performance will be better than Configuration EPROM modes.
Feature
The design has the following advantages compared with Configuration EPROM modes：
1) reduce hardware cost --- eliminate the cost of FPGA special external memories, and hardly increase other into
This.At least to match somebody with somebody the EPC1 more than a piece of by taking the 10K series of ALTERA as an example, on plate, the batch valency of every EPC1 is more than 30 yuan,
Capacity 1M.The memory space of 1Mb is provided, is that need not increase hard for most of veneer (such as veneers of 860 systems)
Part.Even if increase 1Mb memory spaces, general-purpose storage also can EPROM more special than FPGA it is cheap.
If 2) can repeatedly program --- the use of special EPROM is nearly all OTP, FPGA versions are once change, legacy version
Not cheap EPROM can only abandon.If configured to FPGA using the design, preserved from erasable general-purpose storage
The programming data of FPGA, changes FPGA versions, without paying any hardware costs.This is also a side for reducing hardware cost
Face.
3) realize real " field-programmable " --- it is exactly " field-programmable " the characteristics of FPGA, only using DSP (such as
TMS320F28335 this feature) could be embodied to FPGA programmings.If design is thorough, the FPGA on veneer can accomplish
Online upgrading.
4) production process is reduced --- the operation to " the special EPROM of FPGA " sintering is eliminated, to improving productivity ratio, is reduced
Production cost etc. is beneficial to；Further, since the program of FPGA is stored in the FLASH regions of DSP, thus by DSP's itself
Cryptoguard, is difficult leakage.
Using the utility model, one can be marked in the FLASH of DSP by using the dummy order of DSP in subsequent treatment
Fixed region is used for depositing the program of FPGA；On function logic, using the multibus characteristic of DSP, patrolled according to strict sequential
In volume will be stored in the data write-in FPGA in this specific FLASH space.Ensure in system power failure, DSP can carried out
The program configuration to FPGA epicycles is completed during the program initialization of itself.Meanwhile, can be matched somebody with somebody using a piece of dsp chip in the design
Put multiple FPGA.FPGA power failure datas are lost before on the one hand the design solves the problems, such as, on the other hand eliminate the outer of FPGA
Subordinate carries the memory outside JATG interfaces and FPGA, saves veneer space, reduces system cost.
Although the embodiment according to limited quantity describes the utility model, above description, this technology are benefited from
It is in field it is clear for the skilled person that in the range of the utility model for thus describing, it can be envisaged that other embodiments.Additionally,
It should be noted that the language used in this specification primarily to readable and teaching purpose and select, rather than in order to
Explain or limit theme of the present utility model and select.Therefore, without departing from the scope of the appended claims and spirit
In the case of, many modifications and changes will be apparent from for those skilled in the art.For this
The scope of utility model, the disclosure done to the utility model is illustrative and not restrictive, scope of the present utility model
It is defined by the appended claims.
Claims (5)
1. the control circuit device of DSP and FPGA is based on, it is characterised in that the control circuit device includes DSP unit, FPGA
Unit and resistance unit, the FPGA unit include the first FPGA module, and the resistance unit includes first resistor and the second electricity
Resistance；
Wherein, I/O mouthfuls of DATA0 pin of connection first FPGA module of the 0th of the DSP unit, the DSP unit
The nSTATUS pins of the first I/O mouthfuls of connection first FPGA module, the DSP unit the 2nd I/O mouthful connect described first
The nCONFIG pins of FPGA module, the CONF_DONE of the 3rd I/O mouthfuls of connection first FPGA module of the DSP unit is managed
Pin, the DCLK pins of the 4th I/O mouthfuls of connection first FPGA module of the DSP unit；
One end connection predetermined positive voltage of one end of the first resistor and the second resistance, the other end of the first resistor
Connect an I/O mouthfuls of the DSP unit, the other end of the second resistance connects the 3rd I/O mouthfuls of the DSP unit；
The MSEL0 pins of first FPGA module, MSEL1 pins and nCE pins ground connection.
2. the control circuit device based on DSP Yu FPGA according to claim 1 a, it is characterised in that FPGA
The nCE0 pins of module are vacant.
3. the control circuit device based on DSP Yu FPGA according to claim 1, it is characterised in that the FPGA unit
Also include the second FPGA module；
The DATA0 pins of the 0th I/O mouthfuls of connection second FPGA module of the DSP unit, an I/ of the DSP unit
The O mouthfuls of nSTATUS pin of connection second FPGA module, the 2nd I/O mouthfuls of connection the 2nd FPGA mould of the DSP unit
The nCONFIG pins of block, the CONF_DONE pins of the 3rd I/O mouthfuls of connection second FPGA module of the DSP unit, institute
State the DCLK pins of the 4th I/O mouthfuls of connection second FPGA module of DSP unit；
The nCE0 pins of first FPGA module connect the nCE pins of second FPGA module, second FPGA module
MSEL0 pins and MSEL1 pins be grounded.
4. the control circuit device based on DSP Yu FPGA according to claim 1, it is characterised in that the DSP unit is adopted
Use TMS320F28335 chips.
5. the control circuit device based on DSP Yu FPGA according to claim 1, it is characterised in that the predetermined positive electricity
It is 3.3V to press, and the resistance of the first resistor and the second resistance is 1K ohm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621342754.6U CN206209364U (en) | 2016-12-08 | 2016-12-08 | Control circuit device based on DSP Yu FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621342754.6U CN206209364U (en) | 2016-12-08 | 2016-12-08 | Control circuit device based on DSP Yu FPGA |
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| Publication Number | Publication Date |
|---|---|
| CN206209364U true CN206209364U (en) | 2017-05-31 |
Family
ID=58746392
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621342754.6U Expired - Fee Related CN206209364U (en) | 2016-12-08 | 2016-12-08 | Control circuit device based on DSP Yu FPGA |
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| CN (1) | CN206209364U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106951216A (en) * | 2017-05-05 | 2017-07-14 | 郑州云海信息技术有限公司 | A kind of FPGA configuration method and online upgrading method |
| CN113050952A (en) * | 2021-04-19 | 2021-06-29 | 杭州至千哩科技有限公司 | Pseudo instruction compiling method and device, computer equipment and storage medium |
-
2016
- 2016-12-08 CN CN201621342754.6U patent/CN206209364U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106951216A (en) * | 2017-05-05 | 2017-07-14 | 郑州云海信息技术有限公司 | A kind of FPGA configuration method and online upgrading method |
| CN113050952A (en) * | 2021-04-19 | 2021-06-29 | 杭州至千哩科技有限公司 | Pseudo instruction compiling method and device, computer equipment and storage medium |
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