CN106951216A - A kind of FPGA configuration method and online upgrading method - Google Patents
A kind of FPGA configuration method and online upgrading method Download PDFInfo
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- CN106951216A CN106951216A CN201710312862.1A CN201710312862A CN106951216A CN 106951216 A CN106951216 A CN 106951216A CN 201710312862 A CN201710312862 A CN 201710312862A CN 106951216 A CN106951216 A CN 106951216A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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Abstract
The present invention provides a kind of FPGA configurations and online upgrading method, the present invention is configured using passive series mode to FPGA, FPGA configuration data is deposited using ROM Space idle in existing cpu subsystem on plate, and special EPROM is simulated by CPU FPGA is configured, to reduce hardware cost and realize FPGA online upgrading.
Description
Technical field
The present invention relates to computer realm, and in particular to a kind of FPGA configurations and online upgrading method.
Background technology
Many products have all used FPGA extensively at present, although kind is different, but programming mode is nearly all：Using special
EPROM FPGA is configured.Special EPROM prices are not cheap, and it is all that disposable OPT modes are programmed very much not to keep up with.
Once changing FPGA design, cost is not small.
The content of the invention
In order to solve the above technical problems, technical scheme is as follows：
In a first aspect, the present invention provides a kind of method that use passive series mode is configured to FPGA, including it is following
Step：
SS1：NCONFIG=" 0 ", DCLK=" 0 " are set, more than 2 μ S are kept；
SS2：NSTATUS is detected, if " 0 ", shows that FPGA has responded configuration requirement, configuration can be proceeded by, otherwise
Report an error；
SS3：NCONFIG=" 1 " is set, and waits 5 μ S；
SS4：Data are placed on Data0, DCLK=" 1 ", delay are set；
SS5：DCLK=" 0 " is set, and detects nSTATUS, if " 0 ", then report an error and restart；
SS6：Prepare next bit data, and repeat step SS 4, SS 5, untill all data are sent out；
SS7：Whether detection Conf_done becomes " 1 ", if so, showing that FPGA configuration has been completed, if all data are sent
After going out, Conf_done is not " 1 ", it is necessary to reconfigured since SS 1；
SS8：After the completion of configuration, then the DCLK in 10 cycles is sent out, so that FPGA completes initialization.
Further, nSTATUS will be " 0 " in 1 μ S after nCONFIG=" 0 ".
Further, FPGA is Altera FPGA.
Further, CPU is made using MPC860, BootROM uses SST39VF040, FPGA models EP1K30.
Further, the DCLK that FPGA completes 10 cycles required for initialization in step SS8 be for ACEX 1K and
FLEX 10KE's, if APEX 20K, then need 40 cycles.
Further, in configuration process, if detecting nSTATUS for " 0 ", show that FPGA configurations are wrong, then should
Step SS1 is returned to restart.
Second aspect, a kind of method that the present invention provides online upgrading to FPGA, step includes：
SS1：Using compiling and fastening means, the working procedure of FPGA first version and CPU is linked together, point
Not Zhan Yong address be 0x70000-0x7FFFF and 0x00000-0x6FFFF memory space；；
SS 2：During single board starting, CPU automatically downloads to 0x70000-0x7FFFF data in FPGA, completes FPGA and matches somebody with somebody
Put；
SS 3：When FPGA need to upgrade, new RBF configuration files are placed in background computer；
SS 4：CPU BOOTROM 0x70000-0x7FFFF spaces as general data memory block, will be new by backstage
RBF configuration files be placed in 0x70000-0x7FFFF；
SS 5：CPU calls the FPGA in BOOTROM to configure subprogram, and data are re-downloaded to FPGA, FPGA liters are completed
Level.
Further, CPU is made using MPC860, BootROM uses SST39VF040, FPGA model EP1K30,
MCP860 PB mouths select 5 lines to connect into PS configuration modes with EP1K30, and Data0 is also exported by MPC860.
Further, the region of storage FPGA configuration data must be that CPU is rewritable.
Further, if some board B ootROM function of writing must refrain from, now FPGA configuration data can be placed on it
In its memory, in such as FLASH of storage application program, upgrading FPGA configuration data can be complete in the lump with upgrade applications
Into.
Compared with Configuration EPROM modes originally, the solution of the present invention has reduction hardware cost, can repeatedly compiled
The advantages of journey, realization real " field-programmable ", reduction production process.
Brief description of the drawings
Fig. 1 shows the timing diagram that Configuration EPROM modes are configured to FPGA.
Fig. 2 shows PS configuration monolithics FPGA of the present invention hardware connection figure
Fig. 3 shows that PS of the present invention configures the hardware connection figure of multiple FPGA.
Fig. 4 shows the timing diagram that the present invention is configured using PS modes to FPGA.
Fig. 5 shows that the present invention carries out configuration operating process block diagram to FPGA using PS modes.
Fig. 6 shows system architecture diagram of the present invention to FPGA online upgrading
Fig. 7 shows circuit system schematic diagram of the present invention to FPGA online upgrading.
Embodiment
Technical scheme is further illustrated below in conjunction with Figure of description and specific embodiment.It should be appreciated that this
The specific embodiment of place description is not intended to limit the present invention only to explain the present invention.
The inventive concept of the present invention is matching somebody with somebody using ROM Space storage FPGA idle in existing cpu subsystem on plate
Data are put, and special EPROM is simulated by CPU FPGA is configured, to reduce hardware cost and realize FPGA online upgrading.
The characteristics of RAM-Based FPGA are due to SRAM techniques, data can disappear after power down.Therefore, each system electrification
Afterwards, it is both needed to configure FPGA.For Altera FPGA, collocation method can be divided into：Special EPROM
(Configuration EPROM), PS (Passive serial passive series), PPS (Passive parallel
Synchronous is passive simultaneously and concurrently), PPA (the passive asynchronous parallels of Passive parallel asynchronous), JTAG
(not all device is all supported).
Fig. 1 is the timing diagram that Configuration EPROM modes are configured to FPGA.
The present invention is configured using PS modes to FPGA, is mainly based upon consideration following aspects：
1.PS mode lines are most simple；
2. can be compatible (MSEL0,1 set constant) with Configuration EPROM modes；
3. compared with parallel deployment, the probability of maloperation is small, reliability is high.
The system construction drawing that Fig. 2-3 present invention is configured using PS modes to FPGA.
Fig. 2 shows PS configuration monolithics FPGA hardware connection, and Fig. 3 shows the hardware connection of PS configuration multiple FPGAs.
The timing diagram that Fig. 4 is configured for the present invention using PS modes to FPGA.
Fig. 5 carries out configuration operating process block diagram to FPGA for the present invention using PS modes.
As shown in figure 3, show the method flow configured to FPGA using PS modes, CPU step operations in this way
I/O mouth lines, you can complete the configuration to FPGA, method and step is as follows：
SS1：NCONFIG=" 0 ", DCLK=" 0 ", keep more than 2 μ S.
SS2：NSTATUS is detected, if " 0 ", shows that FPGA has responded configuration requirement, configuration can be proceeded by.Otherwise
Report an error.Under normal circumstances, nSTATUS will be " 0 " in 1 μ S after nCONFIG=" 0 ".
SS3：NCONFIG=" 1 ", and wait 5 μ S.
SS4：Data (LSB first), DCLK=" 1 ", delay are placed on Data0.
SS5：DCLK=" 0 ", and nSTATUS is detected, if " 0 ", then report an error and restart.
SS6：Prepare next bit data, and repeat step SS 4, SS 5, untill all data are sent out.
SS7：Now Conf_done strains into " 1 ", shows that FPGA configuration has been completed.After if all data are sent out,
Conf_done is not " 1 ", it is necessary to reconfigured since SS 1.
SS8：After the completion of configuration, then the DCLK in 10 cycles is sent out, so that FPGA completes initialization.
According to one embodiment of the invention, FPGA is Altera FPGA.
According to one embodiment of the invention, the DCLK that FPGA completes 10 cycles required for initialization in step SS8 is
For ACEX 1K and FLEX 10KE, if APEX 20K, then 40 cycles are needed.
According to one embodiment of the invention, in configuration process, if detecting nSTATUS for " 0 ", show that FPGA is configured
It is wrong, then it should return to step SS1 and restart.
Fig. 6-7 is system architecture diagram and circuit theory diagrams of the present invention to FPGA online upgrading.
As shown in fig. 6, showing the system to FPGA online upgradings.
According to one embodiment of the invention, CPU is made using MPC860, BootROM uses SST39VF040, a piece of FPGA types
Number EP1K30QC208-3.We select 5 lines and EP1K30 to connect into PS configuration modes in MCP860 PB mouths, Data0 also by
MPC860 is exported, and signal definition see the table below：
| MPC860 pins | I/O | Signal name | EP1K30 pins |
| PB24 | O | DATA0 | 156 |
| PB25 | I | nSTATUS | 52 |
| PB26 | O | nCONFIG | 105 |
| PB27 | I | CONF_DONE | 2 |
| PB28 | O | DCLK | 155 |
Configuration data required for EP1K30 is 58kB the RBF files of generation (accurate length referring to), due to BootROM
Compare empty, 0x70000~0x7FFFF that configuration data is arranged in BootROM by us is interval interior.The configuration data of first time can
The region for being 0x70000 by the initial address that RBF files write BootROM as binary file using programmable device, can also
Specified location is write data to by 860 emulators.
According to one embodiment of the invention, the region of storage FPGA configuration data must be that CPU is rewritable.
According to one embodiment of the invention, such as some board B ootROM function of writing must refrain from, and now FPGA configures number
According to that can be placed in other memories, in such as FLASH of storage application program, upgrading FPGA configuration data can be with upgrade application journey
Sequence is completed in the lump.
Method to FPGA online upgrading comprises the following steps：
SS1：Using compiling and fastening means, the working procedure of FPGA first version and MPC860 is connected to one
Rise, the memory space that address is 0x70000-0x7FFFF and 0x00000-0x6FFFF is taken respectively.
SS 2：During single board starting, MPC860 automatically downloads to 0x70000-0x7FFFF data in FPGA, completes
FPGA is configured.
SS 3：When FPGA need to upgrade, new RBF configuration files are placed in background computer.
SS 4：BOOTROM 0x70000-0x7FFFF spaces as general data memory block, are passed through backstage by MPC860
New RBF configuration files are placed in 0x70000-0x7FFFF.
SS 5：MPC860 calls the FPGA in BOOTROM to configure subprogram, and data are re-downloaded to FPGA, FPGA is completed
Upgrading.
By taking MPC860 as an example, MPC860 systems can be written directly to using the RBF files converted as binary file
A certain ROM/Flash regions.Because the initial address and length of this segment data are all known, corresponding software programming is very
Easily.
The CPU source programs of the present invention are as follows：
void InitPORT(void)
{ PB mouthfuls of corresponding positions of // initialization：
//PB24- is exported, PB25- inputs, PB26- outputs, PB27- inputs, PB28- outputs
IMMR->Pip_pbpar=0x00000000；
IMMR->Pip_pbdir=0xFFFFF5AF；
IMMR->Pip_pbodr=0x00000000；
IMMR->Pip_pbdat=0xffffff57；
}
UBYTE Fpga_DownLoad(void)
{ //FPGA is configured
UBYTE*Bootaddr；
UWORD CountNum=0x0；
UBYTE FpgaBuffer,i；
// obtain Boot areas first address
Bootaddr=(UBYTE*) (IMMR->memc_or0&IMMR->memc_br0&0xFFFF8000)；
Set_nCONFIG(0)；//nCONFIG=" 0 ", makes FPGA enter configuration status
Set_DCLK(0)；
DELAY5us()；
If (Read_nSTATUS ()==1)
{ // detection nSTATUS, if " 0 ", shows that FPGA has responded configuration requirement, can proceed by configuration.Otherwise report
It is wrong
Err_LED(1)；
return 0；
}
Set_nCONFIG(1)；
DELAY5us()；
// start output configuration：
while(CountNum<=0x0e74e)
{
FpgaBuffer=* (Bootaddr+0x70000+CountNum)；
For (i=0；i<8；i++)
During { //DCLK=" 0 ", data (LSB first) are placed on Data0
Set_Data0(FpgaBuffer&0x01)；
Set_DCLK(1)；//DCLK->" 1 ", makes FPGA read in data
FpgaBuffer>>=1；// prepare next bit data
If (Read_nSTATUS ()==0)
{ // detection nSTATUS, if " 0 ", shows FPGA configuration errors
Err_LED(1)；
return 0；
}
Set_DCLK(0)；
}
CountNum++；
}
//FPGA is initialized：
//ACEX 1K and FLEX 10KE need 10 cycles, and APEX 20K need 40 cycles
For (i=0；i<10；i++)
{
Set_DCLK(1)；
DELAY100us()；
Set_DCLK(0)；
DELAY100us()；
}
Set_Data0(0)；
If (Read_nCONF_Done ()==0)
{ // detection nCONF_Done, if " 0 ", shows that FPGA configurations are failed
Err_LED(1)；
return 0；
}
return 1；// successfully return
}
//Data0 is exported
void Set_Data0(UBYTE setting)
{//PB24
if(setting)IMMR->Pip_pbdat |=0x00000080；
else IMMR->Pio_pbdat＆=0xFFFFFF7F；
}
// read nSTATUS states
UBYTE Read_nSTATUS(void)
{//PB25
if(IMMR->pio_pbdat&0x00000040)return 1；
else return 0；
}
// nCONFIG level is set
void Set_nCONFIG(UBYTE setting)
{//PB26
if(setting)IMMR->Pip_pbdat |=0x00000020；
else IMMR->Pio_pbdat＆=0xFFFFFFDF；
}
// read nCONF_Done states
UBYTE Read_nCONF_Done(void)
{//PB27
if(IMMR->pio_pbdat&0x00000010)return 1；
else return 0；
}
// output DCLK
void Set_DCLK(UBYTE setting)
{//PB28
if(setting)IMMR->Pio_pbdat |=0x00000008；
else IMMR->Pio_pbdat＆=0xFFFFFFF7；
}
// terminate
The present invention is carried out in strict accordance with FPGA PS configuration flows, and the monitoring state all the time in configuration process,
Under sophisticated software coordinates, can correct as above electric order causes to configure the mistake such as abnormal.Therefore, FPGA is entered using the method
Row configuration, performance will be better than Configuration EPROM modes.The design compared with Configuration EPROM modes
Have the following advantages：
1. reduce hardware cost：The special EPROM of FPGA cost is eliminated, and hardly increases other costs.With
Exemplified by ALTERA 10K series, at least dozens of yuan, capacity 1M are wanted with a piece of EPC1 above, every EPC1 price on plate
Position.1Mb memory space is provided, for most of veneer (such as veneers of 860 systems), hardware need not be increased.
Even if increase 1Mb memory spaces, general-purpose storage also can EPROM more special than FPGA it is cheap.
2. can repeatedly it program：The special EPROM of FPGA are nearly all OTP, once FPGA versions are changed, it is legacy version and inconvenient
Suitable EPROM can only be abandoned.If configured using the design to FPGA, FPGA volume is preserved from erasable general-purpose storage
Number of passes evidence, changes FPGA versions, without paying any hardware costs.This is also to reduce the one side of hardware cost.
3. realize real " field-programmable "：The characteristics of FPGA is exactly " field-programmable ", and only FPGA is compiled using CPU
Cheng Caineng embodies this feature.If design is thorough, the FPGA on veneer can accomplish online upgrading.
4. reduce production process：The process sintered to " the special EPROM of FPGA " is eliminated, to improving productivity ratio, reduction life
Cost etc. is produced to be beneficial to.For the veneer of two-sided reflow welding, the process that can more save manual repair welding DIP devices.
Although in terms of having been described for some in the context of device, it is apparent that these aspects also illustrate that corresponding method
Description, wherein block or apparatus and method for step or the feature of method and step be corresponding.Similarly, in the context of method and step
Described in each side also illustrate that the description of corresponding piece or project or the feature of corresponding intrument.(or use) can be passed through
Hardware unit such as microprocessor, programmable calculator or electronic circuit etc is some or all of in method and step to perform.
Can be performed by such device in most important method and step some or it is multiple.
The realization can using hardware or using software or can use for example floppy disk, DVD, blue light, CD, ROM,
PROM, EPROM, EEPROM or flash memory etc the stored digital for being stored in electronically readable control signal thereon that has are situated between
Matter is performed, and the electronically readable control signal coordinates (or with it can coordinate) to perform with programmable computer system
Corresponding method.The data medium with electronically readable control signal can be provided, the electronically readable control signal can be with
Programmable computer system coordinates to perform approach described herein.
The realization can also use the form of the computer program product with program code, work as computer program product
When running on computers, program code is operated to perform this method.Can in machine-readable carrier storage program generation
Code.
Described above be only it is illustrative, and it is to be understood that it is described herein arrangement and details modification and
Change will be apparent to those skilled in the art.It is therefore intended that only by scope of the following claims rather than by
The specific detail that is presented is limited above description and by way of explaining.
Claims (10)
1. a kind of method that use passive series mode is configured to FPGA, it is characterised in that comprise the following steps：
SS1：NCONFIG=" 0 ", DCLK=" 0 " are set, more than 2 μ S are kept；
SS2：NSTATUS is detected, if " 0 ", shows that FPGA has responded configuration requirement, configuration can be proceeded by, otherwise reported an error；
SS3：NCONFIG=" 1 " is set, and waits 5 μ S；
SS4：Data are placed on Data0, DCLK=" 1 ", delay are set；
SS5：DCLK=" 0 " is set, and detects nSTATUS, if " 0 ", then report an error and restart；
SS6：Prepare next bit data, and repeat step SS4, SS5, untill all data are sent out；
SS7：Whether detection Conf_done becomes " 1 ", if so, showing that FPGA configuration has been completed, if all data are sent out
Afterwards, Conf_done is not " 1 ", it is necessary to reconfigured since SS1；
SS8：After the completion of configuration, then the DCLK in 10 cycles is sent out, so that FPGA completes initialization.
2. the method that use passive series mode according to claim 1 is configured to FPGA, it is characterised in that
NSTATUS will be " 0 " in 1 μ S after nCONFIG=" 0 ".
3. the method that use passive series mode according to claim 2 is configured to FPGA, it is characterised in that FPGA
For Altera FPGA.
4. the method that use passive series mode according to claim 2 is configured to FPGA, it is characterised in that use
MPC860 makees CPU, and BootROM uses SST39VF040, FPGA models EP1K30.
5. the method that use passive series mode according to claim 4 is configured to FPGA, it is characterised in that step
In SS8 FPGA complete initialization required for 10 cycles DCLK for ACEX 1K and FLEX 10KE, if
APEX 20K, then need 40 cycles.
6. the method that use passive series mode according to claim 1 is configured to FPGA, it is characterised in that with
During putting, if detecting nSTATUS for " 0 ", show that FPGA configurations are wrong, then should return to step SS1 and restart.
7. a kind of method of online upgrading to FPGA, it is characterised in that step includes：
SS1：Using compiling and fastening means, the working procedure of FPGA first version and CPU is linked together, accounted for respectively
It is 0x70000-0x7FFFF and 0x00000-0x6FFFF memory space with address；
SS2：During single board starting, CPU automatically downloads to 0x70000-0x7FFFF data in FPGA, completes FPGA configurations；
SS3：When FPGA need to upgrade, new RBF configuration files are placed in background computer；
SS4：CPU BOOTROM 0x70000-0x7FFFF spaces as general data memory block, by backstage by new RBF
Configuration file is placed in 0x70000-0x7FFFF；
SS5：CPU calls the FPGA in BOOTROM to configure subprogram, and data are re-downloaded to FPGA, completes FPGA upgradings.
8. the method for the online upgrading according to claim 7 to FPGA, it is characterised in that make CPU using MPC860,
BootROM uses SST39VF040, FPGA model EP1K30, selects 5 lines to connect into PS with EP1K30 in MCP860 PB mouths and matches somebody with somebody
Mode is put, Data0 is also exported by MPC860.
9. the method for the online upgrading according to claim 7 to FPGA, it is characterised in that storage FPGA configuration data
Region must be that CPU is rewritable.
10. the method for the online upgrading according to claim 8 to FPGA, it is characterised in that if some veneers
BootROM function of writing be must refrain from, and now FPGA configuration data can be placed in other memories, such as storage application program
In FLASH, upgrading FPGA configuration data can in the lump be completed with upgrade applications.
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| CN206209364U (en) * | 2016-12-08 | 2017-05-31 | 哈尔滨理工大学 | Control circuit device based on DSP Yu FPGA |
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2017
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| US20050114473A1 (en) * | 2003-10-30 | 2005-05-26 | Ravid Guy | FPGA boot-up over a network |
| CN101165652A (en) * | 2006-10-18 | 2008-04-23 | 中兴通讯股份有限公司 | Method for simultaneously loading multiple FPGA using CPU |
| CN201000625Y (en) * | 2006-12-08 | 2008-01-02 | 上海欣泰通信技术有限公司 | Field programmable gate array online configuration device |
| CN206209364U (en) * | 2016-12-08 | 2017-05-31 | 哈尔滨理工大学 | Control circuit device based on DSP Yu FPGA |
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