CN109525276B

CN109525276B - Multimode data link system and method with external downloading function

Info

Publication number: CN109525276B
Application number: CN201811279467.9A
Authority: CN
Inventors: 杜鹏渊; 李晓曦; 张焱; 肖长春; 王静雨
Original assignee: Space Star Technology Co Ltd
Current assignee: Space Star Technology Co Ltd
Priority date: 2018-10-30
Filing date: 2018-10-30
Publication date: 2020-11-20
Anticipated expiration: 2038-10-30
Also published as: CN109525276A

Abstract

A multimode data link system and method with external download function, including FPGA, MCU master control module, first FLASH module, second FLASH module, gate, receive and dispatch the link module, interface module, power module and clock module; the FPGA completes main data processing and configuration functions of each module, the MCU master control module receives a control instruction from the interface module and completes work mode selection by matching with the FLASH, the interface module also provides a data channel for external downloading, the transceiving link module realizes data conversion and transmission, the power supply module supplies power for the system, and the clock module provides a clock signal for the FPGA. The invention can be used for FPGA multi-loading hardware architecture of a miniaturized multi-mode data link terminal, can load configuration programs of different working modes according to specific use requirements to complete multi-mode selection, has an external downloading function, and can carry out program upgrading or replacement.

Description

Multimode data link system and method with external downloading function

Technical Field

The invention belongs to the technical field of software radio and communication anti-interference, and relates to a multimode selection system which is applied to FPGA multimode loading of a data link terminal with the requirements of miniaturization, high performance, high integration, high reliability and multimode communication use and has an external downloading function.

Background

Miniaturization and high integration are important trends in the development of weapon datalink end machines. Along with the development of device technology and the progress of design means, the working speed of a signal processing and communication circuit is higher and higher, the power is higher and higher, the noise distribution is more and more complex and strong, and meanwhile, along with the continuous improvement of the integration level of a high-speed high-frequency chip, the appearance and the weight are smaller and smaller. The rapid development and rapid upgrade of new large-scale integrated circuits, SOC (system on chip), SIP (system on package) devices, and digital-analog hybrid system chips make the current circuit system interconnection design face severe reliability and stability challenges. The increasing requirements on data processing and the increasing requirements on complex functions bring about the increase of the occupation amount of the space of a configuration program and the occupation amount of FPGA resources, and the complex functions and the cooperation of multiple working modes put higher requirements on FPGA (programmable logic gate array) resources and heat consumption. The contradiction between miniaturization and high integration degree is bound to high power consumption, and an important design technology is how to unify miniaturization and low power consumption when the multimode work is switched.

The program replacement of the FPGA is currently used in the field of aerospace to deal with the single event upset effect caused by space radiation, and an FPGA program online refreshing technology is often used. The technology generally uses a framework of CPU + ARM + FPGA or CPU + CPLD + FPGA, the CPU completes instruction receiving and control instruction sending, the ARM or CPLD completes on-line writing of a program, and the FPGA reconfigures after the FPGA completes program receiving, so as to complete on-line refreshing of the FPGA program. The technology faces to the single event effect generated by space radiation, the level of a memory chip is partially overturned, and the product is influenced by excessive accumulation of erroneously overturned levels, so that the program needs to be refreshed in real time.

However, in the general civil field, the situation can not be met, and the three-core architecture for completing the online refreshing is more complicated than the general use situation, so that the contradiction between miniaturization and low power consumption is still outstanding. The configuration program of the FPGA is separated from the nonvolatile memory device, and the online writing process of the FPGA has a risk, and measures taken to avoid the risk increase the product cost. In the process of writing programs into the FPGA, in order to match the speeds on two sides, the technology usually needs the ARM or the CPLD to store the configuration programs into a local cache, and the configuration programs are sent into the FPGA after being matched, so that the configuration efficiency is reduced.

In some applications, the device operating time is short, long-term boot service is not required, and an online refresh function is not required.

In some applications, the product is often stored for many years before being used, and sometimes the program is upgraded, so that the external downloading function in the complete machine state is required, and the configuration program of each module can be updated rapidly without being disassembled.

Disclosure of Invention

The invention aims to: the system and the method overcome the defects of the prior art, provide the multimode data link system with the external download function, solve the contradiction between overlarge FPGA resource occupancy rate, overhigh power consumption and product miniaturization of a data link terminal under the requirement of multiple communication modes, have a simple and reliable communication mode selection method, have the external download capability and can be upgraded on line.

The technical scheme adopted by the invention is as follows:

a multimode data link system with external download functionality, comprising: the system comprises an FPGA, an MCU main control module, a first FLASH module, a second FLASH module, a gate, a transceiving link module and an interface module;

the MCU main control module receives a control instruction input from the outside through the interface module and controls the gate to work, so that a chip selection signal generated by the FPGA is sent to the first FLASH module through the gate or sent to the second FLASH module through the gate; the FPGA carries out relevant configuration on the FPGA and the receiving and transmitting link module according to preset configuration programs corresponding to different communication modes read from the first FLASH module or the second FLASH module, and then receives and processes information of an external input data chain through the receiving and transmitting link module or sends the information to the external data chain through the receiving and transmitting link module;

the FPGA downloads an external configuration program on line through the interface module and carries out data processing, the processed configuration program is written into the first FLASH module or the second FLASH module, and the preset configuration program in the first FLASH module or the second FLASH module is updated.

The updating of the preset configuration program in the first FLASH module or the second FLASH module refers to upgrading the preset configuration program or replacing the preset configuration program with a new configuration program corresponding to other communication modes.

The FPGA comprises a download checking module, a cache module, a secondary checking module, a writing module and a reading module;

the FPGA checks the external configuration program downloaded online through the interface module through the download checking module, the external configuration program is stored in the cache module after the checking is successful, the downloaded external configuration program is written into the first FLASH module or the second FLASH module through the writing module, the written content is read through the reading module after the writing, and the checking is carried out through the secondary checking module, so that the written configuration program is ensured to be correct.

And an external configuration program which is downloaded on line by the FPGA through the interface module is transmitted into the download checking module through the RapidIO interface and carries out data processing.

The receiving and transmitting link module comprises an antenna link communication module, a Beidou communication module, a ground communication module, a standby communication module and a data processing module;

the antenna chain communication module is used for carrying out data interaction between the FPGA and an external data chain through the antenna chain communication module when the communication is in an antenna chain communication mode;

the Beidou communication module is used for carrying out data interaction with an external data chain through the FPGA when the communication is in a Beidou communication mode;

the standby communication module is used for carrying out data interaction with an external data link through the standby communication module when the communication is in other communication modes except the skink and the Beidou;

the ground communication module is used for communication between the FPGA and a ground station;

the data processing module is used for sequentially carrying out filtering, amplification and analog/digital conversion on data received by the FPAG (field programmable gate array) when the FPGA is communicated with an external data chain or a ground station, and sequentially carrying out digital/analog conversion, amplification and filtering on data sent by the FPGA.

Configuration programs corresponding to the antenna chain communication mode and the Beidou communication mode are respectively prestored in the first FLASH module or the second FLASH module, and the configuration programs corresponding to other communication modes are realized in an FPGA (field programmable gate array) online downloading mode.

When the working mode is changed, the MCU sends a control instruction to control the switching of the gate, so that the FPGA switches and reads the configuration program in the first FLASH module or the second FLASH module, thereby realizing the switching of the working mode.

And the interface module receives an external control instruction through the CAN bus to further complete the selection of the working mode, and reports the monitoring state through the IIC bus.

The FPGA power supply module is used for supplying power to other modules, and the clock module provides working clock signals for the FPGA.

A data transmission method realized based on the multimode data link system with the external download function comprises the following steps:

(1) the interface module receives an external control instruction through a CAN bus;

(2) the MCU master control module receives an externally input control instruction through the interface module and controls the gate to work;

(3) the chip selection signal generated by the FPGA is sent to the first FLASH module through the gate or sent to the second FLASH module through the gate;

(4) the FPGA reads preset configuration programs corresponding to different communication modes and stored in the first FLASH module or the second FLASH module;

(5) the FPGA configures the FPGA and the transceiving link module according to the read preset configuration programs corresponding to different communication modes;

(6) the FPGA receives and processes the information of the external input data chain through the transceiving link module or sends the information to the external data chain through the transceiving link module;

(7) judging whether a communication mode needs to be switched, if the communication mode needs to be switched, retransmitting a control instruction by the MCU main control module, enabling the gate to work, and switching the FLASH communicated with the FPGA; if the communication mode needing to be switched is not in the preset configuration program range in the first FLASH module and the second FLASH module, entering the step (8);

(8) the FPGA downloads an external configuration program on line through the interface module and carries out data processing, the processed configuration program is written into the first FLASH module or the second FLASH module, and the preset configuration program in the first FLASH module or the second FLASH module is updated.

Compared with the prior art, the invention can realize the following beneficial effects:

1) for FPGA application with high data processing capacity requirements and large FPGA programs under the requirements of various communication modes, the common performance FPGA resource occupancy rate can reach more than 90%, and when the FPGA resource occupancy rate is critical, the system can have the problem of unstable functions. The system is designed according to the use requirements, the occupation amount of FPGA resources can be reasonably distributed according to the configuration programs of the functional differentiation, the occupation rate of the FPGA resources can be effectively reduced, and the system has higher reliability;

2) when multiple communication modes are simultaneously started, the occupation rate of FPGA resources is large, the occupation rate of common FPGA resources with common performance can reach more than 90%, and further the power consumption of the FPGA under full-force work is large, meanwhile, the peripheral transceiving link modules also work at the same time, and even if part of components can be in standby use, extra power consumption can be generated. When the system is designed according to the use requirements, the FPGA program is effectively decomposed in a certain communication mode, the power consumption of the FPGA is reduced, the working mode of the transceiving link module is confirmed, and the power consumption of the transceiving link module is optimized, so that the power consumption of the whole data link terminal is reduced;

3) compared with an FPGA (field programmable gate array) online refreshing technology, the invention has the advantages of simple hardware architecture, simple and reliable use process and high configuration efficiency, and provides a more direct and reliable multimode selection mode under the conditions of one-time use and short working time (partial weapon application);

4) the system has a quick external downloading function, can realize quick program upgrade in the state of the whole machine through a loaded program of the FPGA, can cope with all supportable working modes by matching with a double-FLASH structure, can be directly written into FLASH when a verified new working mode occurs, and has backup FLASH for emergency processing when erasing and writing have problems. The RapidIO interface adopted by external downloading is a high-speed interface, the speed of transmitting the configuration program is high, and in the verification of an actual product, the program upgrading is carried out by adopting an external downloading mode, and the speed is higher than that of directly connecting an upper computer to carry out program upgrading by returning a cover to a factory and using the most common JTAG interface.

In conclusion, the invention can meet the use requirements of miniaturization, high performance, high integration, high reliability and multi-mode communication, effectively avoids the problems of large occupied space of a configuration program and high occupancy rate of FPGA resources caused by the high performance and the multi-mode communication, can carry out non-cover-dismounting upgrading through an external downloading function in a work mode which can be supported by hardware, and has higher upgrading speed and protective measures.

Drawings

FIG. 1 is a schematic diagram of the present invention.

Detailed Description

The invention provides a FPGA multi-loading hardware framework applied to a miniaturized multi-mode data chain terminal, aiming at the problems of large occupied space of a configuration program, insufficient FPGA resource quantity, large power consumption and the like caused by high requirements under the requirements of miniaturization, high performance, high integration degree, high reliability and multi-mode communication of the data chain terminal.

In the case of miniaturization, multiple working modes, high data processing requirements, large FPGA configuration program space and large resource occupation, the complicated multi-mode program is decomposed and recombined, the decomposed program is stored in a plurality of FLASH chips, and different configuration FLASH chips are selected according to the use requirements to select the multiple working modes.

As shown in fig. 1, the present invention provides a multimode data link system with an external download function, comprising: the system comprises an FPGA, an MCU main control module, a first FLASH module, a second FLASH module, a gate, a transceiving link module and an interface module;

the preset two sets of different configuration programs ensure that the receiving and transmitting link module is configured differently after the FPGA is started, different data processing work is required to be carried out for different communication modes, the configuration programs are required to be effectively split according to the use requirements when the system is used for designing products, the complex functions are reasonably decomposed, meanwhile, the circuit design of the receiving and transmitting link module ensures the reusability of the circuit in different communication modes as far as possible, a universal circuit is designed according to the use requirements, such as time sharing, common wave band sharing and the like, a small part of circuits which are not reusable can be configured in different split configuration programs in a distinguishing way, and shutdown processing is carried out when the circuits are not suitable, so that only the small part of PCB space and component cost are paid out, and a set of system which can be selected and adapted to different communication modes is enabled to be selected and adapted, the workload in actual work is as light as in a system of a single communication mode.

In a communication link, the burden of data processing of an FPGA aiming at a certain communication mode is relatively large, and the combination of multiple communication modes and other functions puts higher requirements on the resource occupancy rate and the power consumption of the FPGA, which collides with the development trend of miniaturization and low power consumption of the existing data link product. The product is designed according to the system described by the invention, the circuit has reusability, the PCB space occupation is smaller, the configuration program is reasonably divided, the resource occupancy rate is reduced, and the power consumption is reduced, so that the use requirements of a miniaturized, high-performance, high-integration, high-reliability and multi-mode communication data link terminal are met.

The FPGA downloads an external configuration program on line through the interface module and carries out data processing, the processed configuration program is written into the first FLASH module or the second FLASH module, and the preset configuration program in the first FLASH module or the second FLASH module is updated. The FPGA enables the RapidIO interface to be used interactively with the outside through the interface module, the transmission rate of the RapidIO interface is very high, and the data stream of the configuration program can be transmitted to the FPGA in a short time.

Updating the preset configuration program in the first FLASH module or the second FLASH module refers to upgrading the preset configuration program or replacing the preset configuration program with a new configuration program corresponding to other communication modes. It is more common that the configuration program of the FPGA often needs to be version-upgraded, and the external download capability enables the data link terminal to be more convenient to upgrade the program without removing the cover. In subsequent use, a third non-preset communication mode may be used, and since in the circuit design of the transceiving link module in the earlier stage, reusability of the circuit is guaranteed to be high, and parts which are not reusable are distinguished to be configured separately, a data link terminal designed by the system is compatible with the third non-preset communication mode, at this time, only an external download function is needed, a preset configuration program is replaced by a version which can cope with the third communication mode, upgrading of the whole product which can be compatible with a new communication mode is completed, upgrading of the product which can be compatible with the new communication mode is completed only through external download without changing a hardware state, cost is low, and a large amount of follow-up cost or development cost is reduced.

And an external configuration program which is downloaded on line by the FPGA through the interface module is transmitted into the download checking module through the RapidIO interface and carries out data processing. In the whole process of downloading the external configuration program on line, the transmission rate of the RapidIO interface is high, the transmission of data streams can be completed in a short time, and the subsequent checking work and writing work of the FPGA are relatively slow, so that a cache module needs to be developed for data caching. Even so, the speed of upgrading the configuration program through the external downloading function is also very fast, and in the verification of the actual product, the program upgrading is carried out by adopting an external downloading mode, which is faster than the speed of directly connecting the upper computer to carry out the program upgrading by returning the cover of the factory and using the most common JTAG interface.

Considering the reliability of the system, if a problem occurs in the transmission process of a configuration program performed by a certain FLASH module, the FPGA cannot normally work due to the abnormal configuration FLASH state, and cannot continue to complete or re-execute external downloading through the self program, but at this time, the first FLASH module and the second FLASH module can be mutually backed up, and the FPGA can load the configuration program in the backup FLASH to normally work only by letting the MCU give a switching instruction and restart the FPGA.

the antenna chain communication module is used for carrying out data interaction with an external data chain through the antenna chain communication module by the FPGA when communication is in an antenna chain communication mode, and the circuit design of the FPGA is suitable for the antenna chain communication mode and has a reusability design compatible with other communication modes;

the Beidou communication module is used for carrying out data interaction with an external data link through the FPGA when the communication is in a Beidou communication mode, the circuit design of the FPGA is suitable for the Beidou communication mode, and the FPGA has a reusability design compatible with other communication modes;

the standby communication module is used for performing data interaction with an external data link through the FPGA when communication is in other communication modes except the skyline and the Beidou, and the circuit design of the FPGA has prospective consideration of other communication modes, can be used as an expansion function, improves the expandability of products and has reusability compatible with other communication modes;

the ground communication module is used for communication between the FPGA and the ground station, the circuit design of the ground communication module is suitable for a ground communication mode, and the ground communication module has a reusability design compatible with other communication modes;

the engineering application background of the invention determines that the product object of the invention supports the three working modes, but in the field of civil communication, not only relay communication is provided, so that a data link terminal meeting the use requirement can be designed according to the design of any data link product of the invention.

The data processing module is used for sequentially carrying out filtering, amplification and analog/digital conversion on data received by the FPAG (field programmable gate array) when the FPGA is communicated with an external data chain or a ground station, and sequentially carrying out digital/analog conversion, amplification and filtering on data sent by the FPGA. The main data processing functions including analog/digital conversion and digital/analog conversion should have good reusability, and the non-reusable part is mainly a passive device and a closeable device in a communication link.

When the working mode is changed, the MCU sends a control instruction to control the gate to switch and control the FPGA to restart, so that the FPGA switches and reads the configuration program in the first FLASH module or the second FLASH module, and the working mode is switched.

Based on the multimode data link system, the invention also provides a data transmission method, which comprises the following steps:

(8) the FPGA downloads an external configuration program on line through the interface module and carries out data processing, the processed configuration program is written into the first FLASH module or the second FLASH module, and the preset configuration program in the first FLASH module or the second FLASH module is updated. Thus, other communication modes can be adopted for data transmission.

In summary, under the background of using a data link terminal with the use requirements of miniaturization, high performance, high integration, high reliability and multimode communication, the invention can effectively avoid the influences of large space occupation of a configuration program, high FPGA resource occupancy rate, high power consumption and the like caused by the high performance and multimode communication, has simple structure, simple and reliable use process and high configuration efficiency, can effectively reduce the power consumption, has an external downloading function and can carry out rapid program upgrading.

The invention is applied to the field of weapon data chains, and the product has the characteristics of long storage time, short working time, infrequent replacement of communication modes and the like.

The invention adopts RapidIO interface transmission configuration program to download to FPGA for restarting from the beginning, the time used is three fourths of the traditional JTAG interface updating program, and is one half of the time used for on-line refreshing of part on-satellite application.

KINTEX7 XILINX CORPORATION adopted by the invention^TMXC7K410T, the corresponding configuration FLASH is N25Q128 series serial FLASH, and the capacity is 128 Mbit. In the application of the early stage, the two communication modes of the antenna chain and the Beidou are not disassembled and placed in the same FPGA configuration program, and the function of data processing is added, so that the resource occupancy rate of the FPGA is over 90, the FPGA works in full, and the power consumption is 5W. The configuration program is split, and when the single communication mode works, the occupancy rate of FPGA resources is about 60%, and the power consumption is 3W.

The application background requires that the working time of the product is short, and the product has a stable working state before use, so that a simple and reliable reconfiguration mode is adopted for switching the communication mode, the hardware circuit is simple and reliable, a three-core architecture which is refreshed online can be optimized into a two-core architecture in the invention, and the application is more reliable.

The parts not described in the present invention belong to the known art in the field.

Claims

1. A multimode data link system with external download capability, comprising: the system comprises an FPGA, an MCU main control module, a first FLASH module, a second FLASH module, a gate, a transceiving link module and an interface module;

the FPGA downloads an external configuration program on line through an interface module and performs data processing, writes the processed configuration program into the first FLASH module or the second FLASH module, and updates the preset configuration program in the first FLASH module or the second FLASH module;

the FPGA checks the external configuration program downloaded online through the interface module through the download checking module, the external configuration program is stored in the cache module after the checking is successful, the downloaded external configuration program is written into the first FLASH module or the second FLASH module through the writing module, the written content is read through the reading module after the writing, and the checking is carried out through the secondary checking module, so that the written configuration program is ensured to be correct;

2. The multi-mode data-link system with external download capability as claimed in claim 1, wherein: the updating of the preset configuration program in the first FLASH module or the second FLASH module refers to upgrading the preset configuration program or replacing the preset configuration program with a new configuration program corresponding to other communication modes.

3. The multi-mode data-link system with external download capability as claimed in claim 1, wherein: the receiving and transmitting link module comprises an antenna link communication module, a Beidou communication module, a ground communication module, a standby communication module and a data processing module;

4. The multi-mode data-link system with external download capability as claimed in claim 1, wherein: configuration programs corresponding to the antenna chain communication mode and the Beidou communication mode are respectively prestored in the first FLASH module or the second FLASH module, and the configuration programs corresponding to other communication modes are realized in an FPGA (field programmable gate array) online downloading mode.

5. The multi-mode data-link system with external download capability as claimed in claim 1, wherein: when the working mode is changed, the MCU sends a control instruction to control the switching of the gate, so that the FPGA switches and reads the configuration program in the first FLASH module or the second FLASH module, thereby realizing the switching of the working mode.

6. The multi-mode data-link system with external download capability as claimed in claim 1, wherein: and the interface module receives an external control instruction through the CAN bus to further complete the selection of the working mode, and reports the monitoring state through the IIC bus.

7. The multi-mode data-link system with external download capability as claimed in claim 1, wherein: the FPGA power supply module is used for supplying power to other modules, and the clock module provides working clock signals for the FPGA.

8. A data transmission method implemented based on the multimode data chain system with external download function according to any claim 1 to 7, characterized by comprising the following steps: