CN106775796B - Firmware upgrading method, device and system - Google Patents
Firmware upgrading method, device and system Download PDFInfo
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- CN106775796B CN106775796B CN201510831125.3A CN201510831125A CN106775796B CN 106775796 B CN106775796 B CN 106775796B CN 201510831125 A CN201510831125 A CN 201510831125A CN 106775796 B CN106775796 B CN 106775796B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44568—Immediately runnable code
- G06F9/44573—Execute-in-place [XIP]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44568—Immediately runnable code
- G06F9/44578—Preparing or optimising for loading
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Abstract
The invention discloses a firmware upgrading method, a firmware upgrading device and a firmware upgrading system, which are used for improving the firmware upgrading speed and saving time. The invention provides a firmware upgrading method, which comprises the following steps: the FPGA receives the latest firmware version of the firmware to be upgraded sent by the processor; the method comprises the following steps of upgrading firmware of a configuration chip outside an FPGA by utilizing a preloaded firmware version with a programming function and the latest firmware version, and specifically comprises the following steps: the FPGA burns the latest firmware version into a version area where the firmware stored in a configuration chip outside the FPGA is located by utilizing a preloaded firmware version with a burning function; and the FPGA loads the latest firmware version from the version area to finish the firmware upgrading process of the configuration chip outside the FPGA.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a firmware upgrading method, apparatus, and system.
Background
Generally, when firmware of a configuration chip outside a Field Programmable Gate Array (FPGA) in a circuit board needs to be upgraded, programming of a firmware program in the configuration chip outside the FPGA is completed through a Joint Test Action Group (JTAG) interface, so that an upgrade process is completed. For example, at the beginning of debugging, a Personal Computer (PC) is used to upgrade the firmware of a configuration chip outside the FPGA in cooperation with dedicated downloaded software and JTAG cable; or, in the operation process of the single board, the board control processor simulates the JTAG time sequence to carry out firmware upgrade on the configuration chip outside the FPGA.
However, in the firmware upgrading process, since the JTAG interface is required to control the programming timing of the configuration chip outside the FPGA, the upgrading rate is limited by the rate of the JTAG interface. This is because, in the prior art, the JTAG clock rate generally does not exceed 2MHz, time consumption is within about 10 minutes when downloading small FPGA firmware, while for a large-capacity FPGA, the size of the firmware often reaches tens of megabytes, taking a certain type of FPGA with about 2000K of logic units as an example, the time consumed for programming a firmware program of a configuration chip exceeds 30 minutes, and the efficiency is very low.
In summary, when firmware upgrade is performed on a configuration chip outside the FPGA by using the prior art, the speed is low, and the time consumption is long.
Disclosure of Invention
The embodiment of the invention provides a firmware upgrading method, a firmware upgrading device and a firmware upgrading system, which are used for improving the firmware upgrading speed and saving time.
The firmware upgrading method provided by the embodiment of the invention comprises the following steps:
receiving the latest firmware version of the firmware to be upgraded;
upgrading the firmware by utilizing a preloaded firmware version with a programming function and the latest firmware version;
the receiving the latest firmware version of the firmware to be upgraded specifically includes:
the FPGA receives the latest firmware version of the firmware to be upgraded sent by the processor;
the firmware upgrading of the configuration chip outside the FPGA by utilizing the preloaded firmware version with the programming function and the latest firmware version specifically comprises the following steps:
the FPGA burns the latest firmware version into a version area where the firmware stored in a configuration chip outside the FPGA is located by utilizing a preloaded firmware version with a burning function;
and the FPGA loads the latest firmware version from the version area to finish the firmware upgrading process of the configuration chip outside the FPGA.
Therefore, the firmware version with the programming function is preloaded, the latest firmware version of the firmware to be upgraded is received, the firmware can be upgraded according to the preloaded firmware version with the programming function and the latest firmware version, a JTAG interface is not needed, the firmware upgrading speed is improved, and the firmware upgrading time is saved.
Preferably, the receiving, by the FPGA, the latest firmware version of the firmware to be upgraded sent by the processor specifically includes:
and the FPGA receives the latest firmware version of the firmware to be upgraded sent by the processor through a local bus LocalBus interface between the FPGA and the processor.
Because the LocalBus interface has higher speed and the data bits thereof can be expanded, higher transmission speed can be realized, and the time for upgrading the firmware is further shortened.
Preferably, the configuration chip comprises a first configuration chip and a second configuration chip;
the firmware version with the programming function is pre-programmed in the first configuration chip and/or the second configuration chip;
the FPGA burns the latest firmware version into the version area where the firmware stored in the first configuration chip is located by utilizing the preloaded firmware version with the burning function;
and the FPGA loads the firmware version with the programming function from the first configuration chip or the second configuration chip in advance.
Therefore, when the firmware needs to be upgraded for many times, the FPGA only needs to directly load the firmware version with the programming function without a JTAG interface, and the latest firmware version of the firmware to be upgraded can be programmed into the version area where the firmware to be upgraded is located according to the firmware version with the programming function, so that the upgrading of the firmware is completed, and the time for upgrading the firmware is greatly saved.
Preferably, the first configuration chip corresponds to a Byte Peripheral Interface (BPI) loading mode, and the second configuration chip corresponds to a Serial Peripheral Interface (SPI) loading mode.
Preferably, when the firmware version with the programming function is loaded from the first configuration chip in advance, the FPGA loads the firmware version with the programming function from the first configuration chip in advance, and specifically includes:
the FPGA determines to load the firmware version with the programming function from the first configuration chip by adopting a BPI loading mode according to a loading mode setting signal sent by a processor;
the FPGA determines an offset address of the firmware version with the programming function in the first configuration chip according to a version area selection signal sent by the processor;
and after receiving a program loading control signal sent by the processor, the FPGA loads the firmware version with the programming function according to the offset address of the first configuration chip.
Preferably, when the firmware version with the programming function is loaded from the second configuration chip in advance, the FPGA loads the firmware version with the programming function from the second configuration chip in advance, and specifically includes:
the FPGA determines to load the firmware version with the programming function from the second configuration chip by adopting an SPI loading mode according to a loading mode setting signal sent by the processor;
and after receiving a program loading control signal sent by the processor, the FPGA loads the firmware version with the programming function from the second configuration chip.
The firmware upgrading device provided by the embodiment of the invention comprises:
a receiving unit, configured to receive a latest firmware version of a firmware to be upgraded;
the execution unit is used for upgrading the firmware of the configuration chip outside the FPGA by utilizing the preloaded firmware version with the programming function and the latest firmware version; the receiving unit is specifically configured to:
receiving the latest firmware version of the firmware to be upgraded sent by a processor;
the execution unit is specifically configured to:
burning the latest firmware version into a version area where the firmware is stored in a configuration chip outside the device by using a preloaded firmware version with a burning function;
and loading the latest firmware version from the version area, and finishing the firmware upgrading process of the configuration chip outside the FPGA.
Preferably, when the receiving unit receives the latest firmware version of the firmware to be upgraded sent by the processor, the receiving unit is specifically configured to:
and receiving the latest firmware version of the firmware to be upgraded, which is sent by the processor, through a local bus LocalBus interface between the receiving unit and the processor.
Preferably, the configuration chip comprises a first configuration chip and a second configuration chip;
the firmware version with the programming function is pre-programmed in the first configuration chip and/or the second configuration chip;
the execution unit burns the latest firmware version into a version area where the firmware stored in the first configuration chip is located by using a preloaded firmware version with a burning function;
the execution unit loads the firmware version with the programming function from the first configuration chip or the second configuration chip in advance.
Preferably, the first configuration chip corresponds to a BPI loading mode, and the second configuration chip corresponds to an SPI loading mode.
Preferably, when the firmware version with the programming function is loaded from the first configuration chip in advance, the execution unit is specifically configured to:
according to a loading mode setting signal sent by a processor, determining to load the firmware version with the programming function from the first configuration chip by adopting a Byte Peripheral Interface (BPI) loading mode;
determining an offset address of the firmware version with the programming function in the first configuration chip according to a version area selection signal sent by the processor;
and after receiving a program loading control signal sent by the processor, loading the firmware version with the programming function according to the offset address of the first configuration chip.
Preferably, when the firmware version with the programming function is loaded from the second configuration chip in advance, the execution unit is specifically configured to:
according to a loading mode setting signal sent by a processor, determining to load the firmware version with the programming function from the second configuration chip by adopting a Serial Peripheral Interface (SPI) loading mode;
and after receiving a program loading control signal sent by the processor, loading the firmware version with the programming function from the second configuration chip.
The system for upgrading firmware of the configuration chip outside the field programmable gate array provided by the embodiment of the invention comprises the following steps:
the configuration chip is used for storing firmware;
the FPGA is used for receiving the latest firmware version of the firmware to be upgraded; upgrading the firmware to be upgraded by utilizing the preloaded firmware version with the programming function and the latest firmware version;
the processor is used for sending the latest firmware version of the firmware to be upgraded to the FPGA;
the FPGA is specifically configured to:
the FPGA receives the latest firmware version of the firmware to be upgraded sent by the processor;
the FPGA burns the latest firmware version into a version area where the firmware stored in a configuration chip outside the FPGA is located by utilizing a preloaded firmware version with a burning function;
and the FPGA loads the latest firmware version from the version area to finish the firmware upgrading process of the configuration chip outside the FPGA.
Preferably, the FPGA receives the latest firmware version of the firmware to be upgraded, which is sent by the processor, through a local bus LocalBus interface between the FPGA and the processor.
Preferably, the configuration chip comprises a first configuration chip and a second configuration chip; the firmware version with the programming function is pre-programmed in the first configuration chip and/or the second configuration chip;
the FPGA burns the latest firmware version into the version area where the firmware stored in the first configuration chip is located by utilizing the preloaded firmware version with the burning function;
and the FPGA loads the firmware version with the programming function from the first configuration chip or the second configuration chip in advance. .
Preferably, the first configuration chip corresponds to a BPI loading mode, and the second configuration chip corresponds to an SPI loading mode.
A general purpose input and/or output GPIO interface of the processor is connected with a special mode configuration pin of the FPGA; the GPIO interface of the processor is also connected with a pin corresponding to a program loading control signal of the FPGA; the GPIO interface of the processor is also connected with the highest address line of the first configuration chip;
when the firmware version with the programming function is loaded from the first configuration chip in advance by the FPGA:
the FPGA receives a loading mode setting signal sent by the processor through the GPIO interface through a special mode configuration pin, and the FPGA determines to load the firmware version with the programming function from the first configuration chip by adopting a Byte Peripheral Interface (BPI) loading mode according to the loading mode setting signal sent by the processor;
the FPGA receives a version area selection signal sent by the first configuration chip, wherein the version area selection signal is received by the first configuration chip through a most significant address line and is sent by the processor through the GPIO interface; the FPGA determines an offset address of the firmware version with the programming function in the first configuration chip according to a version area selection signal sent by the processor;
and the FPGA receives a program loading control signal sent by the processor through a GPIO (general purpose input/output) interface through a pin corresponding to the program loading control signal, and loads the firmware version with the programming function according to the offset address of the first configuration chip after receiving the program loading control signal sent by the processor.
Preferably, a general purpose input and/or output GPIO interface of the processor is connected to a dedicated mode configuration pin of the FPGA; the GPIO interface of the processor is also connected with a pin corresponding to a program loading control signal of the FPGA;
when the firmware version with the programming function is loaded from the second configuration chip in advance by the FPGA:
the FPGA receives a loading mode setting signal sent by the processor through the GPIO interface through a special mode configuration pin, and the FPGA determines to load the firmware version with the programming function from the second configuration chip by adopting a Serial Peripheral Interface (SPI) loading mode according to the loading mode setting signal sent by the processor;
and the FPGA receives a program loading control signal sent by the processor through a GPIO (general purpose input/output) interface through a pin corresponding to the program loading control signal, and loads the firmware version with the programming function from the second configuration chip after receiving the program loading control signal sent by the processor.
Drawings
Fig. 1 is a system architecture diagram of a firmware upgrade provided in an embodiment of the present invention;
fig. 2 is a schematic flowchart of firmware upgrade according to an embodiment of the present invention;
FIG. 3 is a timing diagram illustrating an embodiment of a processor triggering an FPGA to load a firmware version in a BPI loading mode;
fig. 4 is a timing diagram illustrating that a processor triggers an FPGA to load a firmware version in an SPI loading mode according to an embodiment of the present invention;
fig. 5 is a flowchart illustrating a firmware upgrading method according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a firmware upgrading apparatus according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a firmware upgrading method, a firmware upgrading device and a firmware upgrading system, which are used for improving the firmware upgrading speed and saving time.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a system architecture diagram of firmware upgrade according to an embodiment of the present invention.
The system comprises an FPGA, a first configuration chip, a second configuration chip and a processor. The first configuration chip corresponds to a BPI loading mode, and the second configuration chip corresponds to an SPI loading mode. The address space of the first configuration chip is divided into two parts: the version 1 area and the version 2 area are used for storing different firmware versions, the version 1 area corresponds to a low-order address area, and the version 2 area corresponds to a high-order address area. The processor is connected with the FPGA through a local bus LocalBus interface, a state and control signal exists between the processor and the FPGA, and a state and control signal also exists between the processor and the first configuration chip. Specifically, the state and control signals between the processor and the FPGA include: PROGRAM loading control signal (PROGRAM #), loading MODE setting signal (MODE), and loading completion identification signal (DONE); the status and control signals between the processor and the first configuration chip include: version area selection signal (RS). And the GPIO interface of the processor is respectively connected with a pin corresponding to a PROGRAM # signal, a special MODE configuration pin, a pin corresponding to a MODE signal and a pin corresponding to a DONE signal of the FPGA, and is also connected with a highest-order address line of the first configuration chip.
Preferably, the LocalBus interface adopted in the embodiment of the present invention is an 8-bit parallel LocalBus interface, and the interface rate is about 33MHz, but it is also possible to extend the data bit width to 16 bits or 32 bits, etc. to achieve a higher transmission rate.
The above-mentioned status and control signals are controlled by GPIO on the processor side, and the definition of each signal is shown in table 1. Wherein, the directions mentioned in the table are all based on the processor side, for example, the direction of the PROGRAM # signal is output, which means that the PROGRAM # is output from the GPIO interface of the processor; the direction of the DONE signal is input, and the DONE signal is input into a GPIO interface of the processor by the FPGA.
TABLE 1
In this embodiment, since the first configuration chip corresponds to the BPI loading mode and the version 1 area of the first configuration chip is set as the default version area, when the firmware version of the configuration chip outside the FPGA is upgraded, the latest firmware version is stored in the version 1 area of the first configuration chip by default. Of course, in specific implementation, the version 2 area of the first configuration chip may be set as the default version area, and the latest firmware version may be stored in the version 2 area by default.
Taking the FPGA and the configuration chip shown in fig. 1 as an example, a firmware upgrading process in the configuration chip outside the FPGA is introduced, and a complete firmware upgrading flow is shown in fig. 2.
Before upgrading the firmware, the method provided by the embodiment of the invention is used for preparing hardware, firmware, software and the like before upgrading, and then the method provided by the embodiment of the invention is used for executing an upgrading process.
Hardware preparation before upgrade
Before upgrading the firmware, the hardware circuits related to the single-board FPGA chip are connected as shown in fig. 1.
(II) firmware preparation before upgrade
When the firmware is upgraded for the first time, before the firmware is upgraded, a firmware version with a programming function needs to be burnt into a configuration chip outside the FPGA. After that, when the firmware needs to be upgraded for the second time or more, the firmware version containing the programming function does not need to be programmed in the configuration chip again. In this embodiment, two types of configuration chips are provided outside the FPGA, so that one configuration chip can be randomly selected from the first configuration chip and the second configuration chip, and the firmware version with the programming function is programmed and stored in the configuration chip, or the firmware version with the programming function is programmed in the first configuration chip and the second configuration chip simultaneously.
The firmware version with the programming function is that the firmware version with the programming function can be used for programming the firmware program of the configuration chip.
The firmware version with the programming function can be programmed in the configuration chip in one of the following ways:
the first method is as follows: burning a firmware version with a programming function into a second configuration chip (or a version 2 area of a first configuration chip) outside the FPGA through a programmer, and finishing the installation or welding of the configuration chip in a single board;
the second method comprises the following steps: and burning a firmware version containing a programming function into a second configuration chip (or a version 2 area of the first configuration chip) outside the FPGA installed on the single board through a JTAG download cable.
Of course, other modes can be adopted besides the above two modes, as long as the firmware version containing the programming function can be programmed in the second configuration chip (or the version 2 area of the first configuration chip) outside the FPGA, and the implementation mode of the present invention is not limited.
(III) Pre-upgrade software preparation
The relevant modules of the processor are provided with relevant programs for sending the latest firmware version of the firmware to be upgraded to the FPGA from the LocalBus interface according to bytes and setting the state and the control signals.
(IV) performing an upgrade procedure
The method comprises the following steps: and the FPGA loads a pre-programmed firmware version containing a programming function from the configuration chip.
Specifically, when the FPGA loads the firmware version containing the programming function, which is programmed in advance, from the configuration chip, one of the following ways may be adopted:
the first method is as follows: BPI load mode
FIG. 3 is a timing diagram of a processor triggering an FPGA to load a firmware version containing a write-burn function in BPI load mode. And the processor operates the GPIO to set the state value of the MODE signal to 010, which indicates that the FPGA adopts a BPI loading MODE to load the firmware version containing the programming function from the first configuration chip. And secondly, the processor sets the RS signal to be high level through the GPIO, and the offset address according to which the FPGA is loaded is the address of the version 2 area in the first configuration chip. And finally, the processor sends a low pulse to the PROGRAM # signal through the GPIO, and the DONE signal of the FPGA is changed into low level at the moment, which indicates that the loading process of the FPGA is started. When the DONE signal changes from low to high, the loading process is completed.
Specifically, the level of the DONE signal may be detected by the processor to determine whether the FPGA completes the loading process.
The second method comprises the following steps: SPI load mode
FIG. 4 is a timing diagram of a processor triggering an FPGA to load a firmware version containing a program function in SPI load mode. And the processor operates the GPIO to set the state value of the MODE signal to 001, which indicates that the FPGA adopts a BPI loading MODE to load the firmware version containing the programming function from the second configuration chip. At this time, the RS signal has no effect on the SPI load mode, and remains low here. And then, the processor sends a low pulse to the PROGRAM # signal through the GPIO, and the DONE signal of the FPGA is changed into low level at the moment, which indicates that the loading process of the FPGA is started. When the DONE signal changes from low to high, the loading process is completed.
Specifically, the level of the DONE signal may be detected by the processor to determine whether the FPGA completes the loading process.
Through any one of the above manners, the FPGA can complete the process of loading the firmware version with the programming function from the configuration chip, so that the FPGA can have the programming function so as to execute the subsequent programming of the latest firmware version of the firmware to be upgraded into the version area where the firmware to be upgraded is located.
Step two: and the FPGA receives the latest firmware version of the firmware to be upgraded sent by the processor, and updates and upgrades the firmware in the first configuration chip.
And the processor sends the latest firmware version of the firmware to be upgraded to the FPGA through a local bus LocalBus interface.
After receiving the latest firmware version, the FPGA burns and saves the latest firmware version in the version 1 area of the first configuration chip according to the preloaded firmware version with the burning and writing function and the corresponding time sequence.
Specifically, the FPGA may determine, according to the state and the control signal sent by the GPIO of the processor, a configuration chip or a version area in the configuration chip where the firmware to be upgraded is located, and execute a programming process of the latest firmware program.
Step three: and the FPGA loads the updated latest firmware version from the first configuration chip.
After the firmware version in the first configuration chip is upgraded, the processor sets a corresponding state and a control signal through the GPIO, so that the FPGA loads the updated latest firmware version from the first configuration chip, and the whole firmware upgrading process is finished.
The process of loading the latest firmware version from the first configuration chip by the FPGA is similar to the principle of loading the firmware version with the programming function from the configuration chip by the FPGA. Firstly, a processor sets a MODE signal through a GPIO (general purpose input/output), and sets an FPGA (field programmable gate array) loading MODE to be a BPI (field programmable gate array) active loading MODE; secondly, the processor sets the RS signal to be low level through GPIO, and instructs the FPGA to load a version program from a version 1 area of the first configuration chip; then, the processor sends a low pulse to the PROGRAM # signal through the GPIO, and the FPGA executes a loading process; and finally, the processor detects the DONE signal, and confirms that the loading of the latest firmware version is finished after the DONE signal is changed from low level to high level.
It can be understood that, the three steps of the hardware preparation before the upgrade, the firmware preparation before the upgrade and the software preparation before the upgrade are not in strict sequence, as long as the preparation of the corresponding hardware, firmware and software is completed before the step of performing the upgrade process.
Based on the above discussion, on the FPGA side, referring to fig. 5, a firmware upgrading method provided in an embodiment of the present invention includes:
s101, receiving the latest firmware version of the firmware to be upgraded;
s102, upgrading the firmware by utilizing a preloaded firmware version with a programming function and the latest firmware version; the receiving the latest firmware version of the firmware to be upgraded specifically includes:
the FPGA receives the latest firmware version of the firmware to be upgraded sent by the processor;
the firmware upgrading of the configuration chip outside the FPGA by utilizing the preloaded firmware version with the programming function and the latest firmware version specifically comprises the following steps:
the FPGA burns the latest firmware version into a version area where the firmware stored in a configuration chip outside the FPGA is located by utilizing a preloaded firmware version with a burning function;
and the FPGA loads the latest firmware version from the version area to finish the firmware upgrading process of the configuration chip outside the FPGA.
Preferably, the receiving, by the FPGA, the latest firmware version of the firmware to be upgraded sent by the processor specifically includes:
and the FPGA receives the latest firmware version of the firmware to be upgraded sent by the processor through a local bus LocalBus interface between the FPGA and the processor.
Preferably, in the embodiment of the present invention, the FPGA receives the latest firmware version of the firmware to be upgraded, which is sent by the processor, through a local bus LocalBus interface between the FPGA and the processor, and of course, the above process may also be implemented through other communication interfaces with higher speed, which is not limited in the present invention.
Preferably, the processor may be, for example, an ARM processor, a COM-E module, or the like.
That is to say, the FPGA can have the programming function by preloading the firmware version with the programming function, so that the latest firmware version of the firmware to be upgraded can be programmed and stored in the configuration chip without a JTAG interface, thereby completing the upgrade of the firmware program in the configuration chip.
Specifically, after the firmware version with the programming function is loaded by the FPGA, it can be understood that the FPGA is provided with a programming controller, and the latest firmware version of the firmware to be upgraded can be programmed into the configuration chip through the programming controller according to the corresponding time sequence.
The firmware version with the programming function is specifically any firmware version with the programming function, and other auxiliary functions are not limited to be extended on the version.
Preferably, the configuration chip includes a first configuration chip and a second configuration chip, wherein the first configuration chip corresponds to a BPI loading mode, and the second configuration chip corresponds to an SPI loading mode.
Preferably, the firmware version with the programming function is pre-programmed in the first configuration chip and/or the second configuration chip.
The FPGA burns the latest firmware version into the version area of the firmware to be upgraded stored in the first configuration chip by utilizing the preloaded firmware version with the burning function;
and the FPGA loads the firmware version with the programming function from the first configuration chip or the second configuration chip in advance.
That is, the firmware version with the programming function may be programmed in the first configuration chip in advance; or, the firmware version with the programming function may be pre-programmed in the second configuration chip; or, the firmware version with the programming function may be programmed in the first configuration chip and the second configuration chip at the same time in advance. When the firmware version with the programming function is programmed in the first configuration chip in advance, the FPGA loads the firmware version with the programming function from the first configuration chip; when the firmware version with the programming function is programmed in the second configuration chip in advance, the FPGA loads the firmware version with the programming function from the second configuration chip; when the firmware version with the programming function is simultaneously programmed in the first configuration chip and the second configuration chip in advance, the FPGA selects one of the first configuration chip and the second configuration chip and loads the firmware version with the programming function from the selected one.
Of course, in addition to the above cases, the configuration chip according to the embodiment of the present invention may also include only the first configuration chip, where the first configuration chip corresponds to the BPI loading mode. When the configuration chip only comprises a first configuration chip, the firmware version with the programming function is programmed in the first configuration chip in advance; therefore, the FPGA loads the firmware version with the programming function from the first configuration chip in advance; and the FPGA burns the latest firmware version into a version area where the firmware to be upgraded in the first configuration chip is stored by utilizing the preloaded firmware version with the burning function.
It should be noted that the first and second configuration chips do not represent any order, quantity or importance, but are used to distinguish different types of configuration chips. For example, the configuration chip corresponding to the SPI load mode may be referred to as a first configuration chip, and the configuration chip corresponding to the BPI load mode may be referred to as a second configuration chip.
Preferably, when the firmware version with the programming function is loaded from the first configuration chip in advance, the FPGA loads the firmware version with the programming function from the first configuration chip in advance, and specifically includes:
the FPGA determines to load the firmware version with the programming function from the first configuration chip by adopting a BPI loading mode according to a loading mode setting signal sent by a processor;
preferably, the loading MODE setting signal can be, for example, a MODE signal, which is a set of signals consisting of MODE [2], MODE [1] and MODE [0], for example, the processor can set the state value of the MODE signal to 010, which indicates the BPI loading MODE. And the MODE pin of the FPGA is connected with the GPIO interface of the processor, so that the FPGA receives the MODE signal sent by the processor, and the loading MODE is determined according to the MODE signal.
The FPGA determines an offset address of the firmware version with the programming function in the first configuration chip according to a version area selection signal sent by the processor;
preferably, the address space of the first configuration chip should at least accommodate two firmware versions, the first configuration chip may be divided into two version areas according to the offset address of the first configuration chip, one of the version areas is set as a default version area, and when the firmware needs to be updated, the latest firmware version is stored in the default version area. For example, the lower address is set as the default version area, but the upper address may also be set as the default version area, which is not limited by the present invention.
Preferably, the version area selection signal may be an RS signal, for example. In this embodiment, the GPIO interface of the processor is connected to the highest address line of the first configuration chip, and the offset address is selected according to the level of the RS.
And after receiving a program loading control signal sent by the processor, the FPGA loads the firmware version with the programming function according to the offset address of the first configuration chip.
Preferably, the PROGRAM load control signal may be, for example, a PROGRAM # signal, wherein "#" indicates that the signal is active low. And when the FPGA receives that the PROGRAM # signal sent by the processor is a low pulse, sampling the signal in the FPGA, and further loading the firmware version with the programming function from a specified position.
Preferably, when the firmware version with the programming function is loaded from the second configuration chip in advance, the FPGA loads the firmware version with the programming function from the second configuration chip in advance, and specifically includes:
the FPGA determines to load the firmware version with the programming function from the second configuration chip by adopting an SPI loading mode according to a loading mode setting signal sent by the processor;
here, the loading MODE setting signal may be, for example, a MODE signal.
And after receiving a program loading control signal sent by the processor, the FPGA loads the firmware version with the programming function from the second configuration chip.
Here, the PROGRAM load control signal may be, for example, a PROGRAM # signal, where "#" indicates that the signal is active when it is low.
Preferably, the processor determines whether the FPGA completes the process of loading the firmware version with the programming function according to a load complete identification signal (DONE); and determining whether the FPGA finishes the process of loading the latest firmware version of the firmware to be upgraded according to the DONE signal. Specifically, the processor detects the level of the DONE signal in the FPGA, and when the DONE signal changes from low level to high level, the processor determines that the FPGA has completed the loading process of the firmware program.
Correspondingly, on the FPGA side, referring to fig. 6, an embodiment of the firmware upgrading apparatus provided in the present invention includes:
a receiving unit 11, configured to receive a latest firmware version of firmware to be upgraded;
the execution unit 12 is configured to perform firmware upgrade on a configuration chip outside the FPGA by using a preloaded firmware version with a programming function and the latest firmware version; the receiving unit 11 is specifically configured to:
receiving the latest firmware version of the firmware to be upgraded sent by a processor;
the execution unit 12 is specifically configured to:
burning the latest firmware version into a version area where the firmware is stored in a configuration chip outside the device by using a preloaded firmware version with a burning function;
and loading the latest firmware version from the version area, and finishing the firmware upgrading process of the configuration chip outside the FPGA.
Preferably, when the receiving unit 11 receives the latest firmware version of the firmware to be upgraded sent by the processor, the receiving unit is specifically configured to:
the latest firmware version of the firmware to be upgraded sent by the processor is received through a local bus interface between the receiving unit 11 and the processor.
Preferably, the configuration chip comprises a first configuration chip and a second configuration chip;
the firmware version with the programming function is pre-programmed in the first configuration chip and/or the second configuration chip;
the execution unit burns the latest firmware version into the version area where the firmware to be upgraded is stored in the first configuration chip by using the preloaded firmware version with the burning function;
the execution unit loads the firmware version with the programming function from the first configuration chip or the second configuration chip in advance.
Preferably, the first configuration chip corresponds to a BPI loading mode, and the second configuration chip corresponds to an SPI loading mode.
Of course, in addition to the above cases, the configuration chip according to the embodiment of the present invention may also include only the first configuration chip, where the first configuration chip corresponds to the BPI loading mode. When the configuration chip only comprises a first configuration chip, the firmware version with the programming function is programmed in the first configuration chip in advance; thus, the execution unit 12 loads the firmware version with the programming function from the first configuration chip in advance; the execution unit 12 uses the preloaded firmware version with the programming function to program the latest firmware version into the version area where the firmware to be upgraded in the first configuration chip is stored.
Preferably, when the firmware version with the programming function is loaded from the first configuration chip in advance, the execution unit 12 is specifically configured to:
determining to load the firmware version with the programming function from the first configuration chip by adopting a BPI loading mode according to a loading mode setting signal sent by a processor;
preferably, the loading MODE setting signal may be, for example, a MODE signal.
Determining an offset address of the firmware version with the programming function in the first configuration chip according to a version area selection signal sent by the processor;
preferably, the version area selection signal may be an RS signal, for example.
And after receiving a program loading control signal sent by the processor, loading the firmware version with the programming function according to the offset address of the first configuration chip.
Preferably, the PROGRAM load control signal may be, for example, a PROGRAM # signal, wherein "#" indicates that the signal is active low.
Preferably, when the firmware version with the programming function is loaded from the second configuration chip in advance, the execution unit 12 is specifically configured to:
determining to load the firmware version with the programming function from the second configuration chip by adopting an SPI loading mode according to a loading mode setting signal sent by a processor;
and after receiving a program loading control signal sent by the processor, loading the firmware version with the programming function from the second configuration chip.
The firmware upgrading device provided by the embodiment of the invention can be an FPGA (field programmable gate array), for example.
Each of the functional units is implemented by a physical device such as a control processor having functions of receiving and processing.
An embodiment of the present invention provides a firmware upgrade system, including:
the configuration chip is used for storing firmware;
the FPGA is used for receiving the latest firmware version of the firmware to be upgraded; and upgrading the firmware to be upgraded by utilizing the preloaded firmware version with the programming function and the latest firmware version.
Preferably, the system further comprises:
and the processor is used for sending the latest firmware version of the firmware to be upgraded to the FPGA.
Preferably, the FPGA receives the latest firmware version of the firmware to be upgraded, which is sent by the processor, through a local bus LocalBus interface between the FPGA and the processor.
Preferably, the configuration chip comprises a first configuration chip and a second configuration chip; the firmware version with the programming function is pre-programmed in the first configuration chip and/or the second configuration chip;
the FPGA burns the latest firmware version into the version area where the firmware stored in the first configuration chip is located by utilizing the preloaded firmware version with the burning function;
and the FPGA loads the firmware version with the programming function from the first configuration chip or the second configuration chip in advance. .
Preferably, the first configuration chip corresponds to a BPI loading mode, and the second configuration chip corresponds to an SPI loading mode.
Preferably, a general purpose input and/or output GPIO interface of the processor is connected to a dedicated mode configuration pin of the FPGA; the GPIO interface of the processor is also connected with a pin corresponding to a program loading control signal of the FPGA; the GPIO interface of the processor is also connected with the highest address line of the first configuration chip;
when the firmware version with the programming function is loaded from the first configuration chip in advance by the FPGA:
the FPGA receives a loading mode setting signal sent by the processor through the GPIO interface through a special mode configuration pin, and the FPGA determines to load the firmware version with the programming function from the first configuration chip by adopting a Byte Peripheral Interface (BPI) loading mode according to the loading mode setting signal sent by the processor;
the FPGA receives a version area selection signal sent by the first configuration chip, wherein the version area selection signal is received by the first configuration chip through a most significant address line and is sent by the processor through the GPIO interface; the FPGA determines an offset address of the firmware version with the programming function in the first configuration chip according to a version area selection signal sent by the processor;
and the FPGA receives a program loading control signal sent by the processor through a GPIO (general purpose input/output) interface through a pin corresponding to the program loading control signal, and loads the firmware version with the programming function according to the offset address of the first configuration chip after receiving the program loading control signal sent by the processor.
Preferably, the loading MODE setting signal may be, for example, a MODE signal; the PROGRAM loading control signal may be, for example, a PROGRAM # signal; the version region selection signal may be, for example, an RS signal.
Preferably, a general purpose input and/or output GPIO interface of the processor is connected to a dedicated mode configuration pin of the FPGA; the GPIO interface of the processor is also connected with a pin corresponding to a program loading control signal of the FPGA;
when the firmware version with the programming function is loaded from the second configuration chip in advance by the FPGA:
the FPGA receives a loading mode setting signal sent by the processor through the GPIO interface through a special mode configuration pin, and the FPGA determines to load the firmware version with the programming function from the second configuration chip by adopting a Serial Peripheral Interface (SPI) loading mode according to the loading mode setting signal sent by the processor;
and the FPGA receives a program loading control signal sent by the processor through a GPIO (general purpose input/output) interface through a pin corresponding to the program loading control signal, and loads the firmware version with the programming function from the second configuration chip after receiving the program loading control signal sent by the processor.
Preferably, the loading MODE setting signal may be, for example, a MODE signal; the PROGRAM load control signal may be, for example, a PROGRAM # signal.
Preferably, a GPIO interface of the processor is connected to the load completion identification signal of the FPGA, and the processor detects the load completion identification signal through the GPIO interface and determines whether the FPGA loading process is completed by the level of the load completion identification signal. For example, the loading completion identification signal may be a DONE signal, and when the level of the DONE signal is a low level, it indicates that the FPGA is executing the loading process; when the level of the DONE signal is high, it indicates that the FPGA has completed the loading process.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (18)
1. A method for firmware upgrade, the method comprising:
receiving the latest firmware version of the firmware to be upgraded;
upgrading the firmware of a configuration chip outside the field programmable gate array FPGA by utilizing the preloaded firmware version with the programming function and the latest firmware version; the receiving the latest firmware version of the firmware to be upgraded specifically includes:
the FPGA receives the latest firmware version of the firmware to be upgraded sent by the processor;
the firmware upgrading of the configuration chip outside the FPGA by utilizing the preloaded firmware version with the programming function and the latest firmware version specifically comprises the following steps:
the FPGA burns the latest firmware version into a version area where the firmware stored in a configuration chip outside the FPGA is located by utilizing a preloaded firmware version with a burning function;
and the FPGA loads the latest firmware version from the version area to finish the firmware upgrading process of the configuration chip outside the FPGA.
2. The method according to claim 1, wherein the receiving, by the FPGA, the latest firmware version of the firmware to be upgraded sent by the processor specifically includes:
and the FPGA receives the latest firmware version of the firmware to be upgraded sent by the processor through a local bus LocalBus interface between the FPGA and the processor.
3. The method of claim 1, wherein the configuration chip comprises a first configuration chip and a second configuration chip; the firmware version with the programming function is pre-programmed in the first configuration chip and/or the second configuration chip;
the FPGA burns the latest firmware version into the version area where the firmware stored in the first configuration chip is located by utilizing the preloaded firmware version with the burning function;
and the FPGA loads the firmware version with the programming function from the first configuration chip or the second configuration chip in advance.
4. The method of claim 3, wherein the first configuration chip corresponds to a Byte Peripheral Interface (BPI) load mode and the second configuration chip corresponds to a Serial Peripheral Interface (SPI) load mode.
5. The method according to claim 4, wherein when the firmware version with the programming function is loaded in advance from the first configuration chip by the FPGA, and specifically includes:
the FPGA determines to load the firmware version with the programming function from the first configuration chip by adopting a Byte Peripheral Interface (BPI) loading mode according to a loading mode setting signal sent by the processor;
the FPGA determines an offset address of the firmware version with the programming function in the first configuration chip according to a version area selection signal sent by the processor;
and after receiving a program loading control signal sent by the processor, the FPGA loads the firmware version with the programming function according to the offset address of the first configuration chip.
6. The method according to claim 4, wherein when the firmware version with the programming function is loaded in advance from the second configuration chip by the FPGA, the FPGA loading the firmware version with the programming function in advance from the second configuration chip specifically comprises:
the FPGA determines to load the firmware version with the programming function from the second configuration chip by adopting a Serial Peripheral Interface (SPI) loading mode according to a loading mode setting signal sent by the processor;
and after receiving a program loading control signal sent by the processor, the FPGA loads the firmware version with the programming function from the second configuration chip.
7. A firmware upgrade apparatus, comprising:
a receiving unit, configured to receive a latest firmware version of a firmware to be upgraded;
the execution unit is used for upgrading the firmware of the configuration chip outside the FPGA by utilizing the preloaded firmware version with the programming function and the latest firmware version; the receiving unit is specifically configured to:
receiving the latest firmware version of the firmware to be upgraded sent by a processor;
the execution unit is specifically configured to:
burning the latest firmware version into a version area where the firmware is stored in a configuration chip outside the device by using a preloaded firmware version with a burning function;
and loading the latest firmware version from the version area, and finishing the firmware upgrading process of the configuration chip outside the FPGA.
8. The apparatus according to claim 7, wherein when the receiving unit receives the latest firmware version of the firmware to be upgraded sent by the processor, the receiving unit is specifically configured to:
and receiving the latest firmware version of the firmware to be upgraded, which is sent by the processor, through a local bus LocalBus interface between the receiving unit and the processor.
9. The apparatus of claim 7, wherein the configuration chip comprises a first configuration chip and a second configuration chip;
the firmware version with the programming function is pre-programmed in the first configuration chip and/or the second configuration chip;
the execution unit burns the latest firmware version into a version area where the firmware stored in the first configuration chip is located by using a preloaded firmware version with a burning function;
the execution unit loads the firmware version with the programming function from the first configuration chip or the second configuration chip in advance.
10. The apparatus of claim 9, wherein the first configuration chip corresponds to a Byte Peripheral Interface (BPI) load mode and the second configuration chip corresponds to a Serial Peripheral Interface (SPI) load mode.
11. The apparatus of claim 10, wherein the execution unit, when loading the firmware version with the programming function from the first configuration chip in advance, is specifically configured to:
according to a loading mode setting signal sent by a processor, determining to load the firmware version with the programming function from the first configuration chip by adopting a Byte Peripheral Interface (BPI) loading mode;
determining an offset address of the firmware version with the programming function in the first configuration chip according to a version area selection signal sent by the processor;
and after receiving a program loading control signal sent by the processor, loading the firmware version with the programming function according to the offset address of the first configuration chip.
12. The apparatus of claim 10, wherein the execution unit, when loading the firmware version with the programming function from the second configuration chip in advance, is specifically configured to:
according to a loading mode setting signal sent by a processor, determining to load the firmware version with the programming function from the second configuration chip by adopting a Serial Peripheral Interface (SPI) loading mode;
and after receiving a program loading control signal sent by the processor, loading the firmware version with the programming function from the second configuration chip.
13. A system for firmware upgrade of a configuration chip external to a field programmable gate array, the system comprising:
the configuration chip is used for storing firmware;
the field programmable gate array FPGA is used for receiving the latest firmware version of the firmware to be upgraded; upgrading the firmware to be upgraded by utilizing the preloaded firmware version with the programming function and the latest firmware version;
the processor is used for sending the latest firmware version of the firmware to be upgraded to the FPGA;
the FPGA is specifically configured to:
the FPGA receives the latest firmware version of the firmware to be upgraded sent by the processor;
the FPGA burns the latest firmware version into a version area where the firmware stored in a configuration chip outside the FPGA is located by utilizing a preloaded firmware version with a burning function;
and the FPGA loads the latest firmware version from the version area to finish the firmware upgrading process of the configuration chip outside the FPGA.
14. The system according to claim 13, wherein the FPGA receives the latest firmware version of the firmware to be upgraded sent by the processor through a LocalBus interface of a local bus between the FPGA and the processor.
15. The system of claim 13, wherein the configuration chip comprises a first configuration chip and a second configuration chip; the firmware version with the programming function is pre-programmed in the first configuration chip and/or the second configuration chip;
the FPGA burns the latest firmware version into the version area where the firmware stored in the first configuration chip is located by utilizing the preloaded firmware version with the burning function;
and the FPGA loads the firmware version with the programming function from the first configuration chip or the second configuration chip in advance.
16. The system of claim 15, wherein the first configuration chip corresponds to a Byte Peripheral Interface (BPI) load mode and the second configuration chip corresponds to a Serial Peripheral Interface (SPI) load mode.
17. The system according to claim 16, wherein the general purpose input and/or output GPIO interface of the processor is connected to a dedicated mode configuration pin of the FPGA; the GPIO interface of the processor is also connected with a pin corresponding to a program loading control signal of the FPGA; the GPIO interface of the processor is also connected with the highest address line of the first configuration chip;
when the firmware version with the programming function is loaded from the first configuration chip in advance by the FPGA:
the FPGA receives a loading mode setting signal sent by the processor through the GPIO interface through a special mode configuration pin, and the FPGA determines to load the firmware version with the programming function from the first configuration chip by adopting a Byte Peripheral Interface (BPI) loading mode according to the loading mode setting signal sent by the processor;
the FPGA receives a version area selection signal sent by the first configuration chip, wherein the version area selection signal is received by the first configuration chip through a most significant address line and is sent by the processor through the GPIO interface; the FPGA determines an offset address of the firmware version with the programming function in the first configuration chip according to a version area selection signal sent by the processor;
and the FPGA receives a program loading control signal sent by the processor through a GPIO (general purpose input/output) interface through a pin corresponding to the program loading control signal, and loads the firmware version with the programming function according to the offset address of the first configuration chip after receiving the program loading control signal sent by the processor.
18. The system according to claim 16, wherein the general purpose input and/or output GPIO interface of the processor is connected to a dedicated mode configuration pin of the FPGA; the GPIO interface of the processor is also connected with a pin corresponding to a program loading control signal of the FPGA;
when the firmware version with the programming function is loaded from the second configuration chip in advance by the FPGA:
the FPGA receives a loading mode setting signal sent by the processor through the GPIO interface through a special mode configuration pin, and the FPGA determines to load the firmware version with the programming function from the second configuration chip by adopting a Serial Peripheral Interface (SPI) loading mode according to the loading mode setting signal sent by the processor;
and the FPGA receives a program loading control signal sent by the processor through a GPIO (general purpose input/output) interface through a pin corresponding to the program loading control signal, and loads the firmware version with the programming function from the second configuration chip after receiving the program loading control signal sent by the processor.
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