CN112650543A - FPGA dynamic configuration method - Google Patents
FPGA dynamic configuration method Download PDFInfo
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- CN112650543A CN112650543A CN202011522137.5A CN202011522137A CN112650543A CN 112650543 A CN112650543 A CN 112650543A CN 202011522137 A CN202011522137 A CN 202011522137A CN 112650543 A CN112650543 A CN 112650543A
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- 230000005540 biological transmission Effects 0.000 claims description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
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Abstract
The invention discloses a FPGA dynamic configuration method, which is suitable for Virtex-7 chips of Xilinx company and comprises the following specific steps: the microprocessor receives a remote control instruction through the Ethernet and stores the control instruction in the EEPROM; the microprocessor controls the high two bits of BPI Flash address through GPIO interface to divide the Flash into four memory areas; the FPGA downloads the user program into different storage areas in the BPI Flash through a JTAG interface; the microprocessor controls the configuration pin of the FPGA and the high two bits of the BPI Flash address through the GPIO interface to realize the dynamic configuration of the FPGA program. The invention can realize the dynamic switching of the FPGA function in a flexible and configurable mode so as to meet different applications.
Description
Technical Field
The invention belongs to the field of electronic engineering and computer science, and particularly relates to a dynamic configuration method of an FPGA (field programmable gate array).
Background
As a highly parallel chip, FPGA is widely used in situations where real-time requirements are stringent. In the aspect of configuring an FPGA program, a JTAG downloading method is generally adopted at present, but only one program code can be downloaded by the method every time, when the FPGA function needs to be replaced, a new user program needs to be downloaded again through the JTAG, and the dynamic configuration of the FPGA program is inconvenient to realize.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the invention provides a dynamic FPGA configuration method, and discloses a dynamic FPGA configuration method, which can realize dynamic switching of FPGA functions in a flexible and configurable mode so as to meet different applications.
The technical scheme of the invention is as follows: a FPGA dynamic configuration method comprises the following steps:
the microprocessor realizes remote data transmission based on the Ethernet through a PHY chip, receives a remote control instruction through the Ethernet, stores the control instruction in an EEPROM, and automatically loads the last control instruction when the microprocessor is powered on next time; the control instruction is a time sequence instruction for controlling the FPGA to load different storage area codes from the BPI Flash;
the microprocessor controls BPI Flash and high two bits of address through a GPIO interface to divide the Flash into four storage areas, wherein each storage area stores one program and can dynamically configure four programs;
step (3) the FPGA downloads the user program to different storage areas in the BPI Flash through a JTAG interface;
and (4) the microprocessor controls a configuration pin of the FPGA through the GPIO interface to enable the configuration pin to generate a section of low level pulse, and after the FPGA detects the pulse, the FPGA loads user programs from different storage areas of the BPI Flash by combining with the high two bits of the BPI Flash address to realize the dynamic configuration of the FPGA function.
Furthermore, the microprocessor is connected with the Ethernet through a PHY chip, is connected with the EEPROM storage module through an I2C interface, and is also responsible for controlling the upper two bits of a BPI Flash address, controlling a configuration pin of an FPGA and controlling a power supply module; the FPGA is connected with the BPI Flash through an address line, a data line and a control line.
Furthermore, the method is suitable for Virtex-7FPGA chips of Xilinx company.
Further, the microprocessor is an STM32F 429.
Further, the BPI Flash is S29GL 01G.
Has the advantages that:
compared with the prior art, the invention has the advantages that: compared with the user program single download based on the JTAG mode, the FPGA function dynamic switching can be realized in a flexible and configurable mode so as to meet different applications.
Drawings
FIG. 1 is a block diagram of the system architecture of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by a person skilled in the art based on the embodiments of the present invention belong to the protection scope of the present invention without creative efforts.
The invention relates to a FPGA dynamic configuration method, which is suitable for Virtex-7FPGA chips of Xilinx company, and the specific model is XC7V690T-2FFG 1927I; the microprocessor is STM32F 429; is suitable for S29GL01G BPI Flash. The dynamic switching of FPGA functions can be realized in a flexible and configurable mode so as to meet different applications.
The system structure block diagram of the invention is shown in fig. 1.
The system comprises a microprocessor STM32F429, XC7V690T-2FFG1927I type FPGA, S29GL01G type BPI Flash, a JTAG download module, a PHY chip, an EEPROM storage module and a power supply module. The microprocessor is connected with the Ethernet through the PHY chip, is connected with the EEPROM storage module through the I2C interface, and is also responsible for controlling the high two bits of the BPI Flash address, controlling the configuration pins of the FPGA and controlling the power supply module. The FPGA is mainly connected with the BPI Flash through an address line, a data line and a control line.
According to one embodiment of the invention, the process of performing FPRA dynamic configuration is as follows:
the microprocessor realizes remote data transmission based on the Ethernet through a PHY chip, receives a remote control instruction through the Ethernet, stores the control instruction in an EEPROM, and automatically loads the last control instruction when the microprocessor is powered on next time; the control instruction can be a time sequence instruction for controlling the FPGA to load different storage area codes from the BPI Flash.
The microprocessor controls BPI Flash and high two bits of address through a GPIO interface to divide the Flash into four storage areas, wherein each storage area stores one program and can dynamically configure four programs; the invention is optional, and the BPI Flash can be other storage modules, and is taken as an example here.
Step (3) the FPGA downloads the user program to different storage areas in the BPI Flash through a JTAG interface;
and (4) the microprocessor controls a configuration pin of the FPGA through the GPIO interface to enable the configuration pin to generate a section of low level pulse, and after the FPGA detects the pulse, the FPGA loads user programs from different storage areas of the BPI Flash by combining with the high two bits of the BPI Flash address to realize the dynamic configuration of the FPGA function. The invention respectively stores 4 programs in 4 storage areas of BPI Flash, and the dynamic configuration of FPGA among 4 programs can be realized by the method of the invention.
In summary, the present invention discloses a dynamic configuration method for an FPGA, which can implement dynamic switching of FPGA functions in a flexible and configurable manner to meet different applications.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (5)
1. A FPGA dynamic configuration method is characterized by comprising the following steps:
the microprocessor realizes remote data transmission based on the Ethernet through a PHY chip, receives a remote control instruction through the Ethernet, stores the control instruction in an EEPROM, and automatically loads the last control instruction when the microprocessor is powered on next time; the control instruction is a time sequence instruction for controlling the FPGA to load different storage area codes from the BPI Flash;
the microprocessor controls BPI Flash and high two bits of address through a GPIO interface to divide the Flash into four storage areas, wherein each storage area stores one program and can dynamically configure four programs;
step (3) the FPGA downloads the user program to different storage areas in the BPI Flash through a JTAG interface;
and (4) the microprocessor controls a configuration pin of the FPGA through the GPIO interface to enable the configuration pin to generate a section of low level pulse, and after the FPGA detects the pulse, the FPGA loads user programs from different storage areas of the BPI Flash by combining with the high two bits of the BPI Flash address to realize the dynamic configuration of the FPGA function.
2. The method for dynamically configuring an FPGA of claim 1, wherein:
the microprocessor is connected with the Ethernet through a PHY chip, is connected with the EEPROM storage module through an I2C interface, and is also responsible for controlling the high two bits of the BPI Flash address, controlling the configuration pins of the FPGA and controlling the power supply module; the FPGA is connected with the BPI Flash through an address line, a data line and a control line.
3. The method for dynamically configuring an FPGA of claim 1, wherein: the method is suitable for Virtex-7FPGA chips of Xilinx company.
4. The method for dynamically configuring an FPGA of claim 1, wherein: the microprocessor is STM32F 429.
5. The method for dynamically configuring an FPGA of claim 1, wherein: the BPI Flash is S29GL 01G.
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