CN107577438A - The partitioning method and device of the memory space of flash memory in field programmable gate array - Google Patents
The partitioning method and device of the memory space of flash memory in field programmable gate array Download PDFInfo
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Abstract
The embodiment of the present invention provides a kind of partitioning method and device of the memory space of flash memory in field programmable gate array, belongs to on-site programmable gate array FPGA technical field.The division methods of the memory space of flash memory include in the field programmable gate array：The number that the memory space of flash memory in the FPGA of input is divided is received, the number is the natural number more than 0；Receive the size of each memory space of input；According to the number of the memory space of reception and the size of each memory space, corresponding divide is carried out to the memory space of flash memory in the FPGA.By the first address storage of each memory space in a register.The present invention solves the technical problem that the size and number of memory space is limited, significantly improve convenience and the flexibility of FPGA data storage, the space waste in traditional FPGA memory space division methods based on parallel FLASH is thoroughly avoided, significantly reduces the cost of FPGA system.
Description
Technical field
The present invention relates to on-site programmable gate array FPGA technical field, more particularly to a kind of field programmable gate array
The partitioning method and device of the memory space of middle flash memory.
Background technology
Field programmable gate array (FPGA：Field-Programmable Gate Array) scale it is increasing, it is right
The convenience of FPGA data storage and the cost of system propose higher requirement, in numerous FPGA data storage methods, base
In the FPGA data storage method of flash memory (FLASH), compared with other FPGA data storage methods, the convenience that is used with its user
Property and relatively low system cost, are widely used, become the FPGA data storage mode of industry main flow.
It is currently based on parallel FLASH FPGA memory space division methods, FPGA is by controlling parallel FLASH high-order ground
Location, parallel FLASH is divided into 2,4,8,16 etc. equal-sized 2nPart.The very day of one's doom be present in the size and number of memory space
System, seriously constrains convenience and the flexibility of FPGA data storage, and often has very big space waste in practical application,
Considerably increase the cost of FPGA system.
The content of the invention
The embodiment of the present invention provides a kind of partitioning method and device of the memory space of flash memory in field programmable gate array,
Convenience and the flexibility of FPGA data storage can be improved, the waste to memory space in practical application is reduced, so as to reduce
The cost of FPGA system.
Technical scheme is as follows used by the present invention solves above-mentioned technical problem：
The division of the memory space of flash memory in a kind of field programmable gate array provided according to an aspect of the present invention
Method, this method include：
The number that the memory space of flash memory in the FPGA of input is divided is received, the number is the natural number more than 0；
Receive the size of each memory space of input；
According to the number of the memory space of reception and the size of each memory space, the storage to flash memory in the FPGA
Space divides corresponding to carrying out.
By the first address storage of each memory space in a register.
In one of which embodiment, above-mentioned flash memory includes paralleling flash memory.
In one of which embodiment, the division methods of the memory space of flash memory are also wrapped in the field programmable gate array
Include：
When the flash memory is selected, the storage being stored in the register is obtained by the address bus interface of the FPGA
The first address in space；
The data being stored in memory space corresponding with the first address are read out, or should when receiving data
Data are stored in memory space corresponding with the first address.
In one of which embodiment, the division methods of the memory space of flash memory are also wrapped in the field programmable gate array
Include：
In the trailing edge of the first clock, the high level signal of output port saltus step is selected to choose the sudden strain of a muscle according to the piece of the FPGA
Deposit；
In the trailing edge of next clock of first clock, storage is obtained by the address bus output port of the FPGA
The first address of the memory space in the register；
The trailing edge of each clock within the clock cycle after next clock, it is total by the data of the FPGA
Line output terminal mouth sends the data being stored in memory space corresponding with the first address；
The rising edge of each clock within the clock cycle after next clock, it is total by the data of the FPGA
Line input port is by the data storage of reception in memory space corresponding with the first address.
In one of which embodiment, the division methods of the memory space of flash memory are also wrapped in the field programmable gate array
Include：
After the flash memory is selected, it is low level that the piece of the FPGA, which selects output port saltus step,.
In one of which embodiment, the division methods of the memory space of flash memory are also wrapped in the field programmable gate array
Include：
After the first address for the memory space being stored in the register is got, the effective output end in address of the FPGA
Mouth saltus step is high level.
The memory space of flash memory draws in a kind of field programmable gate array provided according to another aspect of the present invention
Separating device, the division device of the memory space of flash memory includes in the field programmable gate array：
First receiving module, the number that the memory space for receiving flash memory in the FPGA inputted is divided, the number are
Natural number more than 0；
Second receiving module, the size of each memory space for receiving input；
Division module, for the number of the memory space according to reception and the size of each memory space, to this
The memory space of flash memory carries out corresponding divide in FPGA.
Memory module, for the first address of each memory space to be stored in a register.
In one of which embodiment, above-mentioned flash memory includes paralleling flash memory, flash memory in the field programmable gate array
The division device of memory space include：
First address acquisition module, for when the flash memory is selected, storage to be obtained by the address bus interface of the FPGA
The first address of the memory space in the register；
Data access module, for being read out to the data being stored in memory space corresponding with the first address, or
The data are stored in memory space corresponding with the first address when receiving data.
In one of which embodiment, the division device of the memory space of flash memory also wraps in the field programmable gate array
Include：
Flash memory chooses module, and for the trailing edge in the first clock, the height of output port saltus step is selected according to the piece of the FPGA
Level signal chooses the flash memory；
The first address acquisition module is specifically used for the trailing edge in next clock of first clock, passes through the FPGA's
Address bus output port obtains the first address for the memory space being stored in the register；
The data access module includes：
Data storage cell, for the trailing edge of each clock within the clock cycle after next clock,
The data being stored in memory space corresponding with the first address are sent by the data/address bus output port of the FPGA；
Data transmission unit, for the rising edge of each clock within the clock cycle after next clock,
By the data/address bus input port of the FPGA by the data storage of reception in memory space corresponding with the first address.
In one of which embodiment, the division device of the memory space of flash memory also wraps in the field programmable gate array
Include：
First level saltus step module, for after the first address for the memory space being stored in the register is got,
The effective output port saltus step in address of the FPGA is high level.
Number and the appearance for the memory space being each divided of the invention by being divided according to the memory space of input
Amount size divides to the memory space of flash memory so that user can be according to storage of the data storage requirement of reality to flash memory
Space carries out the division of any amount, arbitrary size, with traditional FPGA memory space division methods phases based on parallel FLASH
Than, solve the limited technical problem of the size and number of memory space, significantly improve FPGA data storage convenience and
Flexibility so that the size and number for the data that user can store as needed divides depositing for parallel FLASH in practical application
Space is stored up, thoroughly avoids the space waste in traditional FPGA memory space division methods based on parallel FLASH, significantly drop
The low cost of FPGA system.
Brief description of the drawings
Fig. 1 is to be shown according to the connection of the on-site programmable gate array FPGA and flash memory FLASH of one embodiment of the present of invention
It is intended to；
Fig. 2 is the division side of the memory space of flash memory in the field programmable gate array according to one embodiment of the present of invention
The flow chart of method；
Fig. 3 is the division side of the memory space of flash memory in the field programmable gate array according to another embodiment of the present invention
The flow chart of method；
Fig. 4 is the FPGA memory space division methods stored based on parallel FLASH according to one embodiment of the present of invention
Time sequential routine schemes；
Fig. 5 is that the division of the memory space of flash memory in the field programmable gate array according to one embodiment of the present of invention fills
The exemplary block diagram put.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Fig. 1 is to be shown according to the connection of the on-site programmable gate array FPGA and flash memory FLASH of one embodiment of the present of invention
It is intended to, on-site programmable gate array FPGA and flash memory according to an embodiment of the invention is described in detail with reference to Fig. 1
FLASH annexation, as shown in figure 1, FPGA and parallel FLASH interconnection, wherein：
The FPGA parallel FLASH of output terminal of clock mouth CLK connections input end of clock mouth；
FPGA piece selects the parallel FLASH of output port CE_N connections chip select input port；
The FPGA parallel FLASH of the enabled output port OE_N connections of output output enables input port；
The FPGA parallel FLASH of the effective output port ADV_N connections in the address effective input port in address；
FPGA address bus output port A [25:0] parallel FLASH address bus input port is connected；
FPGA data/address bus input port D [15:0] parallel FLASH data/address bus output port is connected.
Wherein, the BPI in Fig. 1 (Business Process Improvement) represents that operation flow improves.
On-site programmable gate array FPGA, flash memory FLASH and the annexation between both that the present embodiment provides to
The division methods of the memory space of flash memory provide the support on hardware in following field programmable gate arrays.
Fig. 2 is the division side of the memory space of flash memory in the field programmable gate array according to one embodiment of the present of invention
The flow chart of method, it is described in detail in field programmable gate array according to an embodiment of the invention and dodges with reference to Fig. 2
The division methods for the memory space deposited, this method are applied to the on-site programmable gate array FPGA for including flash memory FLASH, the party
Method comprises the following steps S101 to S104.
S101, the number that the memory space of flash memory in the FPGA inputted is divided is received, the number is the nature more than 0
Number.
According to the present embodiment example, the number that above-mentioned memory space is divided is no longer confined in traditional scheme
Can only be 2nIt is individual, but can be any number more than 0.User by modes such as mouse, keyboards and can pass through computer
The form of input carries out the division of memory space to the flash memory.
S102, the size for receiving each memory space inputted.
, can be with when being not received by the size of each memory space of input according to the present embodiment example
The size of the memory space is respectively stored on the basis of the number received, that is, is defaulted as each memory space
Size is all identical.According to another example of the present embodiment, user can also make by oneself to the size for the memory space being divided
Justice is set, and the division of corresponding number, corresponding size is carried out according to the data storage requirement of reality.
S103, the number of the memory space and the size of each memory space according to reception, to flash memory in the FPGA
Memory space carry out corresponding to divide.
S104, by the storage of the first address of each memory space in a register.
In one of which embodiment, above-mentioned flash memory includes paralleling flash memory.Paralleling flash memory has that data throughout is big,
The characteristics of access speed of data is fast.
The present embodiment passes through the number being divided according to the memory space of input and the memory space being each divided
Amount of capacity divides to the memory space of flash memory so that user can deposit according to the data storage requirement of reality to flash memory
The division that space carries out any amount, arbitrary size is stored up, with traditional FPGA memory space division methods based on parallel FLASH
Compare, solve the limited technical problem of the size and number of memory space, significantly improve the convenience of FPGA data storage
And flexibility so that the size and number for the data that user can store as needed divides parallel FLASH's in practical application
Memory space, the space waste in traditional FPGA memory space division methods based on parallel FLASH is thoroughly avoided, significantly
Reduce the cost of FPGA system.
Fig. 3 is the division side of the memory space of flash memory in the field programmable gate array according to another embodiment of the present invention
The flow chart of method, in the one embodiment, the division methods of the memory space of flash memory in above-mentioned field programmable gate array
On the basis of including above-mentioned steps S101 to S104, further comprising the steps of S201 and S202.
S201, when the flash memory is selected, obtained and be stored in the register by the address bus interface of the FPGA
The first address of the memory space.
According to the present embodiment example, above-mentioned flash memory is chosen by the hop mode of low and high level, works as FPGA
Piece select output port signal CE_N to be changed into low level 0 from high level 1, choose parallel FLASH, conversely, when FPGA piece select it is defeated
When exit port signal CE_N is changed into high level 1 from low level 0, represent that the data access in the paralleling flash memory terminates, release pair is simultaneously
Row FLASH's chooses.
S202, the data being stored in memory space corresponding with the first address are read out, or are receiving data
When the data are stored in memory space corresponding with the first address.
According to the present embodiment example, read the data in memory space corresponding with the first address it
Afterwards, other electronic equipments, such as computer equipment can be sent the data to, is not limited herein.
In one of which embodiment, this method also includes：
In the trailing edge of the first clock, the high level signal of output port saltus step is selected to choose the sudden strain of a muscle according to the piece of the FPGA
Deposit；
In the trailing edge of next clock of first clock, storage is obtained by the address bus output port of the FPGA
The first address of the memory space in the register；
The trailing edge of each clock within the clock cycle after next clock, it is total by the data of the FPGA
Line output terminal mouth sends the data being stored in memory space corresponding with the first address；
The rising edge of each clock within the clock cycle after next clock, it is total by the data of the FPGA
Line input port is by the data storage of reception in memory space corresponding with the first address.
The present embodiment passes through the level signal for all kinds of interfaces being adapted in different clocks so that is provided according to the present embodiment
The division methods of the memory space of flash memory carry out the on-site programmable gate array FPGA of space division in field programmable gate array
Can the various protocol specifications that are applicable of compatible FPGA.
In one of which embodiment, this method also includes：
After the flash memory is selected, it is low level that the piece of the FPGA, which selects output port saltus step,.
In one of which embodiment, this method also includes：
After the first address for the memory space being stored in the register is got, the effective output end in address of the FPGA
Mouth saltus step is high level.
According to the present embodiment example, above-mentioned steps S101~S202 label is not used to limit in the present embodiment
The sequencing of each step, the numbering of each step are intended merely to so that can be with general reference step when describing each step
Label easily referred to, represented as long as the order that each step performs does not influence the logic of the present embodiment in the application
Within the scope of being claimed.
Fig. 4 is the FPGA memory space division methods stored based on parallel FLASH according to one embodiment of the present of invention
Time sequential routine schemes, on fpga chip after electricity, as shown in figure 4, FPGA, from parallel FLASH access evidences, its specific sequential flow is such as
It is lower described.
In clock falling edge, FPGA piece selects output port signal CE_N to be changed into 0 from 1, chooses parallel FLASH.
In next clock falling edge, the effective output port ADV_N in FPGA addresses is changed into 0 from 1, and parallel FLASH is next
Address bus output port A [25 of the individual rising edge clock from FPGA:0] address that FPGA address register 0 stores is received.
In next clock falling edge, the effective output port ADV_N in FPGA addresses is enabled defeated from 0 output for being changed into 1, FPGA
Exit port OE_N is changed into 0 from 1.The address end of transmission, data, which are sent, to be started.
In ensuing each clock falling edge, FLASH is with from FPGA address bus output port A [25:0] receive
Address be first address, send data from parallel FLASH data/address bus output port, each clock cycle sends 16 bit numbers
According to.
In ensuing each rising edge clock, data/address bus input port Ds [15 of the FPGA from FPGA:0] data are received,
Each clock cycle receives 16 bit datas.
After the data receiver in Part I space is complete, in clock falling edge, FPGA output enables output port OE_N by 0
The piece for being changed into 1, FPGA selects output port signal CE_N to be changed into 1 from 0.Data receiver terminates, and discharges and parallel FLASH is chosen.
If FPGA needs to read the data in parallel FLASH other parts space, in clock falling edge, FPGA piece selects
Output port signal CE_N is changed into 0 from 1, chooses parallel FLASH again, repeats the above steps.
FPGA memory spaces division methods provided by the invention based on parallel FLASH storages are existing based on parallel
On the basis of FLASH FPGA memory space division methods, increase n address register inside FPGA, it is parallel for configuring
The initial address of each memory spaces of FLASH.
The present embodiment is by selecting n address register and allowing user to carry out arbitrary disposition as needed, with biography
The FPGA memory space division methods based on parallel FLASH storages of system are compared, and solve the size and number limit of memory space
Problem processed, significantly improve convenience and the flexibility of FPGA data storage.The number that can be stored as needed in practical application
According to size and number divide parallel FLASH memory space, thoroughly avoid traditional FPGA storages based on parallel FLASH
Space waste in space-division method, significantly reduce the cost of FPGA system.
Fig. 5 is that the division of the memory space of flash memory in the field programmable gate array according to one embodiment of the present of invention fills
The exemplary block diagram put, the field programmable gate array of one embodiment of the present of invention is described in detail with reference to Fig. 5
The division device of the memory space of middle flash memory, the division device 10 of the memory space of flash memory includes in the field programmable gate array
First receiving module 11, the second receiving module 12, division module 13 and memory module 14 below.
First receiving module 11, the number that the memory space for receiving flash memory in the FPGA inputted is divided, the number
For the natural number more than 0.
According to the present embodiment example, the number that above-mentioned memory space is divided is no longer confined in traditional scheme
Can only be 2nIt is individual, but can be any number more than 0.User by modes such as mouse, keyboards and can pass through computer
The form of input carries out the division of memory space to the flash memory.
Second receiving module 12, the size of each memory space for receiving input.
, can be with when being not received by the size of each memory space of input according to the present embodiment example
The size of the memory space is respectively stored on the basis of the number received, i.e., second receiving module is defaulted as
The size of each memory space is identical.According to another example of the present embodiment, user can also be to the memory space that is divided
Size carry out self-defined setting, the division of corresponding number, corresponding size is carried out according to the data storage requirement of reality.
Division module 13, for the number of the memory space according to reception and the size of each memory space, to this
The memory space of flash memory carries out corresponding divide in FPGA.
Memory module 14, for the first address of each memory space to be stored in a register.
In one of which embodiment, above-mentioned flash memory includes paralleling flash memory.Paralleling flash memory has that data throughout is big,
The characteristics of access speed of data is fast.
In one of which embodiment, the division device 10 of the memory space of flash memory is gone back in the field programmable gate array
Including：
First address acquisition module, for when the flash memory is selected, storage to be obtained by the address bus interface of the FPGA
The first address of the memory space in the register；
Data access module, for being read out to the data being stored in memory space corresponding with the first address, or
The data are stored in memory space corresponding with the first address when receiving data.
According to the present embodiment example, above-mentioned first address acquisition module includes flash memory and chooses unit：For passing through
The hop mode of low and high level chooses the flash memory, and the flash memory is chosen unit and is specifically used for when FPGA piece selects output end message
Number CE_N is changed into low level 0 from high level 1, chooses parallel FLASH, conversely, when FPGA piece select output port signal CE_N by
When low level 0 is changed into high level 1, represents that the data access in the paralleling flash memory terminates, discharge and parallel FLASH is chosen.
According to the present embodiment example, read the data in memory space corresponding with the first address it
Afterwards, the data access module can send the data to other electronic equipments, such as computer equipment, not be limited herein.
In one of which embodiment, the division device 10 of the memory space of flash memory is gone back in the field programmable gate array
Including：
Flash memory chooses module, and for the trailing edge in the first clock, the height of output port saltus step is selected according to the piece of the FPGA
Level signal chooses the flash memory；
The first address acquisition module is specifically used for the trailing edge in next clock of first clock, passes through the FPGA's
Address bus output port obtains the first address for the memory space being stored in the register；
The data access module includes：
Data storage cell, for the trailing edge of each clock within the clock cycle after next clock,
The data being stored in memory space corresponding with the first address are sent by the data/address bus output port of the FPGA；
Data transmission unit, for the rising edge of each clock within the clock cycle after next clock,
By the data/address bus input port of the FPGA by the data storage of reception in memory space corresponding with the first address.
In one of which embodiment, the division device 10 of the memory space of flash memory is gone back in the field programmable gate array
Including：
First level saltus step module, for after the first address for the memory space being stored in the register is got,
The effective output port saltus step in address of the FPGA is high level.
In one of which embodiment, the division device 10 of the memory space of flash memory is gone back in the field programmable gate array
Including：
Second electrical level saltus step module, for after the flash memory is selected, it to be low electricity that the piece of the FPGA, which selects output port saltus step,
It is flat.
Wherein, the first above-mentioned level saltus step module and the meaning of " first " and " second " in second electrical level saltus step module
Be only that and be distinguish between two level saltus step modules, be not used to limit which level saltus step module priority it is higher or
Other limiting meanings.
Wherein, the modules that the division device of the memory space of flash memory includes in the field programmable gate array can be complete
Portion or part are realized by software, hardware or its combination.Further, the storage of flash memory is empty in the field programmable gate array
Between division device in modules can be program segment for realizing corresponding function.
The partitioning method and device of the memory space of flash memory, passes through root in the field programmable gate array that the present embodiment provides
Storage of the number and the amount of capacity for the memory space being each divided being divided according to the memory space of input to flash memory is empty
Between divided so that user can carry out any amount to the memory space of flash memory according to the data storage requirement of reality, appoint
The division for size of anticipating, compared with traditional FPGA memory space division methods based on parallel FLASH, solves memory space
The limited technical problem of size and number, significantly improve convenience and the flexibility of FPGA data storage so that practical application
The size and number for the data that middle user can store as needed divides parallel FLASH memory space, thoroughly avoids biography
Space waste in the FPGA memory space division methods based on parallel FLASH of system, significantly reduce the cost of FPGA system.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope that this specification is recorded all is considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more specific and detailed, but simultaneously
Can not therefore it be construed as limiting the scope of the patent.It should be pointed out that come for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. the division methods of the memory space of flash memory in a kind of field programmable gate array, it is characterised in that methods described includes：
The number that the memory space of flash memory in the FPGA of input is divided is received, the number is the natural number more than 0；
Receive the size of each memory space of input；
According to the number of the memory space of reception and the size of each memory space, flash memory in the FPGA is deposited
Store up space and carry out corresponding divide.
By the first address storage of each memory space in a register.
2. according to the method for claim 1, it is characterised in that the flash memory includes paralleling flash memory.
3. according to the method for claim 1, it is characterised in that methods described also includes：
When the flash memory is selected, obtained by the address bus interface of the FPGA described in being stored in the register
The first address of memory space；
The data being stored in memory space corresponding with the first address are read out, or when receiving data by described in
Data are stored in memory space corresponding with the first address.
4. according to the method for claim 3, it is characterised in that methods described also includes：
In the trailing edge of the first clock, the high level signal for selecting output port saltus step according to the piece of the FPGA chooses the sudden strain of a muscle
Deposit；
In the trailing edge of next clock of first clock, storage is obtained by the address bus output port of the FPGA
The first address of the memory space in the register；
The trailing edge of each clock within the clock cycle after next clock, the data by the FPGA are total
Line output terminal mouth sends the data being stored in memory space corresponding with the first address；
The rising edge of each clock within the clock cycle after next clock, the data by the FPGA are total
Line input port is by the data storage of reception in memory space corresponding with the first address.
5. according to the method for claim 4, it is characterised in that methods described also includes：
After the flash memory is selected, it is low level that the piece of the FPGA, which selects output port saltus step,.
6. according to the method for claim 4, it is characterised in that methods described also includes：
After the first address for the memory space being stored in the register is got, the address of the FPGA effectively exports
Port-hopping is high level.
7. the division device of the memory space of flash memory in a kind of field programmable gate array, it is characterised in that described device includes：
First receiving module, the number that the memory space for receiving flash memory in the FPGA inputted is divided, the number is big
In 0 natural number；
Second receiving module, the size of each memory space for receiving input；
Division module, for the number of the memory space according to reception and the size of each memory space, to described
The memory space of flash memory carries out corresponding divide in FPGA.
Memory module, for the first address of each memory space to be stored in a register.
8. device according to claim 7, it is characterised in that the flash memory includes paralleling flash memory；Described device includes：
First address acquisition module, for when the flash memory is selected, storage to be obtained by the address bus interface of the FPGA
The first address of the memory space in the register；
Data access module, for being read out to the data being stored in memory space corresponding with the first address, or
The data are stored in memory space corresponding with the first address when receiving data.
9. device according to claim 8, it is characterised in that described device also includes：
Flash memory chooses module, for the trailing edge in the first clock, is selected the height of output port saltus step electric according to the piece of the FPGA
Ordinary mail number chooses the flash memory；
The first address acquisition module is specifically used for the trailing edge in next clock of first clock, passes through the FPGA
Address bus output port obtain the first address for being stored in the memory space in the register；
The data access module includes：
Data storage cell, for the trailing edge of each clock within the clock cycle after next clock, lead to
The data/address bus output port for crossing the FPGA sends the data being stored in memory space corresponding with the first address；
Data transmission unit, for the rising edge of each clock within the clock cycle after next clock, lead to
The data/address bus input port of the FPGA is crossed by the data storage of reception in memory space corresponding with the first address.
10. device according to claim 8, it is characterised in that described device also includes：
First level saltus step module, for after the first address for the memory space being stored in the register is got,
The effective output port saltus step in address of the FPGA is high level.
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| CN107577438B (en) | 2020-07-28 |
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