CN107577438B - Method and device for dividing storage space of flash memory in field programmable gate array - Google Patents
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Abstract
The embodiment of the invention provides a method and a device for dividing a storage space of a flash memory in a field programmable gate array, belonging to the technical field of Field Programmable Gate Arrays (FPGA). the method for dividing the storage space of the flash memory in the field programmable gate array comprises the steps of receiving the number of divided storage spaces of the flash memory in the input FPGA, wherein the number is a natural number larger than 0, receiving the size of each input storage space, correspondingly dividing the storage space of the flash memory in the FPGA according to the number of the received storage spaces and the size of each storage space, and storing a first address of each storage space in a register.
Description
Technical Field
The invention relates to the technical field of Field Programmable Gate Arrays (FPGA), in particular to a method and a device for dividing a storage space of a flash memory in a field programmable gate array.
Background
The Field Programmable Gate Array (FPGA) has a larger scale, and puts higher demands on the convenience of FPGA data storage and the cost of the system, and among the FPGA data storage methods, the FPGA data storage method based on the flash memory (F L ASH) is widely applied with the convenience of user use and the lower system cost compared with other FPGA data storage methods, and becomes a mainstream FPGA data storage mode in the industry.
At present, in the method for dividing the storage space of the FPGA based on the parallel F L ASH, the FPGA divides the parallel F L ASH into 2, 4, 8, 16 and other equal-size 2 by controlling the high-order address of the parallel F L ASHnAnd (4) portions are obtained. The size and the number of the storage space are greatly limited, the convenience and the flexibility of FPGA data storage are seriously restricted, and the practical application often has great space waste, thereby greatly increasing the cost of the FPGA system.
Disclosure of Invention
The embodiment of the invention provides a method and a device for dividing the storage space of a flash memory in a field programmable gate array, which can improve the convenience and flexibility of FPGA data storage and reduce the waste of the storage space in practical application, thereby reducing the cost of an FPGA system.
The technical scheme adopted by the invention for solving the technical problems is as follows:
according to an aspect of the present invention, a method for partitioning a storage space of a flash memory in a field programmable gate array is provided, the method comprising:
receiving the number of divided storage spaces of a flash memory in an input FPGA, wherein the number is a natural number greater than 0;
receiving an input of a size of each of the storage spaces;
and correspondingly dividing the storage space of the flash memory in the FPGA according to the number of the received storage spaces and the size of each storage space.
The first address of each of the memory spaces is stored in a register.
In one embodiment, the flash memory includes a parallel flash memory.
In one embodiment, the method for dividing the storage space of the flash memory in the field programmable gate array further includes:
when the flash memory is selected, acquiring a first address of the storage space stored in the register through an address bus interface of the FPGA;
and reading the data stored in the storage space corresponding to the first address, or storing the data in the storage space corresponding to the first address when the data is received.
In one embodiment, the method for dividing the storage space of the flash memory in the field programmable gate array further includes:
selecting the flash memory according to a high level signal jumped by a chip selection output port of the FPGA on the falling edge of a first clock;
at the falling edge of the next clock of the first clock, acquiring the first address of the storage space stored in the register through an address bus output port of the FPGA;
transmitting data stored in the storage space corresponding to the first address through a data bus output port of the FPGA at a falling edge of each clock within a clock cycle after the next clock;
at the rising edge of each clock within the clock cycle following the next clock, the received data is stored in the memory space corresponding to the first address through the data bus input port of the FPGA.
In one embodiment, the method for dividing the storage space of the flash memory in the field programmable gate array further includes:
when the flash memory is selected, the chip selection output port of the FPGA jumps to a low level.
In one embodiment, the method for dividing the storage space of the flash memory in the field programmable gate array further includes:
and after the first address of the storage space stored in the register is acquired, the address effective output port of the FPGA jumps to high level.
According to another aspect of the present invention, an apparatus for dividing a storage space of a flash memory in a field programmable gate array is provided, the apparatus comprising:
the first receiving module is used for receiving the number of divided storage spaces of the flash memory in the input FPGA, and the number is a natural number greater than 0;
the second receiving module is used for receiving the input size of each storage space;
and the dividing module is used for correspondingly dividing the storage space of the flash memory in the FPGA according to the number of the received storage spaces and the size of each storage space.
And the storage module is used for storing the first address of each storage space in a register.
In one embodiment, the flash memory includes a parallel flash memory, and the apparatus for dividing the storage space of the flash memory in the field programmable gate array includes:
the first address acquisition module is used for acquiring the first address of the storage space stored in the register through an address bus interface of the FPGA when the flash memory is selected;
and the data access module is used for reading the data stored in the storage space corresponding to the first address or storing the data in the storage space corresponding to the first address when the data is received.
In one embodiment, the apparatus for dividing the storage space of the flash memory in the field programmable gate array further includes:
the flash memory selection module is used for selecting the flash memory according to the high level signal jumped by the chip selection output port of the FPGA at the falling edge of the first clock;
the first address obtaining module is specifically configured to obtain, at a falling edge of a next clock of the first clock, a first address of the storage space stored in the register through an address bus output port of the FPGA;
the data access module includes:
the data storage unit is used for sending the data stored in the storage space corresponding to the first address through a data bus output port of the FPGA at the falling edge of each clock in a clock period after the next clock;
and the data sending unit is used for storing the received data in the storage space corresponding to the first address through the data bus input port of the FPGA at the rising edge of each clock in a clock cycle after the next clock.
In one embodiment, the apparatus for dividing the storage space of the flash memory in the field programmable gate array further includes:
and the first level jump module is used for jumping an effective address output port of the FPGA to a high level after the first address of the storage space stored in the register is acquired.
According to the method, the storage space of the flash memory is divided according to the number of the divided input storage spaces and the capacity of each divided storage space, so that a user can divide the storage space of the flash memory into any number and any size according to the actual data storage requirement.
Drawings
Fig. 1 is a schematic diagram of connection between a field programmable gate array FPGA and a flash memory F L ASH according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for partitioning a memory space of a flash memory in a field programmable gate array according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for partitioning a memory space of a flash memory in a field programmable gate array according to another embodiment of the present invention;
FIG. 4 is a timing diagram illustrating the operation of the FPGA memory space partitioning method based on parallel F L ASH storage according to an embodiment of the present invention;
fig. 5 is a block diagram illustrating an exemplary structure of a device for dividing a storage space of a flash memory in a field programmable gate array according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a schematic diagram of connection between a field programmable gate array FPGA and a flash memory F L ASH according to an embodiment of the present invention, and the connection relationship between the field programmable gate array FPGA and the flash memory F L ASH according to an embodiment of the present invention is described in detail below with reference to fig. 1, where the FPGA and the parallel F L ASH are interconnected as shown in fig. 1, where:
a clock output port C L K of the FPGA is connected with a clock input port of the parallel F L ASH;
a chip selection output port CE _ N of the FPGA is connected with a chip selection input port of the parallel F L ASH;
an output enabling output port OE _ N of the FPGA is connected with an output enabling input port of the parallel F L ASH;
an address valid output port ADV _ N of the FPGA is connected with an address valid input port of the parallel F L ASH;
the address bus output port A [25:0] of the FPGA is connected with the address bus input port of the parallel F L ASH;
the data bus input ports D [15:0] of the FPGA are connected with the data bus output ports of the parallel F L ASH.
Wherein, bpi (business Process improvement) in fig. 1 represents business Process improvement.
The field programmable gate array FPGA, the flash memory F L ASH and the connection relationship between the two provided by this embodiment provide hardware support for the following method for dividing the storage space of the flash memory in the field programmable gate array.
Fig. 2 is a flowchart of a method for dividing a storage space of a flash memory in a field programmable gate array according to an embodiment of the present invention, and the method for dividing a storage space of a flash memory in a field programmable gate array according to an embodiment of the present invention is described in detail below with reference to fig. 2, and is applied to a field programmable gate array FPGA including a flash memory F L ASH, and the method includes the following steps S101 to S104.
S101, receiving the number of divided storage spaces of the input flash memory in the FPGA, wherein the number is a natural number larger than 0.
According to an example of the embodiment, the number of the divided storage spaces is no longer limited to only 2 in the conventional schemenBut can be any number greater than 0. The user can divide the storage space of the flash memory by means of a mouse, a keyboard and the like and in a computer input mode.
And S102, receiving the input size of each storage space.
According to an example of this embodiment, when the size of each of the storage spaces that has not received the input is not received, the size of the storage space may be stored equally on the basis of the number received, that is, the size of each of the storage spaces is the same by default. According to another example of this embodiment, the user may also perform a custom setting on the size of the partitioned storage space, and perform the corresponding number and size partitioning according to the actual data storage requirement.
S103, correspondingly dividing the storage space of the flash memory in the FPGA according to the number of the received storage spaces and the size of each storage space.
And S104, storing the first address of each storage space in a register.
In one embodiment, the flash memory includes a parallel flash memory. The parallel flash memory has the characteristics of large data throughput and high data access speed.
In the embodiment, the storage space of the flash memory is divided according to the number of divided input storage spaces and the capacity of each divided storage space, so that a user can divide the storage space of the flash memory into any number and any size according to actual data storage requirements.
Fig. 3 is a flowchart of a method for dividing a storage space of a flash memory in a field programmable gate array according to another embodiment of the present invention, in this embodiment, the method for dividing a storage space of a flash memory in a field programmable gate array further includes the following steps S201 and S202 on the basis of the steps S101 to S104.
S201, when the flash memory is selected, the first address of the storage space stored in the register is obtained through an address bus interface of the FPGA.
According to an example of this embodiment, the flash memory is selected by high-low level jump, when the chip select output port signal CE _ N of the FPGA changes from high level 1 to low level 0, the parallel F L ASH is selected, and conversely, when the chip select output port signal CE _ N of the FPGA changes from low level 0 to high level 1, it indicates that data access in the parallel flash memory is finished, and the selection of the parallel F L ASH is released.
S202, reading the data stored in the storage space corresponding to the first address, or storing the data in the storage space corresponding to the first address when receiving the data.
According to an example of the embodiment, after the data in the storage space corresponding to the first address is read, the data may be sent to other electronic devices, such as a computer device, without limitation.
In one embodiment thereof, the method further comprises:
selecting the flash memory according to a high level signal jumped by a chip selection output port of the FPGA on the falling edge of a first clock;
at the falling edge of the next clock of the first clock, acquiring the first address of the storage space stored in the register through an address bus output port of the FPGA;
transmitting data stored in the storage space corresponding to the first address through a data bus output port of the FPGA at a falling edge of each clock within a clock cycle after the next clock;
at the rising edge of each clock within the clock cycle following the next clock, the received data is stored in the memory space corresponding to the first address through the data bus input port of the FPGA.
In this embodiment, by adapting the level signals of various interfaces in different clocks, the field programmable gate array FPGA performing space division according to the method for dividing the storage space of the flash memory in the field programmable gate array provided by this embodiment can be compatible with various protocol specifications applicable to the FPGA.
In one embodiment thereof, the method further comprises:
when the flash memory is selected, the chip selection output port of the FPGA jumps to a low level.
In one embodiment thereof, the method further comprises:
and after the first address of the storage space stored in the register is acquired, the address effective output port of the FPGA jumps to high level.
According to an example of this embodiment, the reference numerals of the above steps S101 to S202 are not used to limit the sequence of each step in this embodiment, and the number of each step is only used to make the reference numerals that refer to the steps in the description of each step be used for convenient reference, so long as the execution sequence of each step does not affect the logic of this embodiment, that is, the steps are represented within the scope of the present application.
Fig. 4 is an operation timing diagram of an FPGA memory space partitioning method based on parallel F L ASH storage according to an embodiment of the present invention, and after an FPGA chip is powered on, as shown in fig. 4, the FPGA fetches data from parallel F L ASH, and a specific timing flow thereof is as follows.
On the falling edge of the clock, the chip select output port signal CE _ N of the FPGA changes from 1 to 0, and parallel F L ASH is selected.
On the next clock falling edge, the FPGA address valid output port ADV _ N changes from 1 to 0, and parallel F L ASH receives the address stored by address register 0 of the FPGA from address bus output port A [25:0] of the FPGA on the next clock rising edge.
On the next clock falling edge, the FPGA address valid output port ADV _ N changes from 0 to 1, and the output enable output port OE _ N of the FPGA changes from 1 to 0. The address transmission ends and the data transmission begins.
On the next falling edge of each clock, F L ASH sends data from the data bus output port of parallel F L ASH with the address received from the address bus output port A [25:0] of the FPGA as the head address, sending 16 bits of data each clock cycle.
On the next rising edge of the clock, the FPGA receives data from the FPGA's data bus input ports D [15:0], which receives 16 bits of data each clock cycle.
After the data in the first partial space is received, on the falling edge of the clock, the output enable output port OE _ N of the FPGA is changed from 0 to 1, the chip select output port signal CE _ N of the FPGA is changed from 0 to 1, the data receiving is finished, and the parallel F L ASH is released from being selected.
If the FPGA needs to read the data of other partial spaces of the parallel F L ASH, a chip selection output port signal CE _ N of the FPGA is changed from 1 to 0 on the falling edge of the clock, the parallel F L ASH is reselected, and the steps are repeated.
On the basis of the traditional FPGA storage space division method based on parallel F L ASH, the FPGA storage space division method based on parallel F L ASH storage provided by the invention is additionally provided with n address registers in the FPGA for configuring the initial address of each storage space of the parallel F L ASH.
In the embodiment, n address registers are selected and a user is allowed to carry out arbitrary configuration as required, compared with the traditional FPGA storage space dividing method based on parallel F L ASH storage, the problem of limitation of the size and the number of the storage space is solved, the convenience and the flexibility of FPGA data storage are obviously improved, in practical application, the storage space of the parallel F L ASH can be divided according to the size and the number of the data to be stored, the space waste in the traditional FPGA storage space dividing method based on the parallel F L ASH is thoroughly avoided, and the cost of an FPGA system is obviously reduced.
Fig. 5 is a block diagram illustrating an exemplary structure of an apparatus for dividing a storage space of a flash memory in a field programmable gate array according to an embodiment of the present invention, and the apparatus for dividing a storage space of a flash memory in a field programmable gate array according to an embodiment of the present invention is described in detail below with reference to fig. 5, where the apparatus 10 for dividing a storage space of a flash memory in a field programmable gate array includes the following first receiving module 11, second receiving module 12, dividing module 13, and storage module 14.
The first receiving module 11 is configured to receive the number of divided storage spaces of the flash memory in the input FPGA, where the number is a natural number greater than 0.
According to an example of the embodiment, the number of the divided storage spaces is no longer limited to only 2 in the conventional schemenBut can be any number greater than 0. The user can use the mouse,The storage space of the flash memory is divided by means of a keyboard and the like and by means of a computer input mode.
A second receiving module 12, configured to receive an input of each size of the storage space.
According to an example of this embodiment, when the size of each storage space that has not received the input is not received, the size of the storage space may be stored equally based on the number received, that is, the second receiving module defaults that the size of each storage space is the same. According to another example of this embodiment, the user may also perform a custom setting on the size of the partitioned storage space, and perform the corresponding number and size partitioning according to the actual data storage requirement.
And the dividing module 13 is configured to correspondingly divide the storage space of the flash memory in the FPGA according to the number of the received storage spaces and the size of each storage space.
And a storage module 14, configured to store the first address of each of the storage spaces in a register.
In one embodiment, the flash memory includes a parallel flash memory. The parallel flash memory has the characteristics of large data throughput and high data access speed.
In one embodiment, the apparatus 10 for dividing the storage space of the flash memory in the field programmable gate array further includes:
the first address acquisition module is used for acquiring the first address of the storage space stored in the register through an address bus interface of the FPGA when the flash memory is selected;
and the data access module is used for reading the data stored in the storage space corresponding to the first address or storing the data in the storage space corresponding to the first address when the data is received.
According to an example of this embodiment, the head address obtaining module includes a flash memory selecting unit, configured to select the flash memory by a high-low level jump manner, where the flash memory selecting unit is specifically configured to select the parallel F L ASH when a chip select output port signal CE _ N of the FPGA changes from a high level 1 to a low level 0, and conversely, when the chip select output port signal CE _ N of the FPGA changes from the low level 0 to the high level 1, it indicates that data access in the parallel flash memory is finished, and release selection of the parallel F L ASH.
According to an example of the embodiment, after reading the data in the storage space corresponding to the first address, the data access module may transmit the data to other electronic devices, such as a computer device, without limitation.
In one embodiment, the apparatus 10 for dividing the storage space of the flash memory in the field programmable gate array further includes:
the flash memory selection module is used for selecting the flash memory according to the high level signal jumped by the chip selection output port of the FPGA at the falling edge of the first clock;
the first address obtaining module is specifically configured to obtain, at a falling edge of a next clock of the first clock, a first address of the storage space stored in the register through an address bus output port of the FPGA;
the data access module includes:
the data storage unit is used for sending the data stored in the storage space corresponding to the first address through a data bus output port of the FPGA at the falling edge of each clock in a clock period after the next clock;
and the data sending unit is used for storing the received data in the storage space corresponding to the first address through the data bus input port of the FPGA at the rising edge of each clock in a clock cycle after the next clock.
In one embodiment, the apparatus 10 for dividing the storage space of the flash memory in the field programmable gate array further includes:
and the first level jump module is used for jumping an effective address output port of the FPGA to a high level after the first address of the storage space stored in the register is acquired.
In one embodiment, the apparatus 10 for dividing the storage space of the flash memory in the field programmable gate array further includes:
and the second level jump module is used for jumping to a low level from a chip selection output port of the FPGA after the flash memory is selected.
The first and second levels of the first and second level-shifting modules are only used for distinguishing the two level-shifting modules, and are not used for limiting which level-shifting module has a higher priority or other limiting meanings.
The modules included in the partitioning device for the storage space of the flash memory in the field programmable gate array may be implemented in whole or in part by software, hardware, or a combination thereof. Further, each module in the partitioning apparatus of the storage space of the flash memory in the field programmable gate array may be a program segment for implementing a corresponding function.
According to the method and the device for dividing the storage space of the flash memory in the FPGA, the storage space of the flash memory is divided according to the number of divided input storage spaces and the capacity of each divided storage space, so that a user can divide the storage space of the flash memory into any number and any size according to actual data storage requirements.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (2)
1. A method for dividing a storage space of a flash memory in a field programmable gate array is characterized by comprising the following steps:
receiving the number of divided storage spaces of a flash memory in an input FPGA, wherein the number is a natural number greater than 0;
receiving an input of a size of each of the storage spaces;
correspondingly dividing the storage space of the flash memory in the FPGA according to the received number of the storage spaces and the size of each storage space;
storing a first address of each of the memory spaces in a register;
when the flash memory is selected, acquiring a first address of the storage space stored in the register through an address bus interface of the FPGA, wherein the flash memory is a parallel flash memory;
reading data stored in a storage space corresponding to the first address, and storing the data in the storage space corresponding to the first address when the data are received;
selecting the flash memory according to a high level signal hopped by a chip selection output port of the FPGA at the falling edge of a first clock, and after the flash memory is selected, hopping the chip selection output port of the FPGA to a low level;
at the falling edge of the next clock of the first clock, acquiring the first address of the storage space stored in the register through an address bus output port of the FPGA; after the first address of the storage space stored in the register is acquired, the effective address output port of the FPGA jumps to a high level; transmitting data stored in the storage space corresponding to the first address through a data bus output port of the FPGA at a falling edge of each clock within a clock cycle after the next clock; storing the received data in the memory space corresponding to the first address through the data bus input port of the FPGA at a rising edge of each clock within a clock cycle after the next clock.
2. An apparatus for partitioning storage space of a flash memory in a field programmable gate array, the apparatus comprising:
the first receiving module is used for receiving the number of divided storage spaces of the flash memory in the input FPGA, and the number is a natural number greater than 0;
a second receiving module, configured to receive an input size of each of the storage spaces;
the dividing module is used for correspondingly dividing the storage space of the flash memory in the FPGA according to the received number of the storage spaces and the size of each storage space;
the storage module is used for storing the first address of each storage space in a register;
a first address obtaining module, configured to obtain, through an address bus interface of the FPGA, a first address of the storage space stored in the register when the flash memory is selected, where the flash memory is a parallel flash memory;
the data access module is used for reading the data stored in the storage space corresponding to the first address and storing the data in the storage space corresponding to the first address when the data are received;
the flash memory selection module is used for selecting the flash memory according to a high level signal hopped by a chip selection output port of the FPGA at the falling edge of a first clock, and when the flash memory is selected, the chip selection output port of the FPGA is hopped to be a low level;
the first address obtaining module is specifically configured to obtain, at a falling edge of a next clock of the first clock, a first address of the storage space stored in the register through an address bus output port of the FPGA;
the first level jump module is used for jumping an effective address output port of the FPGA to a high level after the first address of the storage space stored in the register is acquired;
the data access module includes:
a data storage unit, configured to send, through a data bus output port of the FPGA, data stored in a storage space corresponding to the head address on a falling edge of each clock within a clock cycle after the next clock;
and the data sending unit is used for storing the received data in the storage space corresponding to the first address through the data bus input port of the FPGA at the rising edge of each clock in a clock cycle after the next clock.
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| WO2016149905A1 (en) * | 2015-03-24 | 2016-09-29 | Hewlett-Packard Development Company, L.P. | Field programmable gate array memory allocation |
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| CN102346677A (en) * | 2010-08-05 | 2012-02-08 | 盛乐信息技术（上海）有限公司 | Method for upgrading field programmable gate array (FPGA) program |
| WO2016149905A1 (en) * | 2015-03-24 | 2016-09-29 | Hewlett-Packard Development Company, L.P. | Field programmable gate array memory allocation |
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