CN101226481B

CN101226481B - Method, device and system for loading field programmable gate array

Info

Publication number: CN101226481B
Application number: CN2008100335508A
Authority: CN
Inventors: 董永强
Original assignee: Shanghai Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd; Shanghai Huawei Technologies Co Ltd
Priority date: 2008-02-02
Filing date: 2008-02-02
Publication date: 2011-05-18
Anticipated expiration: 2028-02-02
Also published as: CN101226481A

Abstract

The invention discloses a method for loading field programmable gate array, a relative device and a system, wherein the method comprises receiving data of preset bit width by an electric programmable logic device (EPLD), while the data bit width of the preset bit width being the biggest accessing port bit width supported by the CPU and the EPLD; and the bit width of the preset bit width being integral N times of the bit width of a data loading port of field programmable gate array (FPGA), dividing the received data of preset bit width into N data by the EPLD, wherein the bit width of each data is the bit width of the FPGA data loading port, loading the divided data into FPGA in integral N times; loading the divided data to the FPGA for integral N times by the FPLD. The invention reduces the access times of CPU on external devices when loads FPGA and reduces FPGA loading time.

Description

A kind of method of loading field programmable gate array, Apparatus and system

Technical field

The present invention relates to communication technical field, relate in particular to a kind of method, Apparatus and system of loading field programmable gate array.

Background technology

Wireless communication devices has requirement to the total system cold start-up time usually, FPGA (Field-Programmable Gate Array on the common veneer, field programmable gate array) the code file size has more than several megabits, the FPGA code when single board starting by CPU (Central Processing Unit, central processing unit) is loaded into FPGA, the time that loads is according to CPU load port speed, and FPGA scale difference, generally need several seconds to tens seconds long time, can become the veneer bottom software critical bottleneck of start-up time during this period of time.

In the prior art, the loading of FPGA can be referring to Fig. 1, FPGA loading interface signal comprises data, clock, control signal, these signals are by EPLD (Electrically Programmable Logic Device, the electrically programmable logical device) provides, CPU operates loading data, clock, the control signal register of controlling among the EPLD by 8 Asynchronous communications ports, realizes the input collection and output simulation of load signal.

In research and practice process to prior art, the inventor finds that there is following problem at least in prior art: byte of every loading, needing to visit peripheral hardware at least for CPU3 time just can finish, peripheral hardware of CPU visit simultaneously need consume at least two bus cycles, and peripheral bus speed is generally 50MHz or 100MHz, therefore loading velocity is slow, and the time consuming time is long.For example, CPU loads the file of a byte to FPGA, at first CPU will write a load document byte to EPLD loading data register, EPLD sends this byte to the FPGA load port, CPU writes one time 0 to loading clock register then, writes one time 1 again, and EPLD just can provide one and load rising edge clock like this, therefore simulating a rising edge clock need operate twice, one byte of EPLD register and just be loaded into FPGA.

Summary of the invention

The technical matters that the embodiment of the invention will solve provides a kind of method, Apparatus and system of loading field programmable gate array, can improve the speed that loads when loading the FPGA code.

For solving the problems of the technologies described above, the embodiment of the invention is achieved through the following technical solutions:

The embodiment of the invention provides a kind of method of loading field programmable gate array on the one hand, comprising:

Electrically programmable logical device EPLD receives the data of default bit wide, and this default bit wide is the maximum access port bit wide of being supported between CPU and the EPLD; The data bit width of described default bit wide be on-site programmable gate array FPGA data load port bit wide Integer N doubly;

The data of the described default bit wide that EPLD will receive are divided into an Integer N data, and wherein the bit wide of each data is the bit wide of described FPGA data load port;

The inferior FPGA that is loaded into of data branch Integer N after EPLD will divide.

The embodiment of the invention also provides a kind of device of loading field programmable gate array on the other hand, comprising:

Receiving element is used to receive the data of presetting bit wide, and this default bit wide is the maximum access port bit wide of being supported between central processing unit CPU and this receiving element; The data bit width of described default bit wide be FPGA data load port bit wide Integer N doubly;

Division unit, the data that are used for the default bit wide that will receive are divided into an Integer N data, and wherein the bit wide of each data is the bit wide of FPGA data load port;

Loading unit is used for the inferior FPGA that is loaded into of the data branch Integer N after dividing.

The embodiment of the invention also provides a kind of system of loading field programmable gate array, comprising:

CPU (central processing unit) is used to send the data of presetting bit wide, and described default bit wide is handled the maximum access port bit wide of being supported between processing unit and the electrically programmable logical block for these central authorities; The data bit width of described default bit wide be FPGA data load port bit wide Integer N doubly;

The electrically programmable logical block, the data that are used to receive the data of the default bit wide that CPU (central processing unit) sends and will preset bit wide are divided into an Integer N data, with the inferior fpga logic unit that is loaded into of the data branch Integer N after the division;

The fpga logic unit is used to receive electrically programmable logical block loaded data.

Above technical scheme as can be seen, when CPU loads FPGA, the default Integer N that the bit wide of CPU visit FPGA data becomes FPGA data load port bit wide by FPGA data load port bit wide doubly, therefore the FPGA loading takies CPU visit peripheral hardware number of times and reduces to default Integer N/one, has shortened the time that loads FPGA.

Description of drawings

The FPGA loaded in parallel schematic diagram that Fig. 1 provides for prior art of the present invention;

The method flow diagram that Fig. 2 provides for the embodiment of the invention one;

The device synoptic diagram that Fig. 3 provides for the embodiment of the invention two;

The system schematic that Fig. 4 provides for the embodiment of the invention three.

Embodiment

The embodiment of the invention provides a kind of method, Apparatus and system of loading field programmable gate array, is used for the FPGA code is loaded into FPGA by CPU when single board starting process, improves the speed that loads FPGA, and avoids losing of loading data.

In order to make technical scheme of the present invention clearer, enumerate embodiment below and be elaborated:

Referring to Fig. 2, the method flow diagram for the embodiment of the invention one provides comprises:

S101:EPLD receives the data of default bit wide.In the present embodiment, should default bit wide be the maximum access port bit wide of being supported between CPU and the EPLD, and the Integer N that this default bit wide is a FPGA data load port bit wide doubly, for example the maximum access port bit wide of being supported between CPU and the EPLD is 16, FPGA data load port bit wide is 8, and then default bit wide is 16.

The data of the default bit wide that S102:EPLD will receive are divided into an Integer N data.Default bit wide be FPGA data load port bit wide Integer N doubly, the bit wide of dividing each data of back is bit wides of FPGA data load port.For example, EPLD is divided into the data of 16 bit wides of step S101 reception the data of 28 bit wides.

S103: the inferior FPGA that is loaded into of the data branch Integer N after will dividing.For example, EPLD before receiving the data of next 16 bit wides, EPLD with the data of 28 bit wides of step S102 gained at twice clock be loaded into FPGA.

In the present embodiment, in the interval of the double loading data of CPU, FPGA loads clock and is provided automatically by EPLD, in each clock period the data load after the division is arrived FPGA.

Embodiment one as can be seen because CPU is when loading FPGA, CPU has increased the bit wide of EPLD loading data operation registers, such as changing 16 visits into by original 8, the load time is reduced to 1/2nd like this; FPGA loads clock and is provided automatically by EPLD, has reduced the number of times that FPGA loads the CPU visit peripheral hardware that takies, reduce to 1 time by 3 times, so the load time is reduced to 1/3rd; And, in CPU writes the interval of loading data for twice, EPLD will load into FPGA to 16 Bit datas that last time, CPU brought, could guarantee like this that loading data is uncovered loses, the shortest time in the time interval of twice write data register of CPU needs CPU8 machine cycle at least, and EPLD finishes re-loaded rising edge clock and only needs 2 EPLD work clock cycles, therefore can avoid losing of loading data.

Referring to Fig. 3, the device synoptic diagram for the embodiment of the invention two provides comprises:

Receiving element 201 is used to receive the data of presetting bit wide, and this default bit wide is the maximum bit wide that 201 of receiving elements can receive data, and the Integer N that this data bit width of presetting bit wide is a FPGA data load port bit wide doubly.For example, the maximum bit wide that 201 of receiving elements can receive data is 16, and FPGA data load port bit wide is 8, and then default bit wide is 16.

Division unit 202, the data that are used for default bit wide that receiving element 201 is received are divided into an Integer N data, and wherein the bit wide of each data is the bit wide of FPAG loading data port.For example, EPLD is divided into the data of 16 bit wides of receiving element 201 receptions the data of 28 bit wides.

Loading unit 203 is used for the inferior FPGA that is loaded into of the data branch Integer N after division unit 202 divisions.For example, EPLD before receiving the data of next 16 bit wides, EPLD with the data of 28 bit wides of division unit 202 gained at twice clock be loaded into FPGA.

Wherein, described device also comprises:

Clock unit 204 is used to provide the clock that loads the data after division unit 202 is divided, and data after loading unit 203 will be divided in each clock period are loaded into FPGA.

Referring to Fig. 4, the system schematic for the embodiment of the invention three provides comprises: CPU (central processing unit) 301, electrically programmable logical block 302, fpga logic unit 303.

CPU (central processing unit) 301, be used to send the data of default bit wide, should default bit wide be the maximum access port bit wide of being supported between CPU (central processing unit) 301 and the electrically programmable logical block 302, and the Integer N that this default bit wide is fpga logic unit 303 loading data port bit wides doubly, for example the maximum access port bit wide of being supported between CPU (central processing unit) 301 and the electrically programmable logical block 302 is 16, fpga logic unit 303 loading data port bit wides are 8, and then default bit wide is 16.

Electrically programmable logical block 302 is used to receive the data of the default bit wide that CPU (central processing unit) 301 sends and the data of the default bit wide that will receive are divided into an Integer N data, with the inferior fpga logic unit 303 that is loaded into of the data branch Integer N after the division.

Fpga logic unit 303 is used to receive electrically programmable logical block 302 loaded data.

Wherein, described system also comprises:

Clock unit, be used to provide the clock of electrically programmable logical block loading data, data after electrically programmable logical block 302 will be divided in each clock period are loaded into FPGA, and this clock unit can integrate with described electrically programmable logical block 302.

In the present embodiment, the port bit wide between described CPU (central processing unit) 301 and the described electrically programmable logical block 302 is 16, and the bit wide of fpga logic unit 303 loading data ports is 8.

Above embodiment as can be seen, when CPU loads FPGA, CPU becomes default integer to FPGA data load operation registers and conducts interviews, and FPGA loads clock and is supplied with automatically by EPLD, and no longer realize by the clock register of CPU operation EPLD, therefore reduce the number of times of CPU visit peripheral hardware when loading FPGA, shortened the time that loads FPGA.

One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description method is to instruct relevant hardware to finish by program, this program can be stored in a kind of computer-readable recording medium.

The above-mentioned storage medium of mentioning can be a ROM (read-only memory), disk or CD etc.

More than method, the Apparatus and system of a kind of loading field programmable gate array provided by the present invention is described in detail, for one of ordinary skill in the art, thought according to the embodiment of the invention, part in specific embodiments and applications all can change, in sum, this description should not be construed as limitation of the present invention.

Claims

1. the method for a loading field programmable gate array is characterized in that, comprising:

2. method according to claim 1 is characterized in that, the data branch Integer N after described EPLD will divide is inferior to be loaded into FPGA, comprising:

The clock that EPLD provides according to self, data after will dividing in each clock period are loaded into FPGA.

3. according to the method shown in the claim 1, it is characterized in that described default bit wide is 16, described FPGA data load port bit wide is 8.

4. the device of a loading field programmable gate array is characterized in that, comprising:

Division unit, the data that are used for the described default bit wide that will receive are divided into an Integer N data, and wherein the bit wide of each data is the bit wide of described FPGA data load port;

Loading unit is used for the inferior FPGA that is loaded into of the described data branch Integer N after dividing.

5. device according to claim 4 is characterized in that, described device also comprises:

Clock unit is used to provide the clock that loads the data after described division unit is divided, and data after described loading unit will be divided in each clock period are loaded into FPGA.

6. the system of a loading field programmable gate array is characterized in that, comprising:

The electrically programmable logical block is used to receive the data of the default bit wide that described CPU (central processing unit) sends and data that will described default bit wide and is divided into an Integer N data, with the inferior fpga logic unit that is loaded into of the described data branch Integer N after the division;

The fpga logic unit is used to receive described electrically programmable logical block loaded data.

7. system according to claim 6 is characterized in that, described system also comprises:

Clock unit is provided by described electrically programmable logical block, is used to provide the clock of described electrically programmable logical block loading data, and data after described electrically programmable logical block will be divided in each clock period are loaded into FPGA.

8. system according to claim 6 is characterized in that, the port bit wide between described CPU (central processing unit) and the described electrically programmable logical block is 16, and the bit wide of described fpga logic cell data load port is 8.