CN103780250B - Change speed gear box circuit and the method for work thereof of data bit width is changed in high-speed transceiver - Google Patents
Change speed gear box circuit and the method for work thereof of data bit width is changed in high-speed transceiver Download PDFInfo
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Abstract
The present invention relates to a kind of change speed gear box circuit changing data bit width in high-speed transceiver and method of work thereof, by controlling the generation of input the used clock of data and output the used clock of data, and the phase relation between two clocks, control the conversion between different pieces of information bit wide, thus realize the data bit width coupling between each internal module.Described change speed gear box circuit includes: enumerator generative circuit, clock generation circuit, the first data width change-over circuit, the second data width change-over circuit, the output of described enumerator generative circuit connects clock generation circuit, the input of clock generation circuit connects clock source, and the output of clock generation circuit connects the first data width change-over circuit and the second data width change-over circuit.The invention have the advantage that and lead not affecting data transmission ratio spy, in the case of not reducing data transmission efficiency, arbitrarily carry out the conversion of data bit width, and the method for designing of the change speed gear box circuit be applicable to any chip designs and circuit.
Description
Technical field
The present invention relates to realize circuit and the method that data bit width arbitrarily changes, especially a kind of in high-speed transceiver
Change change speed gear box circuit and the method for work thereof of data bit width.
Background technology
Along with serial communication speed develops to 10Gbps even 100Gbps, traditional inefficient encoding and decoding such as 8b/10b, by
It is up to the bandwidth waste rate of 20% in it, as continued to use such coded system in High Speed System, will greatly waste channel
Bandwidth, reduce data efficiency of transmission.Therefore some high efficiency coded systems such as 64B/66B, 64B/67B etc. are more conventional
Occur in the design of current High Speed System.But present digital system bus bit wide is the most all n time of 1,2,4,8 grades 2
Square cards for learning characters save, such as in the physical layer standard of ten thousand mbit ethernet 10G-WIS, the data sended over from upper-layer protocol firstly the need of
Through the coding of 64B/66B, then enter back into and the PCS of 10G-WIS standard carries out data process.But the PCS of 10G-WIS defines
Data bit width be 64, in order to be able to allow the data after 64B/66B encodes can process in the PCS of 10G-WIS,
Need exist for a module and 66 bits are changed into 64 bits.The most such as in 10GBase-R agreement, after 64B/66B encodes
Data before being sent to Serdes, bit width conversion to be carried out, because the physical layer transceiver at 10GBase-R sets
During meter, the bit wide number of the parallel end data input of Serdes will not be typically 66 bits, and general no more than 20, as
8,10,16 etc..Situation described in summary, in order to solve such problem, it is desirable to provide a kind of easy, low cost
, the method that arbitrary data bit wide reduces can be realized, the seamless link between each module and normal data in ensureing chip
Transfer function.
If directly according to the principle that the data output of change speed gear box both sides and the data transfer rate of input are equal, utilizing two frequencies
Clock data bit width is directly changed, and not to both sides clock, or data carry out any control or process, then
When the clock frequency of change speed gear box data output is more than the clock frequency of change speed gear box data input, i.e. export the clock week used by data
When phase is less than the width of input data, in data bit width transformation process, under certain clock cycle, the clock meeting of output data
By the data sampling under current period 2 times, thus cause the repetition of output data.When the clock frequency of change speed gear box data output is little
When the clock frequency of change speed gear box data input, i.e. output clock cycle used by data are more than the width of input data, counting
During bit width conversion, under certain clock cycle, the clock of output data can leak the data adopted under current period, thus shadow
Ring the correctness of data transmission.
The method in the past having inputs data by suspending in certain clock cycle to change speed gear box, but does not stop the number of change speed gear box
According to output.As 66 bits turn 64 bits, within 33 clock cycle, export 64 bits, conveying within 32 clock cycle is come in
66 Bit datas complete bit width conversion.The method realizing data bit width conversion by this method using the clock cycle,
The efficiency of system data transmission, the situation that especially gap is bigger between input data bit width and outputs data bits width can be reduced
Under, the overall performance of system has decline greatly.This method can only be suitable in FPGA design, because FPGA user can
Oneself to design control logic.And in general ASIC or SOC design, this side significantly reducing system transfers efficiency
Method can not meet system requirements.
Summary of the invention
It is an object of the invention to lead not changing data transmission ratio spy, in the case of not affecting systematic entirety energy, overcome
The problems referred to above, it is provided that a kind of change speed gear box circuit changing data bit width and method of work thereof, can need not halt input number
According to, do not reduce the data transmission efficiency of whole system, and under conditions of keeping data input and output to be carried out continuously, carry out data
The conversion of bit wide.
The described change speed gear box circuit changing data bit width in high-speed transceiver includes: enumerator generative circuit, time
Clock produces circuit, the first data width change-over circuit, the second data width change-over circuit, the output of described enumerator generative circuit
Connecting clock generation circuit, the input of clock generation circuit connects clock source, and the output of clock generation circuit connects the first data
Width change-over circuit and the second data width change-over circuit；
Described enumerator generative circuit, is used for controlling the whole process of bit width conversion, including the first enumerator and the second meter
Number device, the count value of the first enumerator and the second enumerator is all to be determined by the bit wide value of input data and output data；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is more than change speed gear box, the first counter controls
The length in each cycle of input clock and the situation of output data displacement after restructuring, the value of the second enumerator controls to input
The situation of data displacement；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is less than change speed gear box, the first counter controls
Exporting length and the situation of output data displacement in each cycle of clock after restructuring, the value of the second enumerator controls to input
The situation of data displacement；
When reset signal is effective, the value of the first enumerator and the second enumerator is complete zero；
The count range of the first enumerator is 0 to i, and the count range of the second enumerator is 0 to j+k-1；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is more than this change speed gear box, this change speed gear box clock
The period definition in source is T, and the clock generation circuit in change speed gear box can generate the clock of two kinds of different cycles, and their value is respectively
T1And T2, T1<Ta<T2, T1=i*T, T2=(i+1)*T；
T1, T2With the clock cycle T used by input dataaWith the clock cycle T used by output databRelation be: Ta=
(j*T1+k*T2)/(j+k), j and k is positive integer, Tb=T；
The count range of the first enumerator, after j time from 0 to the counting of i-1, carries out k time 0 counting to i, the most again
Re-start j the counting from 0 to i-1, then carry out k time 0 counting to i, and repeat this counting process always；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is less than this change speed gear box；This change speed gear box clock
The period definition in source is T, and the clock generation circuit in change speed gear box can generate the clock of two kinds of different cycles, and their value is respectively
T1And T2, T1<Tb<T2, T1=i*T, T2=(i+1)*T；
T1, T2With the clock cycle T used by input dataaWith the clock cycle T used by output databRelation be: Tb=
(j*T1+k*T2)/(j+k), j and k is positive integer, Ta=T；”
The count range of the first enumerator, after k time from 0 to the counting of i, carries out j time 0 counting to i-1, the most again
Re-start k the counting from 0 to i, then carry out j time 0 counting to i-1, and repeat this counting process always；
First enumerator starts once the counting from 0 to i-1 or the counting from 0 to i, and the second enumerator adds 1；
Described clock generation circuit, inputs and output clock in order to produce the data of change speed gear box circuit；Raw according to enumerator
Become the value of circuit, input clock source divided, produce the data input clock required for change speed gear box and data output clock,
When the value of the first enumerator is 0, the restructuring clock of generation is high level, when the value of the first enumerator is (i-1)/2, produces
Restructuring clock become low level；When bit wide n of the output data that bit wide m of the input data of change speed gear box is more than change speed gear box,
Described clock generation circuit produces data input clock；When bit wide m of the input data of change speed gear box is less than the output number of change speed gear box
According to bit wide n time, described clock generation circuit produce data output clock；
Described first data width change-over circuit, in order to carry out reducing the conversion of data width under identical bit rate,
Bit wide m of the first data width change-over circuit input data is more than bit wide n of output data；Before carrying out bit width conversion, right
Multicycle time delay is carried out under the clock that the data that the m Bit data of input produces at change speed gear box clock source input；First data width
In degree change-over circuit, the size of buffer is j* (m-i*n)+m, for input data are carried out temporary transient storage；First data width
During degree change-over circuit work:
1.1, the value of the first enumerator determines the transformation of change speed gear box data, and when the first enumerator starts counting up, input is new
M Bit data enter buffer, the data that last cycle shift retains are 0 as low level, the count range at the first enumerator
During to i-1, moving to right i n-bit data of output, the data now retained are displaced to the lowest order of buffer, when the first enumerator
Count range when being 0 to i, move to right i+1 n-bit data of output, experienced by the counting 0 of k time to after i, the bit of reservation
Number is 0, next repeats this section of operation；
1.2, the value of the second enumerator determines the data of the new m bit inputted position in buffer and upper cycle
Accumulation bit number, the bit number of accumulation of upper cycle is always as low level, and the data of newly inputted m bit are as a high position, buffer
Remaining higher bit zero padding, the count range of the second enumerator is when 0 to j-1, and the second enumerator often adds 1, the bit of accumulation
Number increases m-i*n, and when the count range of the second enumerator is at j to j+k-1, the second enumerator often adds 1, and the bit number of accumulation subtracts
Few n, when the value of the second enumerator is j+k-1, the bit number of accumulation is zero, now completes inputting data into of j+k m bit
(i+1) conversion of k+i*j n-bit output data of *；
Described second data width change-over circuit, in order to carry out increasing the conversion of data width under identical bit rate,
Bit wide m of the second data width change-over circuit input data is less than bit wide n of output data；Before carrying out bit width conversion, right
Multicycle time delay is carried out under the clock that the data that the m Bit data of input produces at change speed gear box clock source input；Second data width
In degree change-over circuit, the size of buffer is j*i*m, for input data are carried out temporary transient storage；Second data width conversion
During circuit work:
2.1, the value of the first enumerator determines the transformation of change speed gear box data, when the first enumerator starts to count from 0 to i,
Inputting i+1 new m Bit data and enter buffer, when the value of the first enumerator is i, buffer moves to right the number of output n-bit
According to, the data now retained are displaced to the lowest order of buffer, and when the count range of the first enumerator is 0 to i-1, input is new
I m Bit data enter buffer, when the value of the first enumerator is i-1, buffer move to right output n-bit data, at warp
Having gone through the count range of k time is 0 to i and after the count range of j time is 0 to i-1, and the bit number of reservation is 0, next repeats this
Section operation；
2.2, the value of the second enumerator determines the data of the new m bit inputted position in buffer and upper cycle
Accumulation bit number, the bit number of accumulation of upper cycle is always as low level, and the data of newly inputted m bit are made successively by input sequence
For a high position, remaining higher bit zero padding of buffer, when the value of the second enumerator is 0, the bit number of accumulation is (i+1) * m-
N, when the value of the second enumerator is j+k-1, the bit number of accumulation is zero, now completes the input of k+i*j m bit of (i+1) *
The conversion of data to j+k n-bit output data.
Data input clock or each clock cycle of data output clock that described clock generation circuit produces are the completeest
Complete consistent.
The described change speed gear box circuit method of work changing data bit width in high-speed transceiver, including data bit width by
The method of multidirectional few conversion and data bit width are by few method to many conversions；
Described data bit width is referred to the bit wide m output more than change speed gear box of the input data of change speed gear box by multidirectional few conversion
Bit wide n of data, and realize data bit width and by the conversion to n position of the m position, described data bit width by the method for multidirectional few conversion be:
3.1, input clock and the output clock of change speed gear box is synchronised clock, for producing the input clock of change speed gear box and defeated
The frequency of the clock source going out clock exports the clock frequency of clock more than or equal to change speed gear box；
3.2, each clock cycle of the input clock A that this change speed gear box clock source produces is not essentially equal, average period
It is Ta；At the input of data, each clock cycle input m Bit data；
3.3, each clock cycle of the output clock B that this change speed gear box clock source produces is essentially equal, and the clock cycle is Tb；
At the outfan of data, each clock cycle output n-bit data；
3.4, the period definition of this change speed gear box clock source is T, and the clock generation circuit in change speed gear box can generate two kinds of differences
The clock T in cycle1And T2, T1<Ta<T2, T1=i*T, T2=(i+1)*T；
3.5、T1, T2With the clock cycle T used by input dataaWith the clock cycle T used by output databRelation be:
Ta=(j*T1+k*T2)/(j+k), Tb=T；
3.6, each cycle is T1Or the cycle is T2Clock cycle, the data all inputting m bit enter change speed gear box；
3.7, each cycle is T1Clock cycle, all export the data of i n-bit, be T in the cycle2Clock cycle,
The data of output (i+1) * n-bit；
3.8, at first T1Clock cycle, the data of m bit enter change speed gear box, and the data of i*n bit are output, reservation
Bit number is m-i*n；
3.9, by that analogy, in jth T1Clock cycle, the data of m bit enter change speed gear box, and the data of i*n bit are defeated
Going out, the bit number of reservation is j* (m-i*n)；
3.10, at first T2Clock cycle, is also jth+1 the input restructuring clock cycle, and the data of m bit enter speed change
Case, the data of (i+1) * n-bit are output, and the bit number of reservation is (j+1) * (m-i*n)-n；
3.11, by that analogy, in kth T2Clock cycle, is also jth+k input restructuring clock cycle, the number of m bit
According to entering change speed gear box, the data of (i+1) * n-bit are output, and the bit number of reservation is (j+k) * (m-i*n)-k*n=0；
3.12, in the clock cycle of jth+k input data, complete j+k m bit inputs data into (i+1) * k+i*
The conversion of j n-bit output data；
3.13, the step of 3.8 to 3.12 is restarted；
Described data bit width is less than the output of change speed gear box by bit wide m of few input data referring to change speed gear box to many conversions
Bit wide n of data, and realize data bit width and by the conversion to n position of the m position, described data bit width by few methods to many conversions be:
4.1, input clock and the output clock of change speed gear box is synchronised clock, for producing the output clock of change speed gear box and defeated
The frequency of the clock source entering clock is more than or equal to the clock frequency of change speed gear box input clock；
4.2, each clock cycle of the output clock B that change speed gear box clock source produces is not essentially equal, but necessarily
Clock periodicity under, average period is Tb；At the outfan of data, each clock cycle output n-bit data；
4.3, each clock cycle of the input clock A that change speed gear box clock source produces is essentially equal, and the clock cycle is Ta；?
The input of data, each clock cycle input m Bit data；
4.4, the period definition of change speed gear box clock source is T, and the clock generation circuit in change speed gear box can generate two kinds of different weeks
The clock of phase, their value is respectively T1And T2, T1<Tb<T2, T1=i*T, T2=(i+1)*T；
4.5、T1, T2With the clock cycle T used by input dataaWith the clock cycle T used by output databRelation be:
Tb=(j*T1+k*T2)/(j+k), Ta=T；
4.6, each cycle is T1Or the cycle is T2Clock cycle, all from the data of change speed gear box output n-bit；
4.7, each cycle is T1Clock cycle, the data all inputting i m bit enter change speed gear box, are T in the cycle2Time
In the clock cycle, the data of input (i+1) * m bit enter change speed gear box；
4.8, at first T2Clock cycle, the data of (i+1) * m bit enter change speed gear box, and the data of n-bit are output, and protect
The bit number stayed is (i+1) * m-n；
4.9, at first T1Clock cycle, the data of i*m bit enter change speed gear box, and the data of n-bit are output, reservation
Bit number is (2i+1) * m-2n；
4.10, by that analogy, in jth T1Clock cycle, is also kth+j input restructuring clock cycle, i*m bit
Data enter change speed gear box, and the data of n-bit are output, and the bit number of reservation is k* ((i+1) m-n)-j* (n-i*m)=0；
4.11, in the clock cycle of kth+j input data, complete k+i*j m bit of (i+1) * inputs data into k+
The conversion of j n-bit output data；
4.12, the step of 4.8 to 4.11 is restarted.
Described m, n, i, j, k are positive integer.
The invention have the advantage that present invention achieves one does not change data transmission ratio spy and lead and can arbitrarily change data bit
Wide Gearbox design, can need not halt input data, not reduce the data transmission efficiency of whole system, and keep number
Under conditions of being carried out continuously according to input and output, carry out any type of data bit width conversion.
Accompanying drawing explanation
Fig. 1 is the change speed gear box circuit structure diagram of the present invention.
Fig. 2 be the present invention change speed gear box circuit in clock source produce input clock schematic diagram.
Fig. 3 be the present invention change speed gear box in reduce the schematic diagram of transition process of data bit width.
Fig. 4 be the present invention change speed gear box circuit in clock source produce output clock schematic diagram.
Fig. 5 be the present invention change speed gear box in increase the transition process schematic diagram of data bit width.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is further elaborated.According to change speed gear box two in the present invention
The end stable principle of bit rate, further according to input data and the bit wide relation of output data, utilizes a high-speed clock source, obtains
Two synchronised clocks control input and the output of change speed gear box data.The method need not to input data carry out any process or
Person controls, and can carry out continuous data transmission and change data bit width.Can protect in the case of need not halt input data
Hold input and under conditions of output is carried out continuously, carry out data bit width by multidirectional few conversion or by few to many transformations.Speed change
Case circuit structure as it is shown in figure 1, include enumerator generative circuit, clock generation circuit, the first data width change-over circuit, second
Data width change-over circuit, the output of described enumerator generative circuit connects clock generation circuit, the input of clock generation circuit
Connecting clock source, the output of clock generation circuit connects the first data width change-over circuit and the second data width change-over circuit.
The method for designing of this change speed gear box mainly includes that clock produces and data bit width conversion two parts.
The frequency of this change speed gear box input clock A used by data is a, and the bit wide of data is m bit, the bit of input data
Rate is r1=a*m.The frequency of this change speed gear box output clock B used by data is b, and the bit wide of data is n-bit, exports data
Bit rate be r2=b*n.The bit rate phase of the bit rate of the input data of this change speed gear box and the output data of this change speed gear box
Deng, i.e. r1=r2.This change speed gear box carry out data bit width by m position to n position change during, do not have at any one
Data have the loss of arbitrary Bit data, change, or in any one data, has the situation that new bit increases.
The input clock of this change speed gear box and output clock are all produced by same clock source, thus ensure that the two clock is
Synchronised clock；Frequency for the clock source of the input clock and output clock that produce this change speed gear box have to be larger than or equal to becoming
The clock frequency of speed case output clock.
There are two kinds of situation: m > n and m in bit wide m of the input data of change speed gear box with bit wide n of the output data of this change speed gear box
< next n is described separately.
When bit wide m of the input data of change speed gear box is more than bit wide n of the output data of this change speed gear box:
1), each clock cycle of input clock A of producing of this change speed gear box clock source be not essentially equal, but necessarily
Clock periodicity under, average period is Ta.At the input of data, each clock cycle input m Bit data；
2), each clock cycle of output clock B of producing of this change speed gear box clock source essentially equal, the clock cycle is Tb。
At the outfan of data, each clock cycle output n-bit data；
3), the period definition of this change speed gear box clock source be T, the clock generation circuit in change speed gear box can generate two kinds of different weeks
The clock of phase, their value is respectively T1And T2, T1<Ta<T2, T1=i*T, T2=(i+1)*T；
4)、T1, T2With the clock cycle T used by input dataaWith the clock cycle T used by output databRelation be: Ta
=(j*T1+k*T2)/(j+k), j and k is positive integer, Tb=T；
5), each cycle is T1Or the cycle is T2Clock cycle, the data all inputting m bit enter change speed gear box；
6), each cycle is T1Clock cycle, all export the data of i n-bit, be T in the cycle2Clock cycle, defeated
Go out the data of (i+1) * n-bit；
7), at first T1Clock cycle, the data of m bit enter change speed gear box, and the data of i*n bit are output, reservation
Bit number is m-i*n；
8), by that analogy, in jth T1Clock cycle, the data of m bit enter change speed gear box, and the data of i*n bit are defeated
Going out, the bit number of reservation is j* (m-i*n)；
9), at first T2Clock cycle, is also that (j+1) individual input is recombinated the clock cycle, and the data of m bit enter speed change
Case, the data of (i+1) * n-bit are output, and the bit number of reservation is (j+1) * (m-i*n)-n；
10), by that analogy, in kth T2Clock cycle, is also that (j+k) individual input is recombinated the clock cycle, m bit
Data enter change speed gear box, and the data of (i+1) * n-bit are output, and the bit number of reservation is (j+k) * (m-i*n)-k*n=0；
11), in the clock cycle of (j+k) individual input data, complete (j+k) individual m bit inputs data into ((i+1) *
K+i*j) conversion of individual n-bit output data；
Then the step of 7 to 11 is restarted.
When bit wide m of the input data of change speed gear box is less than bit wide n of the output data of this change speed gear box:
1), each clock cycle of output clock B of producing of this change speed gear box clock source be not essentially equal, but necessarily
Clock periodicity under, average period is Tb.At the outfan of data, each clock cycle output n-bit data；
2), each clock cycle of input clock A of producing of this change speed gear box clock source essentially equal, the clock cycle is Ta。
At the input of data, each clock cycle input m Bit data；
3), the period definition of this change speed gear box clock source be T, the clock generation circuit in change speed gear box can generate two kinds of different weeks
The clock of phase, their value is respectively T1And T2, T1<Tb<T2, T1=i*T, T2=(i+1)*T；
4), T1, T2With the clock cycle T used by input dataaWith the clock cycle T used by output databRelation be: Tb
=(j*T1+k*T2)/(j+k), j and k is positive integer, Ta=T；
5), each cycle is T1Or the cycle is T2Clock cycle, all from the data of change speed gear box output n-bit；
6), each cycle is T1Clock cycle, the data all inputting i m bit enter change speed gear box, are T in the cycle2Time
In the clock cycle, the data of input (i+1) * m bit enter change speed gear box；
7), at first T2Clock cycle, the data of (i+1) * m bit enter change speed gear box, and the data of n-bit are output, and protect
The bit number stayed is (i+1) * m-n；
8), at first T1Clock cycle, the data of i*m bit enter change speed gear box, and the data of n-bit are output, reservation
Bit number is (2i+1) * m-2*n；
9), by that analogy, in jth T1Clock cycle, is also that (k+j) individual input is recombinated the clock cycle, i*m bit
Data enter change speed gear box, and the data of n-bit are output, and the bit number of reservation is k* ((i+1) m-n)-j* (n-i*m)=0；
10), in the clock cycle of (k+j) individual input data, the input data of ((i+1) * k+i*j) individual m bit are completed
Conversion to (k+j) individual n-bit output data；
Then the step of 7 to 10 is restarted.
The change speed gear box circuit of described change data bit width includes four parts: the first data width change-over circuit；Second number
According to width change-over circuit；Enumerator generative circuit；Clock generation circuit.
Described enumerator generative circuit, is used for controlling the whole process of bit width conversion, and its structure is:
Enumerator generative circuit two enumerators of generation: the first enumerator and the second enumerator；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is more than this change speed gear box, the first enumerator control
The situation that after system restructuring, the length in each cycle of input clock shifts with output data, the value of the second enumerator controls defeated
Enter the situation of data displacement；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is less than this change speed gear box, the first enumerator control
Exporting length and the situation of output data displacement in each cycle of clock after system restructuring, the value of the second enumerator controls defeated
Enter the situation of data displacement；
The count value of the first enumerator and the second enumerator is all to be determined by the bit wide value of input data and output data；
When reset signal is effective, the value of this first enumerator and the second enumerator is complete zero；
The count range of the first enumerator is 0 to i, and the count range of the second enumerator is 0 to j+k-1；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is more than this change speed gear box, the first enumerator
Count range, after j time from 0 to the counting of i-1, carries out k time 0 arriving the counting of i, re-starts j time the most again from 0 to i-1's
Counting, then carry out k time 0 counting to i, and repeat this counting process always；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is less than this change speed gear box, the first enumerator
Count range, after k time from 0 to the counting of i, carries out j time 0 arriving the counting of (i-1), re-starts k time the most again from 0 to i's
Counting, then carry out j time 0 counting to (i-1), and repeat this counting process always；
The count range 0 of j time of the first enumerator arrives i to the count range 0 of i-1 and k time, carries out general interlocking；
First enumerator starts once the counting from 0 to i-1 or the counting from 0 to i, and the second enumerator adds one.
Described clock generation circuit, in order to produce the data input clock of change speed gear box circuit, its structure is:
When bit wide n of the output data that bit wide m of the input data of change speed gear box is more than this change speed gear box, this clock produces electricity
Road produces the clock that data input needs；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is less than this change speed gear box, this clock produces electricity
Road produces the clock that data output needs；
Data input clock or each clock cycle of data output clock that this clock forming circuit produces are incomplete
Unanimously；
According to the value of enumerator generative circuit, dividing input clock source, the data required for generation change speed gear box are defeated
Entering clock and data output clock, when the value of the first enumerator is 0, the restructuring clock of generation is high level, at the first counting
The value of device is (i-1)/2, becomes low level.
Described first data width change-over circuit, in order to carry out reducing the conversion of data width under identical bit rate,
Its structure is:
The bit wide of data width change-over circuit input data is m, and the bit wide of output data is n, and m > n；
Before carrying out bit width conversion, to the m Bit data inputted when the data input that change speed gear box clock source produces
Multicycle time delay is carried out under clock；
In data width change-over circuit, the size of buffer is j* (m-i*n)+m, typically makes T1And T2Cycle is alternately produced defeated
Enter clock, to reduce the size of buffer；
The value of the first enumerator determines the transformation of change speed gear box data, when the first enumerator starts counting up, inputs new m ratio
Special data enter buffer, and the data that last cycle shift retains are as low level, and the count range at the first enumerator is 0 to (i-
1), time, buffer moves to right i n-bit data of output successively, and the Bit data remained is displaced to the lowest order of buffer；
When the first enumerator starts counting up, the data that last cycle shift retains are as low level, newly inputted m bit number
According to entering buffer as a high position, when the count range at the first enumerator is 0 to i, buffer moves to right output (i+1) individual n successively
Bit data, the Bit data remained is displaced to the lowest order of buffer；
Experienced by after the count range of k time is 0 to i at the first enumerator, the bit number of reservation is 0；
The value of the second enumerator determines the data of the new m bit of input position in buffer and the accumulation of upper cycle
Bit number, the bit number of accumulation of upper cycle always as low level, the data of newly inputted m bit as a high position, buffer remaining
Higher bit zero padding；
The value of the second enumerator determines that the count range of the first enumerator is 0 to (i-1) or 0 to i, also correspond to not
With length cycles T1And T2Distribution situation.
With j T1With k T2As a example by being arranged in order, the count range of the second enumerator 0 to (j-1) time, the second enumerator
Often adding one, the bit number of accumulation increases (m-i*n), when the count range of the second enumerator is at j to (j+k-1), and the second counting
Device often adds one, and the bit number of accumulation reduces n, and when the value of the second enumerator is (j+k-1), the bit number of accumulation is zero, now
Complete the conversion inputting data into ((i+1) * k+i*j) individual n-bit output data of (j+k) individual m bit.
Described second data width change-over circuit, in order to carry out increasing the conversion of data width under identical bit rate,
Its structure is:
The bit wide of data width change-over circuit input data is m, and the bit wide of output data is n, and m < n；
Before carrying out bit width conversion, the m Bit data of input is carried out the multicycle under change speed gear box clock source clock and prolongs
Time；
In data width change-over circuit, the size of buffer is j*i*m, can make T1And T2Cycle is alternately produced output clock,
To reduce the size of buffer；
The value of the first enumerator determines the transformation of change speed gear box data, when the first enumerator starts to count from 0 to i, and input
New (i+1) individual m Bit data enters buffer, and the data that last cycle shift retains are as low level, in the value of the first enumerator
During for i, buffer moves to right the data of output n-bit, and the data now retained are displaced to the lowest order of buffer,
When the count range of the first enumerator be 0 to (i-1) time, last cycle shift retain data as low level, defeated
Entering i new m Bit data and enter buffer as a high position, when the value of the first enumerator is (i-1), buffer moves to right output n
The data of bit, the Bit data remained is displaced to the lowest order of buffer；
Experienced by the count range of j time at the first enumerator is 0 to after (i-1), and the bit number of reservation is 0；
The value of the second enumerator determines the data of the new m bit of input position in buffer and the accumulation of upper cycle
Bit number, the bit number of accumulation of upper cycle is always as low level, and the data of newly inputted m bit press input sequence successively as high
Position, remaining higher bit zero padding of buffer,
The value of the second enumerator determines that the count range of the first enumerator is 0 to (i-1) or 0 to i, also correspond to not
With length cycles T1And T2Distribution situation.
With k T2With j T1As a example by being arranged in order, the count range of the second enumerator 0 to (k-1) time, the second enumerator
Often adding one, the bit number of accumulation increases ((i+1) * m-n), when the count range of the second enumerator is at j to (j+k-1), and second
Enumerator often adds one, and the bit number of accumulation reduces n-m, and when the value of the second enumerator is (j+k-1), the bit number of accumulation is
Zero, now complete the conversion inputting data into (j+k) individual n-bit output data of ((i+1) * k+i*j) individual m bit.
The following is a specific embodiment.
As a example by 10GBASE-R physical layer, using the code encoding/decoding mode of 64B/66B, its data baud rate is
, in change speed gear box, there is the conversion between 66 bits to 8 bits, two kinds of bit wides of 8 bits to 66 bit in 10.3125Gbps.
One, change speed gear box circuit carries out data bit width by multidirectional few conversion, and bit wide m wherein inputting data is 66 bits,
Bit wide n of output data is 8 bits；
In the present invention, the input data rate of change speed gear box is equal with output data rate, then the input data of change speed gear box
Clock frequency a=1/ (66T)=156.25MHz used, output clock frequency b=1/ (8T)=1.289GHz used by data, its
Middle T is expressed as the cycle of each Bit data transmission, T=0.09697ns.
In the present invention, the period definition of change speed gear box clock source is 8T, and this 8T clock is produced by PLL built-in for Serdes,
Then the clock cycle of change speed gear box input data is 66T, and the clock cycle of change speed gear box output data is 8T.
Enumerator cnt9 and the determination of cnt4 count range:
The situation that after enumerator cnt9 control restructuring, the length in each cycle of clock shifts with output data, enumerator
The value of cnt4 controls to input the situation of data displacement；
In the present invention, the period definition of change speed gear box clock source is 8T, then 66 Bit datas inputted, in the 8T clock cycle
Under, shift 8 times, the data of 88 bits of output, retain the data of 2 bits, after 66 Bit datas in 4 cycles of input, protect
The data stayed are 8 bits, then, under the 4th input cycle, output needs to shift 9 times, and guarantee does not has loss of data, then
The count range of enumerator cnt9 is 0-8；
For input clock, there is the periodic quantity of two different lengths: 8*8T=64T and 9*8T=72T, according to
((64T) * x+ (72T) * y)/(x+y)=66T, calculates x/y=3/1；Namely the clock cycle of 4 66T can be reassembled as
{ 8*8T, 8*8T, 8*8T, 9*8T}, as in figure 2 it is shown, the count range of enumerator cnt4 is 0-3；
When the value of enumerator cnt9 is 0, the value of enumerator cnt4 adds one；When the value of enumerator cnt4 is 3, enumerator
The count range of cnt9 is 0-8, and when the value of enumerator cnt4 is other values, the count range of enumerator cnt9 is 0-7；
Need 33 8T clock cycle, just can complete the restructuring of 4 66T cycle clocks, obtained input clock cycle
Though unequal, the meansigma methods in its cycle is equal with 66T:
1, in the clock cycle of the 1st 8T, the value of enumerator cnt9 is 0, and the value of enumerator cnt4 is 0；
2, in the clock cycle of the 2nd 8T, the value of enumerator cnt9 adds one and becomes 1；
3, by that analogy to the clock cycle of the 8th 8T, the value of enumerator cnt9 is accumulated as 7；
4, when the value of enumerator cnt4 is 0, in the clock cycle of the 9th 8T, the value of enumerator cnt9 reverts to 0, this
The value of hour counter cnt4 adds one and becomes 1；
5, in the clock cycle of the 10th 8T, the value of enumerator cnt9 becomes 1 after adding one；
6, by that analogy to the clock cycle of the 16th 8T, the value of enumerator cnt9 is added to 7；
7, when the value of enumerator cnt4 is 1, in the clock cycle of the 17th 8T, the value of enumerator cnt9 reverts to 0, this
The value of hour counter cnt4 adds one and becomes 2；
8, in the clock cycle of the 18th 8T, the value of enumerator cnt9 becomes 1 after adding one；
9, by that analogy to the clock cycle of the 24th 8T, the value of enumerator cnt9 is added to 7；
10, when the value of enumerator cnt4 is 2, in the clock cycle of the 25th 8T, enumerator cnt9 reverts to 0, now
The value of enumerator cnt4 adds one and becomes 3；
11, in the clock cycle of the 26th 8T, the value of enumerator cnt9 becomes 1 after adding one；
12, by that analogy to the clock cycle of the 32nd 8T, the value of enumerator cnt9 is added to 7；
13, when the value of enumerator cnt4 is 3, in the clock cycle of the 33rd 8T, the value of enumerator cnt9 becomes after adding one
It is 8；
14, in the clock cycle of the 34th T8, enumerator cnt9 reverts to 0, and the value of this hour counter cnt4 adds one and becomes
0, repeat 5 operations；
15, the value according to cnt9 can obtain the clock of 66T: when the value of cnt9 is 0, clock is low level, at cnt9
Value when being 4, clock is reversed to high level.
16, when, after the restructuring clock completing 4 66T cycles, repeating 1 to 13 operations and constantly produce input clock.
Needing through 33 8T clock cycle, 66 bits that just can complete 4 restructuring clock cycle input data into 33 8
The conversion of Bit data, as shown in Figure 3:
1, before carrying out bit width conversion, 66 Bit datas inputted are inputted in the data that change speed gear box clock source produces
Multicycle time delay is carried out under restructuring clock；
2, each 8*8T clock cycle or the 9*8T clock cycle, the data all inputting 64 bits enter change speed gear box, each
The individual 8*8T clock cycle, all export the data of 88 bits；
3, when the value of enumerator cnt4 is 0, the count range of enumerator cnt9 is 0-7, and the data of 66 bits enter speed change
The buffer of 72 bits of case, the high 6 bit zero paddings of buffer, when the value of enumerator cnt9 is 0, the value of buffer presses 8T clock week
Phase moves to right the output as data of 8 bits, when the value of enumerator cnt9 is 7, and last 8 Bit data removals, 2 bits of accumulation
Data as displacement posterior bumper minimum 2 waits enter into enumerator cnt9 next round counting；
4, when the value of enumerator cnt4 is 1, the count range of enumerator cnt9 is 0-7, and the data of 66 bits enter speed change
The buffer of 72 bits of case, the high 4 bit zero paddings of buffer, when enumerator cnt9 is 0, the value of buffer presses the 8T clock cycle
Move to right the output as data of 8 bits, when the value of enumerator cnt9 is 7, last 8 Bit data removals, 4 bits of accumulation
Data enter into enumerator cnt9 next round counting as minimum 4 waits of displacement posterior bumper；
5, when the value of enumerator cnt4 is 2, the count range of enumerator cnt9 is 0-7, and the data of 66 bits enter speed change
The buffer of 72 bits of case, the high 2 bit zero paddings of buffer, when enumerator cnt9 is 0, the value of buffer presses the 8T clock cycle
Move to right the output as data of 8 bits, when the value of enumerator cnt9 is 7, last 8 Bit data removals, 6 bits of accumulation
Data enter into enumerator cnt9 next round counting as minimum 6 waits of displacement posterior bumper；
6, when the value of enumerator cnt4 is 3, the count range of enumerator cnt9 is 0-8, and the data of 66 bits enter speed change
High 66 bits of the buffer of 72 bits of case, last round of accumulative low 6 Bit datas as low level, enumerator cnt9 are
When 0, the value of buffer moves to right the output as data of 8 bits by the 8T clock cycle, when the value of enumerator cnt9 is 8, and last 8
Bit data removes, and does not has the data of accumulation to enter into enumerator cnt9 next round counting；
7, through one 8*8T, 8*8T, 8*8T, 9*8T} week after date, and complete 4 66 bits input data into 33 8 ratio
The conversion of special output data.
8, input into change speed gear box at next 66 Bit datas, restart the step of 3 to 6.
Two, change speed gear box circuit carries out data bit width by few to many conversions, and bit wide m wherein inputting data is 8 bits, defeated
Bit wide n going out data is 66 bits；
In the present invention, the input data rate of change speed gear box is equal with output data rate, then the input data of change speed gear box
Clock frequency a=1/ (8T)=1.289GHz used, output clock frequency b=1/ (66T)=156.25MHz used by data, its
Middle T is expressed as the cycle of each Bit data transmission, T=0.09697ns.
In the present invention, the period definition of change speed gear box clock source is 8T, and this 8T clock is produced by PLL built-in for Serdes,
Then the clock cycle of change speed gear box input data is 8T, and the clock cycle of change speed gear box output data is 66T；
Enumerator cnt9 and the determination of cnt4 count range:
The situation that after enumerator cnt9 control restructuring, the length in each cycle of clock shifts with output data, enumerator
The value of cnt4 controls to input the situation of data displacement；
In the present invention, the period definition of change speed gear box clock source is 8T, then under the 9*8T clock cycle, and input accumulation 98
The data of bit, retain the data of 6 bits, 66 Bit datas of output, under the output clock cycle, input 25 8T cycles
8 Bit datas, after exporting 3 66 Bit datas, the data of reservation are 2 bits, then under the 4th output cycle, input
8 Bit datas need to accumulate 8 times, then export 66 Bit data bags, guarantee does not has loss of data, then enumerator cnt9
Count range is 0-8；
For output clock, there is the periodic quantity of two different lengths: 8*8T=64T and 9*8T=72T, according to
((64T) * x+ (72T) * y)/(x+y)=66T, calculates x/y=3/1；Namely the clock cycle of 4 66T can be reassembled as
{ 9*8T, 8*8T, 8*8T, 8*8T}, as shown in Figure 4, the count range of enumerator cnt4 is 0-3；
When the value of enumerator cnt9 is 0, the value of enumerator cnt4 adds one；When the value of enumerator cnt4 is 0, enumerator
The count range of cnt9 is 0-8, and when the value of enumerator cnt4 is other values, the count range of enumerator cnt9 is 0-7；
Need 33 8T clock cycle, just can complete the restructuring of 4 66T cycle clocks, obtained output clock cycle
Though unequal, the meansigma methods in its cycle is equal with 66T:
1, in the clock cycle of the 1st 8T, the value of enumerator cnt9 is 0, and the value of enumerator cnt4 is 0；
2, in the clock cycle of the 2nd 8T, the value of enumerator cnt9 adds one and becomes 1；
3, by that analogy to the clock cycle of the 8th 8T, the value of enumerator cnt9 is accumulated as 7；
4, when the value of enumerator cnt4 is 0, in the clock cycle of the 9th 8T, it is 8 that the value of enumerator cnt9 adds one；
5, in the clock cycle of the 10th 8T, the value of enumerator cnt9 becomes 0 after adding one, and the value of this hour counter cnt4 adds
One becomes 1；
6, in the clock cycle of the 11st 8T, the value of enumerator cnt9 becomes 1 after adding one；
7, by that analogy to the clock cycle of the 17th 8T, the value of enumerator cnt9 is added to 7；
8, when the value of enumerator cnt4 is 1, in the clock cycle of the 18th 8T, the value of enumerator cnt9 reverts to 0, this
The value of hour counter cnt4 adds one and becomes 2；
9, in the clock cycle of the 19th 8T, the value of enumerator cnt9 becomes 1 after adding one；
10, by that analogy to the clock cycle of the 25th 8T, the value of enumerator cnt9 is added to 7；
11, when the value of enumerator cnt4 is 2, in the clock cycle of the 26th 8T, enumerator cnt9 reverts to 0, now
The value of enumerator cnt4 adds one and becomes 3；
12, in the clock cycle of the 27th 8T, the value of enumerator cnt9 becomes 1 after adding one；
13, by that analogy to the clock cycle of the 33rd 8T, the value of enumerator cnt9 is added to 7；
14, when the value of enumerator cnt4 is 3, in the clock cycle of the 34th 8T, the value of enumerator cnt9 is extensive after adding one
Being 0 again, the value of this hour counter cnt4 adds one and becomes 0, repeats 9 operations；
15, the value according to cnt9 can obtain the clock of 66T: when the value of cnt9 is 0, clock is low level, at cnt9
Value when being 4, clock is reversed to high level.
16, when, after the restructuring clock completing 4 66T cycles, repeating 1 to 13 operations and constantly produce input clock.
Need, through 33 8T clock cycle, just to complete the 66 of 33 8 Bit datas to 4 restructuring clock cycle 66T
The conversion of bit output data, as shown in Figure 5:
1, before carrying out bit width conversion, 8 Bit datas inputted are inputted in the data that change speed gear box clock source produces
Multicycle time delay is carried out under restructuring clock；
2, each 8T clock cycle, all input 8 Bit datas and enter change speed gear box, each 8*8T clock cycle or 9*8T
Clock cycle, all export the data of 66 bits；
3, when the value of enumerator cnt4 is 0, the count range of enumerator cnt9 is 0-8, and the data of 8 bits are at 8T clock
Under cycle, enter change speed gear box by the order first filling low level, fill the buffer of full 72 bits, when the value of enumerator cnt9 is 8,
The value of buffer moves to right the output as data of 66 bits by the clock cycle of 72T, after the data of 6 bits of accumulation are as displacement
Minimum 6 waits of buffer enter into enumerator cnt9 next round counting；
4, when the value of enumerator cnt4 is 1, the count range of enumerator cnt9 is 0-7, and the data of 8 bits are at 8T clock
Under cycle, enter change speed gear box by the order first filling low level, high 64 bits of fill buffer, when the value of enumerator cnt9 is 7,
The value of buffer moves to right the output as data of 66 bits by the clock cycle of 64T, after the data of 4 bits of accumulation are as displacement
Minimum 4 waits of buffer enter into enumerator cnt9 next round counting；
5, when the value of enumerator cnt4 is 2, the count range of enumerator cnt9 is 0-7, and the data of 8 bits are at 8T clock
Under cycle, enter change speed gear box by the order first filling low level, start to fill 64 high bits, the highest 2 bits from low 4 bits of buffer
Zero padding, when the value of enumerator cnt9 is 7, the value of buffer moves to right the output as data of 66 bits by the clock cycle of 64T,
The data of 2 bits of accumulation enter into enumerator cnt9 next round counting as minimum 2 waits of displacement posterior bumper；
6, when the value of enumerator cnt4 is 3, the count range of enumerator cnt9 is 0-7, and the data of 8 bits are at 8T clock
Under cycle, enter change speed gear box by the order first filling low level, start to fill 64 high bits, the highest 4 bits from low 2 bits of buffer
Zero padding, now in buffer, valid data bit number is 66, when the value of enumerator cnt9 is 7, the value of buffer press 64T time
The clock cycle moves to right the output as data of 66 bits, does not has the data of accumulation to enter into enumerator cnt9 next round counting；
7, through one 9*8T, 8*8T, 8*8T, 8*8T} week after date, and complete 33 8 bits input data into 4 66 ratio
The conversion of special output data.
8, input into change speed gear box at next 8 Bit datas, restart the step of 3 to 7.
Change speed gear box circuit of the present invention and method of work thereof lead not affecting data transmission ratio spy, do not reduce data and pass
The conversion of data bit width is arbitrarily carried out in the case of defeated efficiency, and the setting of the change speed gear box circuit be applicable to any chip designs
Meter.Present invention is particularly suitable in HSSI High-Speed Serial Interface physical chip, solve Physical Coding Sublayer (PCS) circuit bit wide with
The unmatched problem of bit wide between parallel-serial conversion (Serdes) circuit.By controlling input the used clock of data and output number
According to the phase relation between the generation of used clock, and two clocks, control the conversion between different pieces of information bit wide, from
And realize the data bit width coupling between each internal module.Embodiment of the present invention also provide for corresponding change speed gear box module and electricity
Road.
Claims (3)
1. change the change speed gear box circuit of data bit width in the high-speed transceiver, it is characterized in that: include enumerator generative circuit, time
Clock produces circuit, the first data width change-over circuit, the second data width change-over circuit, the output of described enumerator generative circuit
Connecting clock generation circuit, the input of clock generation circuit connects clock source, and the output of clock generation circuit connects the first data
Width change-over circuit and the second data width change-over circuit；
Described enumerator generative circuit, is used for controlling the whole process of bit width conversion, including the first enumerator and the second enumerator,
The count value of the first enumerator and the second enumerator is all to be determined by the bit wide value of input data and output data；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is more than change speed gear box,
The situation that after first counter controls restructuring, the length in each cycle of input clock shifts with output data, the second meter
The value of number device controls to input the situation of data displacement；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is less than change speed gear box, the first counter controls restructuring
The length in each cycle of rear output clock and the situation of output data displacement, the value of the second enumerator controls input data
The situation of displacement；
When reset signal is effective, the value of the first enumerator and the second enumerator is complete zero；
The count range of the first enumerator is 0 to i, and the count range of the second enumerator is 0 to j+k-1；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is more than this change speed gear box, this change speed gear box clock source
Period definition is T, and the clock generation circuit in change speed gear box can generate the clock of two kinds of different cycles, and their value is respectively T1With
T2, T1<Ta<T2, T1=i*T, T2=(i+1)*T；
T1, T2With the clock cycle T used by input dataaWith the clock cycle T used by output databRelation be: Ta=(j*T1+
k*T2)/(j+k), j and k is positive integer, Tb=T；
The count range of the first enumerator, after j time from 0 to the counting of i-1, carries out k time 0 counting to i, the most again
Carry out j the counting from 0 to i-1, then carry out k time 0 counting to i, and repeat this counting process always；
When bit wide n of the output data that bit wide m of the input data of change speed gear box is less than this change speed gear box,
The period definition of this change speed gear box clock source is T, the clock generation circuit in change speed gear box can generate two kinds of different cycles time
Clock, their value is respectively T1And T2, T1<Tb<T2, T1=i*T, T2=(i+1)*T；
T1, T2With the clock cycle T used by input dataaWith the clock cycle T used by output databRelation be: Tb=(j*T1+
k*T2)/(j+k), j and k is positive integer, Ta=T；
The count range of the first enumerator, after k time from 0 to the counting of i, carries out j time 0 counting to i-1, the most again
Carry out k the counting from 0 to i, then carry out j time 0 counting to i-1, and repeat this counting process always；
First enumerator starts once the counting from 0 to i-1 or the counting from 0 to i, and the second enumerator adds 1；
Described clock generation circuit, inputs and output clock in order to produce the data of change speed gear box circuit；Electricity is generated according to enumerator
The value on road, divides input clock source, produces the data input clock required for change speed gear box and data output clock, the
When the value of one enumerator is 0, the restructuring clock of generation is high level, when the value of the first enumerator is (i-1)/2, and the weight of generation
Group clock becomes low level；When bit wide n of the output data that bit wide m of the input data of change speed gear box is more than change speed gear box, described
Clock generation circuit produces data input clock；When bit wide m of the input data of change speed gear box is less than the output data of change speed gear box
During bit wide n, described clock generation circuit produces data output clock；
Described first data width change-over circuit, in order to carry out reducing the conversion of data width under identical bit rate, first
Bit wide m of data width change-over circuit input data is more than bit wide n of output data；Before carrying out bit width conversion, to input
M Bit data under the data input clock that change speed gear box clock source produces, carry out multicycle time delay；First data width conversion
In circuit, the size of buffer is j* (m-i*n)+m, for input data are carried out temporary transient storage；First data width conversion
During circuit work:
1.1, the value of the first enumerator determines the transformation of change speed gear box data, when the first enumerator starts counting up, inputs new m ratio
Special data enter buffer, and the data that last cycle shift retains are as low level, and the count range at the first enumerator is 0 to i-1
Time, moving to right i n-bit data of output, the data now retained are displaced to the lowest order of buffer, when the counting of the first enumerator
When scope is 0 to i, moving to right i+1 n-bit data of output, experienced by the counting 0 of k time to after i, the bit number of reservation is 0,
Next this section of operation is repeated；
1.2, the value of the second enumerator determines the data of the new m bit inputted position in buffer and the accumulation of upper cycle
Bit number, the bit number of accumulation of upper cycle always as low level, the data of newly inputted m bit as a high position, buffer remaining
Higher bit zero padding, the count range of the second enumerator is when 0 to j-1, and the second enumerator often adds 1, and the bit number of accumulation increases
Adding m-i*n, when the count range of the second enumerator is at j to j+k-1, the second enumerator often adds 1, and the bit number of accumulation reduces n,
When the value of the second enumerator is j+k-1, the bit number of accumulation is zero, and now complete j+k m bit inputs data into (i+
1) conversion of k+i*j n-bit output data of *；
Described second data width change-over circuit, in order to carry out increasing the conversion of data width under identical bit rate, second
Bit wide m of data width change-over circuit input data is less than bit wide n of output data；Before carrying out bit width conversion, to input
M Bit data under the data input clock that change speed gear box clock source produces, carry out multicycle time delay；Second data width conversion
In circuit, the size of buffer is j*i*m, for input data are carried out temporary transient storage；Second data width change-over circuit work
When making:
2.1, the value of the first enumerator determines the transformation of change speed gear box data, when the first enumerator starts to count from 0 to i, and input
I+1 new m Bit data enters buffer, and when the value of the first enumerator is i, buffer moves to right the data of output n-bit, this
Time the data that retain be displaced to the lowest order of buffer, when the count range of the first enumerator is 0 to i-1, input new i
M Bit data enters buffer, and when the value of the first enumerator is i-1, buffer moves to right the data of output n-bit, experienced by k
Secondary count range is 0 to i and after the count range of j time is 0 to i-1, and the bit number of reservation is 0, next repeats this section of behaviour
Make；
2.2, the value of the second enumerator determines the data of the new m bit inputted position in buffer and the accumulation of upper cycle
Bit number, the bit number of accumulation of upper cycle is always as low level, and the data of newly inputted m bit press input sequence successively as high
Position, remaining higher bit zero padding of buffer, when the value of the second enumerator is 0, the bit number of accumulation is (i+1) * m-n, when
When the value of the second enumerator is j+k-1, the bit number of accumulation is zero, now completes the input data of k+i*j m bit of (i+1) *
Conversion to j+k n-bit output data；
Described m, n, i, j, k are positive integer.
2. the change speed gear box circuit changing data bit width in high-speed transceiver as claimed in claim 1, is characterized in that, described
Data input clock or each clock cycle of data output clock that clock generation circuit produces are not quite identical.
3. in high-speed transceiver, change the change speed gear box circuit method of work of data bit width, it is characterized in that: include data bit width
Method and data bit width by multidirectional few conversion are by few method to many conversions；
Described data bit width is referred to the bit wide m output data more than change speed gear box of the input data of change speed gear box by multidirectional few conversion
Bit wide n, and realize data bit width and by the conversion to n position of the m position, described data bit width by the method for multidirectional few conversion be:
3.1, input clock and the output clock of change speed gear box is synchronised clock, during for producing input clock and the output of change speed gear box
The frequency of the clock source of clock is more than or equal to the clock frequency of change speed gear box output clock；
3.2, each clock cycle of the input clock A that this change speed gear box clock source produces is not essentially equal, and average period is Ta；
At the input of data, each clock cycle input m Bit data；
3.3, each clock cycle of the output clock B that this change speed gear box clock source produces is essentially equal, and the clock cycle is Tb；Counting
According to outfan, each clock cycle output n-bit data；
3.4, the period definition of this change speed gear box clock source is T, and the clock generation circuit in change speed gear box can generate two kinds of different cycles
Clock T1And T2, T1<Ta<T2, T1=i*T, T2=(i+1)*T；
3.5、T1, T2With the clock cycle T used by input dataaWith the clock cycle T used by output databRelation be: Ta=
(j*T1+k*T2)/(j+k), Tb=T；
3.6, each cycle is T1Or the cycle is T2Clock cycle, the data all inputting m bit enter change speed gear box；
3.7, each cycle is T1Clock cycle, all export the data of i n-bit, be T in the cycle2Clock cycle, output
(i+1) data of * n-bit；
3.8, at first T1Clock cycle, the data of m bit enter change speed gear box, and the data of i*n bit are output, the bit of reservation
Number is m-i*n；
3.9, by that analogy, in jth T1Clock cycle, the data of m bit enter change speed gear box, and the data of i*n bit are output, and protect
The bit number stayed is j* (m-i*n)；
3.10, at first T2Clock cycle, is also jth+1 the input restructuring clock cycle, and the data of m bit enter change speed gear box, (i
+ 1) data of * n-bit are output, and the bit number of reservation is (j+1) * (m-i*n)-n；
3.11, by that analogy, in kth T2Clock cycle, is also jth+k input restructuring clock cycle, and the data of m bit are entered
Change speed gear box, the data of (i+1) * n-bit are output, and the bit number of reservation is (j+k) * (m-i*n)-k*n=0；
3.12, in the clock cycle of jth+k input data, complete j+k m bit inputs data into k+i*j n of (i+1) *
The conversion of bit output data；
3.13, the step of 3.8 to 3.12 is restarted；
Described data bit width is less than the output data of change speed gear box by bit wide m of few input data referring to change speed gear box to many conversions
Bit wide n, and realize data bit width and by the conversion to n position of the m position, described data bit width by few methods to many conversions be:
4.1, input clock and the output clock of change speed gear box is synchronised clock, during for producing output clock and the input of change speed gear box
The frequency of the clock source of clock is more than or equal to the clock frequency of change speed gear box input clock；
4.2, each clock cycle of output clock B that change speed gear box clock source produces is not essentially equal, but when certain
Under clock periodicity, average period is Tb；At the outfan of data, each clock cycle output n-bit data；
4.3, each clock cycle of the input clock A that change speed gear box clock source produces is essentially equal, and the clock cycle is Ta；In data
Input, each clock cycle input m Bit data；
4.4, the period definition of change speed gear box clock source is T, and the clock generation circuit in change speed gear box can generate two kinds of different cycles
Clock, their value is respectively T1And T2, T1<Tb<T2, T1=i*T, T2=(i+1)*T；
4.5、T1, T2With the clock cycle T used by input dataaWith the clock cycle T used by output databRelation be: Tb=
(j*T1+k*T2)/(j+k), Ta=T；
4.6, each cycle is T1Or the cycle is T2Clock cycle, all from the data of change speed gear box output n-bit；
4.7, each cycle is T1Clock cycle, the data all inputting i m bit enter change speed gear box, are T in the cycle2Clock week
Phase, the data of input (i+1) * m bit enter change speed gear box；
4.8, at first T2Clock cycle, the data of (i+1) * m bit enter change speed gear box, and the data of n-bit are output, reservation
Bit number is (i+1) * m-n；
4.9, at first T1Clock cycle, the data of i*m bit enter change speed gear box, and the data of n-bit are output, the bit of reservation
Number is (2i+1) * m-2n；
4.10, by that analogy, in jth T1Clock cycle, is also kth+j input restructuring clock cycle, the data of i*m bit
Entering change speed gear box, the data of n-bit are output, and the bit number of reservation is k* ((i+1) m-n)-j* (n-i*m)=0；
4.11, in the clock cycle of kth+j input data, complete k+i*j m bit of (i+1) * inputs data into k+j n
The conversion of bit output data；
4.12, the step of 4.8 to 4.11 is restarted；
Described m, n, i, j, k are positive integer.
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| CN109525511B (en) * | 2018-11-07 | 2022-04-01 | 西安微电子技术研究所 | Ten-gigabit Ethernet PCS system based on rate matching and control method |
| CN109962754B (en) * | 2019-02-15 | 2022-01-18 | 深圳市紫光同创电子有限公司 | PCS transmitting device and PCS receiving device adapting to 64B/66B coding |
| CN109885515B (en) * | 2019-02-22 | 2020-09-15 | 烽火通信科技股份有限公司 | Bit width conversion implementation method and system |
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