CN103546169A - Method for achieving (2, 1, 7) convolutional coding at 3/4 rate in Field Programmable Gate Array (FPGA) - Google Patents
Method for achieving (2, 1, 7) convolutional coding at 3/4 rate in Field Programmable Gate Array (FPGA) Download PDFInfo
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- CN103546169A CN103546169A CN201210235434.0A CN201210235434A CN103546169A CN 103546169 A CN103546169 A CN 103546169A CN 201210235434 A CN201210235434 A CN 201210235434A CN 103546169 A CN103546169 A CN 103546169A
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Abstract
The invention discloses a method for achieving (2, 1, 7) convolutional coding at 3/4 rate in a Field Programmable Gate Array (FPGA). The method is achieved through a convolutional coding circuit and a punching circuit. Code elements of codes to be coded are input into the (2, 1, 7) convolutional coding circuit, coded IQ information is output after convolutional coding and is input into the punching circuit, and then the coded IQ information is subjected to fixed information bit deletion through the punching circuit to obtain coding at 3/4 rate; two clocks are arranged in the punching circuit, one is a standard reference clock, the other is a coding clock of convolutional codes, and the rate of the coding clock is 3/4 that of the standard reference clock. According to the method, the two independent counters used for counting input data and output data respectively are designed in the punching circuit, when values of the two counters are equal, data are output completely; when input is larger than output, output indication is valid, otherwise output indication data are void.
Description
Technical field
The present invention relates to digital wireless communication field, relate in particular to the method that realizes 3/4 speed (2,1,7) convolutional encoding in FPGA.
Background technology
Software radio is counted technology in conjunction with the practical application of FPGA, various algorithms can be realized in FPGA, digital signal often due to a variety of causes, makes to produce error code in the data flow transmitting in transmission, thus receiving terminal is produced as image jump, discontinuous, there is the phenomenons such as mosaic.So by this link of chnnel coding, logarithmic code stream is processed accordingly, makes system have certain error correcting capability and antijamming capability, can greatly avoid the generation of error code in code stream transmission.The treatment technology of error code has error correction, interweaves, linear interpolation etc.
Convolutional encoding belongs to a kind of conventional chnnel coding in error correction coding, encoder for convolution codes be characterized as the n bit code of exporting within a period of time, not only relevant with the k position information bit in this period, but also with the information bit of m section in the stipulated time is relevant above, the m=N-1 here, conventionally with (n, k, m), represent convolution code.The essence of chnnel coding is the reliability that increases communication.But chnnel coding can make Useful Information transfer of data reduce, and the process of chnnel coding is insert some code elements or data source was processed by specific algorithm in data source code, thereby reach the object of sentencing wrong and error correction at receiving terminal.Chnnel coding when reducing the error rate, loss be data encoding efficiency. code efficiency is exactly briefly the code element number of raw information code element number after than coding.
Realize 3/4 speed convolutional encoding, need 3 codes of 3 clock cycle inputs, and export 4 codes in the mode of serial, need 4 clock cycle, so there is the unmatched problem of clock rate, speed is not mated and can be solved by sufficiently long buffer memory, yet in serial communication, large buffer memory is obviously unrealistic.
Summary of the invention
The object of this invention is to provide a kind of method that realizes 3/4 speed (2,1,7) convolutional encoding in FPGA, solve existing coding and realize 3/4 speed and have the unmatched problem of clock rate.
In order to realize foregoing invention object, the invention provides and in a kind of FPGA, realize 3/4 speed (2,1,7) method of convolutional encoding, comprising: by code element input (2 to be encoded, 1,7) convolutional encoding circuit, the IQ information after convolutional encoding after output encoder, wherein said (2,1,7) code efficiency of convolutional encoding circuit is 1/2; By the IQ input information after described coding, to punching circuit, the IQ information of punching circuit after to described coding is fixed the deletion of information bit, obtains the coding of 3/4 speed; In described punching circuit, be provided with two clocks, one of them is mark ref clock, another encoded clock that is convolution code, and described encoded clock is 3/4 of mark ref clock speed.
Wherein, described by code element input (2,1 to be encoded, 7) convolutional encoding circuit, IQ information after convolutional encoding after output encoder, further comprises: code element to be encoded is input in 7 grades of shift registers in convolutional encoding circuit, exports parallel I road and Q road two-way information; XOR is carried out to according to the expression formula coefficient 1001111 of K=7 and 1101101 in the I road of output and Q road information, the IQ information after being encoded.
Wherein, IQ input information after described coding, after punching circuit, enters shift register and carries out parallel-serial conversion, and the described encoded clock of take brings into operation as controlling the state counter of beat simultaneously, one group of data counter of every input adds 1, and the maximum of state counter counting is 3; When 3 groups of data of input, described state counter resets.
Preferably, in described punching circuit, include two independently counters, an enter counter for the code element of input is taken statistics, described enter counter carries out accumulated counts according to the state of state counter; Another output counter for the code element of output is taken statistics, described output counter is usingd mark ref clock as controlling beat; When the value of enter counter and output counter equates, data are exported completely; When input is greater than output, output indication is effective, otherwise output designation data is invalid.
Wherein, the IQ input information after described coding is after punching circuit, and punching circuit, according to setting template, deletes unnecessary code element in internal register, then outputs in output register; From output register, export 1, described output counter adds 1.Described setting template adopts fixed form ＂ 11,01,10 ＂.
Compared with prior art, the present invention has following beneficial effect:
1, the present invention adopts convolutional encoding circuit in conjunction with punching circuit, has realized 3/4 speed (2,1,7) convolutional encoding;
2, by two, independently counter is respectively to input data counts and the data counts to output, and when this value that connects individual counter equates, data are exported completely, and when input is greater than output, output indication is effective, otherwise output designation data is invalid.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing:
Fig. 1 is convolutional encoding electrical block diagram in the embodiment of the present invention;
Fig. 2 is the electrical block diagram that punches in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The inventive method has realized the convolutional encoding of a kind of (2,1,7) of 3/4 speed through optimization in FPGA.Convolution code (2,1,7) be characterized as 1 tunnel input, two-way output, 7 grades of shift registers.By in punching circuit, the output of convolutional encoding being fixed to the deletion of information bit, to obtain the coding of 3/4 speed, this encoder, when input signal is continuous, is exported also continuously, and time delay is less than 6 output clock cycles.
Convolutional encoding has different implementation methods fairly simple, and substantially realizing principle is that shift register adds two-way or 3 tunnel XOR circuit, or AND circuit. and punching circuit also has different implementation methods.There is the method based on clock punching, or the method based on doubleclocking.And punching template also has difference, such as based on standard form, based on oneself definition template, speed is from basic 1/2, to 3/4,7/8 after punching etc.And the overall structure of punching circuit and convolution code is also different due to design: there is punching along separate routes, in information source, after convolutional encoding, become the signal on two-way or three tunnels, punching circuit design is in corresponding branch circuit. or the signal after convolution is first exported, at the punching circuit to special, carry out parallel-serial conversion again, punch again, the cell not transmitting of Delete superfluous, only retains the information source output of transmission.
The realization of the inventive method is divided into two parts in overall structure, first is convolutional encoding circuit, and referring to Fig. 1, this part is input as coding raw information (being code element to be encoded), after convolutional encoding, export parallel two-way IQ information, code efficiency is 1/2.
Second portion is punching circuit, and referring to Fig. 2, this part is input as the IQ information after coding, is output as the code element after 3/4 speed punching.Convolutional encoding circuit, at 3 codes of 3 clock cycle inputs, obtains exporting 3 group codes totally 6 code words, and only remain 4 codes after more than punching is deleted.The mode of system serial is exported 4 codes, so need 4 clock cycle. there is the unmatched problem of clock rate. and speed is not mated the clock that must need different rates, otherwise wants sufficiently long buffer memory.In serial communication, large buffer memory is obviously unrealistic. and it is obviously the problem that will consider that doubleclocking is added in that one-level.
In the forward error correction that is applied in DVB due to the inventive method, the data of convolutional encoding are the output that comes from interleaver.If adopt the mode of clock punching in convolutional encoding, and comprise an invalid clock cycle in every 4 clock cycle, in the invalid clock cycle, do not export convolutional encoding code character to punching circuit, in convolution and punching circuit, just only need like this clock, but, at the output of front-end circuit interleaver after 3 useful data of every output, just keep an invalid output, so just the not matched transform of speed to front end interleaver, i.e. the input and output of interleaver need two clock signals that speed is different.Another scheme be the interleaver of front end adopt a clock as input and output, in convolution circuit part, also keep clock input and output, and do speed conversion in punching circuit, adopt two clocks.As optimization, the inventive method is selected the latter, in punching circuit, there are two clocks: one is mark ref clock, another is the encoded clock of convolution code, described encoded clock is 3/4 of mark ref clock speed, be every 4 table ref clocks, convolution code is actual only has 3 clocks, exports 3 groups of IQ signals to punching circuit unit.
This example adopts the coding of convolution code (2,1,7), and it inputs 1 tunnel, output two-way, and register capacity is 7.When input is effective, code element to be encoded is input in 7 grades of shift registers, XOR is carried out according to the expression formula coefficient 1001111 of K=7 and 1101101 in I road and the Q road of output, IQ information (referring to Fig. 1) after being encoded, this part circuit (convolutional encoding circuit) time delay is 1 clock, and the IQ input information after coding is done computing again to punching circuit.Referring to Fig. 2, data are after entering punching circuit, enter shift register, the described encoded clock of take brings into operation as controlling the state counter of beat simultaneously, and one group of data counter of every input adds 1, and the maximum of this counting is 3, input IQ data enter shift register and carry out parallel-serial conversion, when 3 groups of data inputs of totally 6 data of input, complete a state, state counter resets.Input data are input to internal register from input register, and punching circuit, according to fixing template, deletes unnecessary code element in internal register, then outputs in output register.Punching circuit design has an output counter, exports 1 from output register, and output counter is usingd mark ref clock as controlling beat, and output counter adds 1. templates and adopts fixed form ＂ 11,01,10 ＂.Two code element information of first clock input will all be exported, if a group code unit of first clock input will all export, obviously want the output clock of two frequencys multiplication, because inside circuit does not have clock multiplier.And output clock is all the time 4/3 times of input, so the code element of output encoder correctly when time delay one is clapped.As optimization, the buffer memory that data after punching have adopted to output register, the data of input want the code character of a template of buffer memory to export again. the data after buffer memory, in input data continuous effective, 5～6 standard time clocks of output time delay of coded data, the coded data of output also keeps continuous effective.For to exporting after the punching of input data integrity, as optimization, in design, used two independently counters, an enter counter for the code element of input is taken statistics, described enter counter carries out accumulated counts according to the state of state counter; Another output counter for the code element of output is taken statistics, described output counter is usingd mark ref clock as controlling beat.As convolutional encoding, data block is encoded, often complete the coding of a data block, make coding think highly of first and make zero, when encoder makes zero, also counter is made zero simultaneously.In the cataloged procedure of each data block, to guarantee each code element output completely after punching circuit of input, as long as guarantee that the value of these two counters equates just can.When the value of enter counter and output counter equates, data are exported completely; When input is greater than output, output indication is effective, otherwise output designation data is invalid.
Disclosed all features in this specification, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.
Disclosed arbitrary feature in this specification (comprising any accessory claim, summary and accompanying drawing), unless narration especially all can be replaced by other equivalences or the alternative features with similar object.That is,, unless narration especially, each feature is an example in a series of equivalences or similar characteristics.
The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature or any new combination disclosing in this manual, and the arbitrary new method disclosing or step or any new combination of process.
Claims (6)
- The method that realizes 3/4 speed (2,1,7) convolutional encoding in 1.FPGA, is characterized in that, comprising:By code element input (2,1,7) convolutional encoding circuit to be encoded, the IQ information after convolutional encoding after output encoder, the code efficiency of wherein said (2,1,7) convolutional encoding circuit is 1/2;By the IQ input information after described coding, to punching circuit, the IQ information of punching circuit after to described coding is fixed the deletion of information bit, obtains the coding of 3/4 speed; In described punching circuit, be provided with two clocks, one of them is mark ref clock, another encoded clock that is convolution code, and described encoded clock is 3/4 of mark ref clock speed.
- 2. the method for claim 1, is characterized in that, described by code element input (2,1,7) convolutional encoding circuit to be encoded, the IQ information after convolutional encoding after output encoder, further comprises:Code element to be encoded is input in 7 grades of shift registers in convolutional encoding circuit, exports parallel I road and Q road two-way information; XOR is carried out to according to the expression formula coefficient 1001111 of K=7 and 1101101 in the I road of output and Q road information, the IQ information after being encoded.
- 3. method as claimed in claim 2, it is characterized in that, IQ input information after described coding is after punching circuit, enter shift register and carry out parallel-serial conversion, the described encoded clock of take brings into operation as controlling the state counter of beat simultaneously, one group of data counter of every input adds 1, and the maximum of state counter counting is 3; When 3 groups of data of input, described state counter resets.
- 4. method as claimed any one in claims 1 to 3, it is characterized in that, in described punching circuit, include two independently counters, an enter counter for the code element of input is taken statistics, described enter counter carries out accumulated counts according to the state of state counter; Another output counter for the code element of output is taken statistics, described output counter is usingd mark ref clock as controlling beat;When the value of enter counter and output counter equates, data are exported completely; When input is greater than output, output indication is effective, otherwise output designation data is invalid.
- 5. method as claimed in claim 4, is characterized in that, the IQ input information after described coding is after punching circuit, and punching circuit, according to setting template, deletes unnecessary code element in internal register, then outputs in output register; From output register, export 1, described output counter adds 1.
- 6. method as claimed in claim 5, is characterized in that, described setting template adopts fixed form ＂ 11,01,10 ＂.
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| CN104199352B (en) * | 2014-08-21 | 2017-02-15 | 东南大学 | Range encoding hardware implementation system based on FPGA (field programmable gate array) |
| CN108011640A (en) * | 2016-11-01 | 2018-05-08 | 中国科学院沈阳自动化研究所 | One kind is used for the universal method of (2,1, N) convolutional encoding |
| CN109635929A (en) * | 2018-12-07 | 2019-04-16 | 锐捷网络股份有限公司 | Convolution implementation method and acoustic convolver based on FPGA |
| CN111922536A (en) * | 2020-09-23 | 2020-11-13 | 南京大树智能科技股份有限公司 | Cigarette filter tip laser drilling angle positioning method based on FPGA hardware logic control |
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Cited By (5)
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| CN104199352B (en) * | 2014-08-21 | 2017-02-15 | 东南大学 | Range encoding hardware implementation system based on FPGA (field programmable gate array) |
| CN108011640A (en) * | 2016-11-01 | 2018-05-08 | 中国科学院沈阳自动化研究所 | One kind is used for the universal method of (2,1, N) convolutional encoding |
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| CN109635929A (en) * | 2018-12-07 | 2019-04-16 | 锐捷网络股份有限公司 | Convolution implementation method and acoustic convolver based on FPGA |
| CN111922536A (en) * | 2020-09-23 | 2020-11-13 | 南京大树智能科技股份有限公司 | Cigarette filter tip laser drilling angle positioning method based on FPGA hardware logic control |
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