CN102468856B - High speed parallel concatenated code coder decoder - Google Patents
High speed parallel concatenated code coder decoder Download PDFInfo
- Publication number
- CN102468856B CN102468856B CN2010105360876A CN201010536087A CN102468856B CN 102468856 B CN102468856 B CN 102468856B CN 2010105360876 A CN2010105360876 A CN 2010105360876A CN 201010536087 A CN201010536087 A CN 201010536087A CN 102468856 B CN102468856 B CN 102468856B
- Authority
- CN
- China
- Prior art keywords
- data
- decoder
- input port
- output
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Error Detection And Correction (AREA)
Abstract
The invention discloses a high speed parallel concatenated code coder decoder, which is widely applied to satellite communication systems, deep space communication systems and the like. The high speed parallel concatenated code coder decoder comprises a coder and a decoder, wherein the coder comprises a branch convertor, a first remote sensing (RS) coder, a second RS coder, a third RS coder, a fourth RS coder, a first frame inserting device, a second frame inserting device, a third frame inserting device, a fourth frame inserting device, a first interleaver group, a second interleaver group, a third interleaver group, a fourth interleaver group, a first convolutional code coder, a second convolutional code coder, a third convolutional code coder and a fourth convolutional code coder; and the decoder comprises a phase convertor, a first convolutional code decoder, a second convolutional code decoder, a third convolutional code decoder, a fourth convolutional code decoder, a first frame searching device, a second frame searching device, a third frame searching device, a fourth frame searching device, a first deinterleaver, a second deinterleaver, a third deinterleaver, a fourth deinterleaver, a first RS decoder, a second RS decoder, a third RS decoder and a fourth RS decoder. The coder directly performs concatenated code coding on high speed serial data through a high speed parallel technology, and transmits the coded data to modulation equipment in a parallel mode; and the decoder directly performs concatenated code decoding on parallel data with phase ambiguity output by a demodulator, and problems of sequence randomness of the parallel data, random malalignment of the parallel data and the like caused by the randomness of analog/digital (AD) sampling time can be solved.
Description
Technical field
The present invention relates to a kind of high speed parallel concatenated code coder decoder in the communications field, be specially adapted to high information rate channel coding and decoding device.
Background technology
Traditional cascaded code coder-decoder adopts serial structure to complete cascaded code coding and decoding code function more, and the resource occupation amount is few, simple in structure is its outstanding advantages, is particularly suitable for low-rate data and carries out the cascaded code coding and decoding.When it, there is an outstanding defect during for high data rate cascaded code coding and decoding: the raising of information rate, need coder-decoder also to want corresponding raising to the processing speed of data, when the coder-decoder processing speed acquires a certain degree, due to the restriction that is subject to chip processing speed and implementation complexity factor, in engineering, will be difficult to realize.Therefore, in the high data rate situation, the application of serial concatenation of codes coder-decoder is greatly limited.
Summary of the invention
The object of the invention is to avoid the weak point in the above-mentioned background technology and a kind of brand-new high speed parallel concatenated code coder decoder is provided.The present invention not only has the systematic function identical with traditional serial concatenation of codes coder-decoder, and by decoder, directly eliminated the data phase ambiguity problem of bringing due to phase-modulation, and overcome between the decoding end parallel data of bringing due to parallel data processing the problem such as different random order between different random time delay and parallel data, also had the characteristics such as integrated degree is high, volume is little, lightweight, mobility is good.
The object of the present invention is achieved like this:
High speed parallel concatenated code coder decoder, comprise encoder and decoder, described encoder comprises converter 1, first to fourth RS encoder 2-1 to 2-4, first to fourth interleave device 3-1 to 3-4, first to fourth interleaver group 4-1 to 4-4 and first to fourth encoder for convolution codes 5-1 to 5-4 along separate routes; Described decoder comprises that phase converter 6, first to fourth Convolutional Decoder Assembly 7-1 to 7-4, first to fourth search frame device 8-1 to 8-4, first to fourth deinterleaver 9-1 to 9-4 and first to fourth RS decoder 10-1 to 10-4;
The input port 1 of described shunt converter 1 is connected with serial data input port A1 to be encoded, the input port 2 of converter 1 is connected with source synchronous clock input port B 1 along separate routes, and the output port 3,4,5,6 of converter 1 is connected with the first input port 1 to RS encoder 2-1 to 2-4 respectively along separate routes; Each output port 2 of first to RS encoder 2-1 to 2-4 is connected with the input port 1 of first to fourth interleave device 3-1 to 3-4 respectively; The output port 2 of first to fourth interleave device 3-1 to 3-4 is connected with the input port 1 of first to fourth interleaver group 4-1 to 4-4 respectively; The output port 2 of first to fourth interleaver group 4-1 to 4-4 is connected with first to fourth encoder for convolution codes 5-1 to 5-4 input port 1 respectively; The output port 2,3 of first to fourth encoder for convolution codes 5-1 to 5-4 is exported respectively completed coded data;
converter carries out the serial data of input to obtain four channel parallel datas and export respectively first to fourth RS encoder to after the serial to parallel conversion processing along separate routes, first to fourth RS encoder carries out the data of input respectively exporting first to fourth interleave device to after the RS coding, last bit check position that first to fourth interleave device produces the RS encoder is with fixing frame head replacement and data are exported to first to fourth interleaver, first to fourth interleaver will be inputted data and carry out going out to first to fourth encoder for convolution codes after interleaving treatment, after first to fourth encoder for convolution codes carries out convolution coding to the input data, export respectively completed coded data,
the input port 1 of described phase converter 6, 2, 3, 4, 5, 6, 7, 8 are connected with 8 tunnel parallel datas to be decoded of demodulated equipment output respectively, phase converter 6 output ports 9, 10, 11, 12, 13, 14, 15, 16 respectively with the input port 1 of first to fourth Convolutional Decoder Assembly 7-1 to 7-4, 2 are connected, phase converter 6 input ports 17, 19, 21, 23 are connected with the output port 4 of first to fourth Convolutional Decoder Assembly 7-1 to 7-4 respectively, the input port 18 of phase converter 6, 20, 22, 24 are connected with first to fourth output port 3 of searching frame device 8-1 to 8-4 respectively, the output port 3 of first to fourth Convolutional Decoder Assembly 7-1 to 7-4 is connected with first to fourth input port 1 of searching frame device 8-1 to 8-4 respectively, first to fourth output port 2 of searching frame device 8-1 to 8-4 is connected with the input port 1 of first to fourth deinterleaver 9-1 to 9-4 respectively, and first to fourth output port 4 of searching frame device 8-1 to the 8-4 input port 3 corresponding with first to fourth deinterleaver 9-1 to 9-4 respectively is connected, the output port 2 of first to fourth deinterleaver 9-1 to 9-4 is connected with the input port 1 of first to fourth RS decoder 10-1 to 10-4 respectively, the output port 4 of first to fourth deinterleaver 9-1 to 9-4 is connected with the input port 3 of first to fourth RS decoder 10-1 to 10-4 respectively, the output port 2 output data of first to fourth RS decoder 10-1 to 10-4 are the high-speed parallel cascade codes decoder and finally export data, and will be transferred to corresponding follow-up data receiving equipment,
phase converter searches according to first to fourth Convolutional Decoder Assembly and first to fourth feedback control signal that the frame device provides, after 8 tunnel parallel datas to be decoded of demodulated equipment output are carried out to self-adaptive processing, export to first to fourth Convolutional Decoder Assembly, after first to fourth Convolutional Decoder Assembly carries out convolution code decoding to the input data, output it to first to fourth and search the frame device, first to fourth searches the frame device searches frame to the input data, data are exported to first to fourth deinterleaver after frame synchronization, after first to fourth deinterleaver carries out the deinterleaving processing to the input data, data are exported to first to fourth RS decoder, first to fourth RS decoder carries out output data after RS decoding to the input data and is the high-speed parallel cascade codes decoder and finally exports data, and will be transferred to corresponding follow-up data receiving equipment,
described phase converter 6 comprises first to fourth controlled backward crossover parallel operation 11-1 to 11-4, first to fourth controllable time delay device 12-1 to 12-4, controlled Order exchange device 13 and data adjustment controller 14, first to fourth each input port 1,2 of controlled backward crossover parallel operation 11-1 to 11-4 connects respectively data to decode, the output port 3,4 of first to fourth controlled backward crossover parallel operation 11-1 to 11-4 is connected with the input port 1,2 of first to fourth controllable time delay device 12-1 to 12-4 respectively, the output port 3 of first to fourth controllable time delay device 12-1 to 12-4 is connected with controlled Order exchange device 13 input ports 1,3,5,7 respectively, and the output port 5 of first to fourth controllable time delay device 12-1 to 12-4 is connected with controlled Order exchange device 13 input ports 2,4,6,8 respectively, controlled Order exchange device 13 output ports 9,11,13,15 are connected with the input port 1 of first to fourth Convolutional Decoder Assembly 7-1 to 7-4 respectively, and controlled Order exchange device 13 output ports 10,12,14,16 are connected with the input port 2 of first to fourth Convolutional Decoder Assembly 7-1 to 7-4 respectively, data are adjusted controller 14 input ports 3, 4, 5, 6 are connected with the output port 4 of first to fourth Convolutional Decoder Assembly 7-1 to 7-4 respectively, data are adjusted controller 14 input ports 7, 8, 9, 10 pin are connected with first to fourth output port 3 of searching frame device 8-1 to 8-4 respectively, data are adjusted controller 14 output ports 1 and with first to fourth controlled backward crossover parallel operation 11-1 to 11-4 input port 5, are connected respectively, data are adjusted controller 14 output ports 11, 12, 13 are connected with the input port 4 of first to fourth controllable time delay device 12-1 to 12-4 respectively with 14, the output port 2 that data are adjusted controller 14 is connected with the input port 17 of controlled Order exchange device 13,
First to fourth controlled backward crossover parallel operation is adjusted controller output corresponding control signal according to data, after inputting data and carrying out corresponding anti-phase exchange and process, export to first to fourth controllable time delay device, first to fourth controllable time delay device is adjusted controller output corresponding control signal according to data, after data are carried out to the corresponding delay processing, data are exported to controlled Order exchange device, controlled Order exchange device is adjusted controller output corresponding control signal according to data, after data are carried out to corresponding sequence, data are exported to first to fourth Convolutional Decoder Assembly.
Parallel data phase ambiguity elimination algorithm, parallel data time delay elimination algorithm, parallel data random order elimination algorithm in high-speed parallel cascade codes decoder phase converter 6.
The present invention compares background technology and has following advantage:
1. high speed parallel cascade code coder of the present invention adopts the high-speed parallel technology directly to carry out the cascaded code coding to high-speed serial data, and after encoding, data are transferred to corresponding modulating equipment in parallel mode.
2. high speed parallel cascade code decoder of the present invention directly carries out cascaded code decoding to the parallel data with phase ambiguity of demodulator output.
3. automatic phase converter in high-speed parallel cascade codes decoder of the present invention, utilize the convolutional code decoder device, the feedback information of searching the frame device has solved between parallel data between data sequence randomness and parallel data the problem such as not lining up property at random, and these problems are all the new problems of bringing due to after the data parallel processing.
4. building block of the present invention adopts extensive field programmable device to make, and therefore can realize neatly the modification to running parameter by configuring different programs, and structure is simplified greatly, and cost significantly reduces.
5. the integrated degree of the present invention is high, so volume is little, and is lightweight, stable and reliable for performance, easy to maintenance, and the equipment maneuverability obviously improves.
The accompanying drawing explanation
Fig. 1 is the electrical schematic diagram of high-speed parallel cascade codes encoder of the present invention.
Fig. 2 is the electrical schematic diagram of high-speed parallel cascade codes decoder of the present invention.
Fig. 3 is the electrical schematic diagram of phase converter 6 of the present invention.
Embodiment
Referring to figs. 1 through Fig. 3, encoder of the present invention comprises converter 1, RS encoder group 2-1 along separate routes, 2-2,2-3,2-4, interleave device group 3-1,3-2,3-3,3-4, interleaver group 4-1,4-2,4-3,4-4, encoder for convolution codes group 5-1,5-2,5-3,5-4; Decoder comprises phase converter 6, Convolutional Decoder Assembly group 7-1,7-2, and 7-3,7-4, search frame device group 8-1,8-2,8-3,8-4, deinterleaver group 9-1,9-2,9-3,9-4, RS decoder group 10-1,10-2,10-3,10-4; Form.Fig. 1 is the functional-block diagram of realizing of high-speed parallel cascade codes encoder embodiment of the present invention, Fig. 2 is the functional-block diagram of realizing of high-speed parallel cascade codes decoder implementation example of the present invention, and embodiment presses Fig. 1, and Fig. 2 connects.
the input 1 of the phase converter 6 in described high-speed parallel cascade codes decoder, 2, 3, 4, 5, 6, 7, 8 pin respectively with data to decode A2, B2, C2, D2, E2, F2, G2, H2 is connected, phase converter 6 inputs 17, 18, 19, 20, 21, 22, 23, 24 pin respectively with Convolutional Decoder Assembly group 7-1, 7-2, 7-3, 7-4 exports 4 pin and searches frame device group 8-1, 8-2, 8-3, each corresponding pin of 8-4 output 3 pin is connected, phase converter 6 carries out automatic phase by these feedback signals to input signal and becomes ring, Order exchange and relative time delay eliminate, signal exports respectively Convolutional Decoder Assembly group 7-1 to after conversion process, 7-2, 7-3, the corresponding input of 7-4 1 pin, 2 pin, Convolutional Decoder Assembly group 7-1, 7-2, 7-3, 7-4 is by the soft core of the Convolutional Decoder Assembly that provides in ISE10.1, according to actual requirement of engineering and correlative coding device, arrange, by the soft karyogenesis guide of encoder for convolution codes, carry out the relevant parameter setting and generate corresponding net table, finally on the FPGA series of products LXC5V220 model that the former factory of Xilinx produces, realize, Convolutional Decoder Assembly group 7-1, 7-2, 7-3, 7-4 carries out the data of input by its corresponding output 2 pin, the data after each decoding to be exported to and search frame device group 8-1 after convolution code decoding, 8-2, 8-3, the corresponding input of 8-4 1 pin, search frame device group 8-1, 8-2, 8-3, the 8-4 operation principle is, searching the frame device will input data and be divided into 4 tunnels, every circuit-switched data compares from different frame heads respectively by shift register, when certain comparison equates for the first time, the corresponding counts device starts counting, if comparison is also for equating when next frame head should occur, think the discovery frame head, if it is unequal that compare this moment, counter O reset, the frame synchronizing signal formal definition is, when there is no frame synchronization, for logic low, if during frame synchronization, at first be the 3bit high level, then according to corresponding frame head classification, be " 00 " according to this, " 01 ", " 10 ", " 11 ", then export high level, loop cycle according to this, when OOF, signal becomes low level, if namely this signal has the 3bit logic low, represent OOF, after being judged as frame synchronization, by the data on corresponding frame synchronization road by searching frame device group 8-1, 8-2, 8-3, 8-4 output 2 pin are exported to respectively deinterleaver group 9-1, 9-2, 9-3, 9-4, and by searching frame device group 8-1, 8-2, 8-3, 8-4 output 4 toes show the frame synchronization start position information of being correlated with, deinterleaver group 9-1, 9-2, 9-3, 9-4 is by the soft core of the Convolutional Decoder Assembly that provides in ISE10.1, according to actual requirement of engineering and correlative coding device, arrange, by the soft karyogenesis guide of encoder for convolution codes, carry out the relevant parameter setting and generate corresponding net table, finally on the FPGA series of products LXC5V220 model that the former factory of Xilinx produces, realize, deinterleaver group 9-1, 9-2, 9-3, 9-4 will input data and carry out after the deinterleaving processing by deinterleaver group 9-1, 9-2, 9-3, the corresponding output of 9-4 2 pin are exported to respectively RS decoder group 10-1, 10-2, 10-3, corresponding input 1 pin of 10-4, corresponding frame synchronizing signal is by deinterleaver group 9-1, 9-2, 9-3, the corresponding output of 9-4 4 pin are exported to RS decoder group 10-1, 10-2, 10-3, 10-4 inputs 3 pin, RS decoder group 10-1, 10-2, 10-3, 10-4 is by the soft core of RS decoder that provides in ISE10.1, according to actual requirement of engineering and correlative coding device, arrange, by the soft karyogenesis guide of RS decoder, carry out the relevant parameter setting and generate corresponding net table, finally on the FPGA series of products LXC5V220 model that the former factory of Xilinx produces, realize, RS decoder group 10-1, 10-2, 10-3, after 10-4 carries out RS decoding to the input data, by RS decoder group 10-1, 10-2, 10-3, 10-4 is data after decoding the high-speed parallel cascade codes decoder and finally exports data from exporting 2 pin outputs, this 4 circuit-switched data was advanced parallel serial conversion, can realize serial output.
Described phase converter 6 is by controlled backward crossover parallel operation group 11-1,11-2, and 11-3,11-4, controllable time delay device group 12-1,12-2,12-3,12-4, controlled Order exchange device 13, data are adjusted controller 14 and are formed.controlled backward crossover parallel operation group 11-1, 11-2, 11-3, 11-4 input 1, 2 pin are connected respectively data to decode A, B, C, D, E, F, G, H, controlled backward crossover parallel operation group 11-1, 11-2, 11-3, 11-4 adjusts controller output 1 pin by controlled backward crossover parallel operation group 11-1 according to data, 11-2, 11-3, the control feedback signal of 11-4 input 5 pin accesses, when rising edge appears in this signal, controlled backward crossover parallel operation group 11-1, 11-2, 11-3, 11-4 carries out anti-phase to the input data successively, one of 8 clock combined transformations of exchange, controlled backward crossover parallel operation group 11-1, 11-2, 11-3, 11-4 output 3, data after 4 pin will be processed transfer to respectively controllable time delay device 12-1, 12-2, 12-3, the corresponding input 1 of 12-4, 2 pin, controllable time delay device group 12-1, 12-2, 12-3, 12-4 adjusts controller output 11 according to data, 12, 13, 14 pin are by controlled backward crossover parallel operation group 11-1, 11-2, 11-3, the control feedback signal of each self-corresponding input 5 pin accesses of 11-4, when this signal is high level, by exporting 3, 5 pin output data relatively postpone 1 and clap, when this signal is low level, by exporting 3, 5 pin output data are without relative delay, controllable time delay device 12-1, 12-2, 12-3, data after 12-4 will process are by output 3, 5 pin correspondence respectively are transferred to controlled Order exchange device 13 inputs 1, 2, 3, 4, 5, 6, 7, 8 pin, controlled Order exchange device 13 is adjusted controller output 17 pin by the control feedback signal of controlled Order exchange device 13 input 17 pin accesses according to data, carry out corresponding data sequence adjustment, data after controlled Order exchange device will be processed are by corresponding output 9, 10, 11, 12, 13, 14, 15, 16 pin, export to convolution decoder group 7-1, 7-2, 7-3, the corresponding input of 7-4 1 pin, 2 pin.data are adjusted controller 17 by convolution decoder group 7-1, 7-2, 7-3, 7-4 exports the error rate Threshold Feedback signal of 4 pin outputs and searches frame device group 8-1, 8-2, 8-3, the frame synchronization index signal of 8-4 output 3 pin outputs, by 8 tunnels with the door as the particular cycle counter reset signal, when this rolling counters forward reaches highest order, produce a pulse signal, all the other situations, this signal is low level, this signal is by output 1 pin output, when above-mentioned low level continues for some time, while there is no pulse signal simultaneously, starting Controled delay controls, this moment is according to the frame synchronizing signal relative time delay, by exporting 11, 12, 13, 14 foot control signal processed is controlled respectively the relative time delay of data, after this EO, by the internal trigger signal, starting controlled Order exchange processes, frame head indication information after this moment Suo Cunge road frame synchronizing signal, can produce control signal, by exporting the controlled Order exchange device 13 of 2 foot control system, completing Order exchange processes, controlled Order exchange device 13 outputs 9, 10, 11, 12, 13, 14, 15, transfer of data after 16 pin will be processed is successively given corresponding Convolutional Decoder Assembly group 7-1, 7-2, 7-3, the corresponding input 1 of 7-4, 2 pin.
The concise and to the point operation principle of the present invention is as follows:
when external traffic signal is carried out the high-speed parallel cascade codes coding, shunt converter 1 input 1 pin in described high-speed parallel cascade codes encoder is connected by the A1 passage with input data to be encoded, input 2 pin are connected with input data respective sources synchronizing clock signals B1, its output 3, 4, 5, 6 pin are connected with RS encoder group respectively, data export the RS encoder to carry out the RS coding after, by its output 2 pin, export the data after each coding to the interleave device, the interleave device will be inputted data and export to interleaver after the data interleave, interleaver will be inputted data and carry out exporting to encoder for convolution codes after interleaving treatment, after encoder for convolution codes carries out convolutional encoding to the input data, encoder for convolution codes output data are the high-speed parallel cascade codes encoder and finally export data.
after receiving parallel data to be decoded, phase converter 6 inputs in described high-speed parallel cascade codes decoder and parallel data to be decoded are by passage A2, B2, C2, D2, E2, F2, G2, H2 is connected, phase converter 6 carries out input data bitstream stream to export Convolutional Decoder Assembly to after corresponding conversion, Convolutional Decoder Assembly carries out the data of input by its output, the data flow after each decoding to be exported to and searches the frame device after convolution code decoding, after searching the frame device and completing data and search frame, data are exported to deinterleaver, deinterleaver will be inputted data and carry out exporting to the RS decoder after the deinterleaving processing, after the RS decoder carries out RS decoding to the input data, output signal is the high-speed parallel cascade codes decoder and finally exports data.
Software programming structure of the present invention is as follows:
In Fig. 1, all functions module all can realize in Virtex_LX110, and in Fig. 2, all functions module all can realize in Virtex_LX220, thereby and connects inputoutput data and the present invention of clock signal formation by FPGA corresponding I/O pin.
Claims (3)
1. high speed parallel concatenated code coder decoder, comprise encoder and decoder, it is characterized in that: described encoder comprises converter (1), first to fourth RS encoder (2-1 to 2-4), first to fourth interleave device (3-1 to 3-4), first to fourth interleaver group (4-1 to 4-4) and first to fourth encoder for convolution codes (5-1 to 5-4) along separate routes; Described decoder comprises that phase converter (6), first to fourth Convolutional Decoder Assembly (7-1 to 7-4), first to fourth search frame device (8-1 to 8-4), first to fourth deinterleaver (9-1 to 9-4) and first to fourth RS decoder (10-1 to 10-4);
The input port 1 of described shunt converter (1) is connected with serial data input port A1 to be encoded, the input port 2 of converter (1) is connected with source synchronous clock input port B 1 along separate routes, and the output port 3,4,5,6 of converter (1) is connected with the input port 1 of first to fourth RS encoder (2-1 to 2-4) respectively along separate routes; Each output port 2 of first to fourth RS encoder (2-1 to 2-4) is connected with the input port 1 of first to fourth interleave device (3-1 to 3-4) respectively; The output port 2 of first to fourth interleave device (3-1 to 3-4) is connected with the input port 1 of first to fourth interleaver group (4-1 to 4-4) respectively; The output port 2 of first to fourth interleaver group (4-1 to 4-4) is connected with first to fourth encoder for convolution codes (5-1 to 5-4) input port 1 respectively; The output port 2,3 of first to fourth encoder for convolution codes (5-1 to 5-4) is exported respectively completed coded data;
converter carries out the serial data of input to obtain four channel parallel datas and export respectively first to fourth RS encoder to after the serial to parallel conversion processing along separate routes, first to fourth RS encoder carries out the data of input respectively exporting first to fourth interleave device to after the RS coding, last bit check position that first to fourth interleave device produces the RS encoder is with fixing frame head replacement and data are exported to first to fourth interleaver, first to fourth interleaver will be inputted data and carry out going out to first to fourth encoder for convolution codes after interleaving treatment, after first to fourth encoder for convolution codes carries out convolution coding to the input data, export respectively completed coded data, coded data is transferred to corresponding modulating equipment in parallel mode,
the input port 1 of described phase converter (6), 2, 3, 4, 5, 6, 7, 8 are connected with 8 tunnel parallel datas to be decoded of demodulated equipment output respectively, phase converter (6) output port 9, 10, 11, 12, 13, 14, 15, 16 respectively with the input port 1 of first to fourth Convolutional Decoder Assembly (7-1 to 7-4), 2 are connected, phase converter (6) input port 17, 19, 21, 23 are connected with the output port 4 of first to fourth Convolutional Decoder Assembly (7-1 to 7-4) respectively, the input port 18 of phase converter (6), 20, 22, 24 are connected with first to fourth output port 3 of searching frame device (8-1 to 8-4) respectively, the output port 3 of first to fourth Convolutional Decoder Assembly (7-1 to 7-4) is connected with first to fourth input port 1 of searching frame device (8-1 to 8-4) respectively, first to fourth output port 2 of searching frame device (8-1 to 8-4) is connected with the input port 1 of first to fourth deinterleaver (9-1 to 9-4) respectively, and first to fourth output port 4 of searching frame device (8-1 to the 8-4) input port 3 corresponding with first to fourth deinterleaver (9-1 to 9-4) respectively is connected, the output port 2 of first to fourth deinterleaver (9-1 to 9-4) is connected with the input port 1 of first to fourth RS decoder (10-1 to 10-4) respectively, the output port 4 of first to fourth deinterleaver (9-1 to 9-4) is connected with the input port 3 of first to fourth RS decoder (10-1 to 10-4) respectively, the output port 2 output data of first to fourth RS decoder (10-1 to 10-4) are the high-speed parallel cascade codes decoder and finally export data, and will be transferred to corresponding follow-up data receiving equipment,
phase converter searches according to first to fourth Convolutional Decoder Assembly and first to fourth feedback control signal that the frame device provides, after 8 tunnel parallel datas to be decoded of demodulated equipment output are carried out to self-adaptive processing, export to first to fourth Convolutional Decoder Assembly, after first to fourth Convolutional Decoder Assembly carries out convolution code decoding to the input data, output it to first to fourth and search the frame device, first to fourth searches the frame device searches frame to the input data, data are exported to first to fourth deinterleaver after frame synchronization, after first to fourth deinterleaver carries out the deinterleaving processing to the input data, data are exported to first to fourth RS decoder, first to fourth RS decoder carries out output data after RS decoding to the input data and is the high-speed parallel cascade codes decoder and finally exports data, and will be transferred to corresponding follow-up data receiving equipment.
2. high speed parallel concatenated code coder decoder according to claim 1 is characterized in that: phase converter (6) comprises that first to fourth controlled backward crossover parallel operation (11-1 to 11-4), first to fourth controllable time delay device (12-1 to 12-4), controlled Order exchange device (13) and data adjust controller (14);
each input port 1 of first to fourth controlled backward crossover parallel operation (11-1 to 11-4), 2 connect respectively data to decode, the output port 3 of first to fourth controlled backward crossover parallel operation (11-1 to 11-4), 4 respectively with the input port 1 of first to fourth controllable time delay device (12-1 to 12-4), 2 are connected, the output port 3 of first to fourth controllable time delay device (12-1 to 12-4) respectively with controlled Order exchange device (13) input port 1, 3, 5, 7 are connected, the output port 5 of first to fourth controllable time delay device (12-1 to 12-4) respectively with controlled Order exchange device (13) input port 2, 4, 6, 8 are connected, controlled Order exchange device (13) output port 9,11,13,15 is connected with the input port 1 of first to fourth Convolutional Decoder Assembly (7-1 to 7-4) respectively, and controlled Order exchange device (13) output port 10,12,14,16 is connected with the input port 2 of first to fourth Convolutional Decoder Assembly (7-1 to 7-4) respectively, data are adjusted controller (14) input port 3, 4, 5, 6 are connected with the output port 4 of first to fourth Convolutional Decoder Assembly (7-1 to 7-4) respectively, data are adjusted controller (14) input port 7, 8, 9, 10 pin are connected with first to fourth output port 3 of searching frame device (8-1 to 8-4) respectively, data are adjusted controller (14) output port 1 and with first to fourth controlled backward crossover parallel operation (11-1 to 11-4) input port 5, are connected respectively, data are adjusted controller (14) output port 11, 12, 13 are connected with the input port 4 of first to fourth controllable time delay device (12-1 to 12-4) respectively with 14, the output port 2 that data are adjusted controller (14) is connected with the input port 17 of controlled Order exchange device (13),
First to fourth controlled backward crossover parallel operation is adjusted controller output corresponding control signal according to data, after inputting data and carrying out corresponding anti-phase exchange and process, export to first to fourth controllable time delay device, first to fourth controllable time delay device is adjusted controller output corresponding control signal according to data, after data are carried out to the corresponding delay processing, data are exported to controlled Order exchange device, controlled Order exchange device is adjusted controller output corresponding control signal according to data, after data are carried out to corresponding sequence, data are exported to first to fourth Convolutional Decoder Assembly.
3. high speed parallel concatenated code coder decoder according to claim 1, is characterized in that: parallel data phase ambiguity elimination algorithm, parallel data time delay elimination algorithm, parallel data random order elimination algorithm in high-speed parallel cascade codes decoder phase converter (6).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105360876A CN102468856B (en) | 2010-11-09 | 2010-11-09 | High speed parallel concatenated code coder decoder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105360876A CN102468856B (en) | 2010-11-09 | 2010-11-09 | High speed parallel concatenated code coder decoder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102468856A CN102468856A (en) | 2012-05-23 |
| CN102468856B true CN102468856B (en) | 2013-11-20 |
Family
ID=46072098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105360876A Active CN102468856B (en) | 2010-11-09 | 2010-11-09 | High speed parallel concatenated code coder decoder |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102468856B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102231631B (en) * | 2011-06-20 | 2018-08-07 | 深圳市中兴微电子技术有限公司 | The coding method of RS encoders and RS encoders |
| CN108551384A (en) * | 2018-03-26 | 2018-09-18 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The radio data transmission method of gigabit rate magnitude parallel encoding and modulation |
| CN110519599B (en) * | 2019-08-22 | 2021-05-14 | 北京数码视讯软件技术发展有限公司 | Video coding method and device based on distributed analysis |
| CN110995280B (en) * | 2019-12-19 | 2023-08-01 | 北京遥测技术研究所 | Parallel Viterbi decoder |
| CN113472363B (en) * | 2020-03-31 | 2024-04-26 | 华为技术有限公司 | Coding method and device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540650A (en) * | 2008-03-18 | 2009-09-23 | 中国移动通信集团公司 | Method for transmitting and processing data, communication system and communication devices |
| CN101848002A (en) * | 2010-06-18 | 2010-09-29 | 上海交通大学 | Iterative decoding device of RS (Reed-solomon) cascading grid modulation code and decoding method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8189627B2 (en) * | 2006-06-28 | 2012-05-29 | Samsung & Electronics Co., Ltd. | System and method for digital communications using multiple parallel encoders |
-
2010
- 2010-11-09 CN CN2010105360876A patent/CN102468856B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540650A (en) * | 2008-03-18 | 2009-09-23 | 中国移动通信集团公司 | Method for transmitting and processing data, communication system and communication devices |
| CN101848002A (en) * | 2010-06-18 | 2010-09-29 | 上海交通大学 | Iterative decoding device of RS (Reed-solomon) cascading grid modulation code and decoding method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102468856A (en) | 2012-05-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102468856B (en) | High speed parallel concatenated code coder decoder | |
| CN101777924B (en) | Method and device for decoding Turbo codes | |
| WO2005079507A3 (en) | Method and apparatus for communications using turbo like codes | |
| CN101969311B (en) | High-speed parallel segmented staggering Viterbi decoding method | |
| CN102158235B (en) | The method and device of turbo decoding | |
| CN104601180B (en) | Method and device for encoding two-dimensional product codes on basis of extended hamming codes | |
| CN101764622A (en) | Parallel multicode-rate convolutional code decoding method and realization device thereof | |
| CN103546169A (en) | Method for achieving (2, 1, 7) convolutional coding at 3/4 rate in Field Programmable Gate Array (FPGA) | |
| CN102647202B (en) | Data transmission method and system based on MDFH (Message Driven Frequency Hopping) | |
| CN102394663A (en) | Segment parallel coding method of feedforward convolutional code | |
| CN102185618A (en) | Method for improving Viterbi decoding algorithm and convolutional code decoder | |
| CN102487307B (en) | EOF (end of file) polarity selection method used for FC (fiber channel) protocol | |
| CN103544113A (en) | Implementation method for RAM arranged in FPGA in convolutional interleaving mode based on data block | |
| CN103346860B (en) | A kind of decoding unit of wireless transmitting system and interpretation method thereof | |
| CN2819662Y (en) | Channel cascade coding decoder | |
| CN203800923U (en) | Circuit suitable for chip test | |
| CN101783682B (en) | Foldable structure ADC and error correction method thereof | |
| CN102594358A (en) | Code system conversion circuit for converting binary-coded decimal (BCD) codes to Lee restrict competition count codes | |
| CN103684473A (en) | High-speed serial-parallel conversion circuit based on FPGA | |
| CN102064916B (en) | CMMB standard-based byte interleaving method | |
| CN201533304U (en) | High-speed partial parallel LDPC channel coder | |
| CN102857241B (en) | The parallel encoder of multi code Rate of Chinese character RS code and coding method in a kind of CMMB | |
| CN112383348A (en) | Time-sharing multiplexing time-frequency transmission method based on optical fiber ring network system | |
| CN103929208A (en) | Device for calculating adjoint polynomial in RS encoder | |
| CN102244555A (en) | Blind identification method for coding parameter of Turbo code |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |