CN102594358A - Code system conversion circuit for converting binary-coded decimal (BCD) codes to Lee restrict competition count codes - Google Patents

Abstract

The invention discloses a code system conversion circuit for converting binary-coded decimal (BCD) codes to Lee restrict competition count codes, which comprises an input register, a decoding logic circuit and an output register, wherein the input end of the input register is used for inputting BCD codes to be converted and inputting the BCD codes to be converted into the decoding logic circuit after the BCD codes to be converted are synchronized through synchronous clock signals; the decoding logic circuit decodes the synchronized BCD codes and then sends the synchronized BCD codes to the output register; and the output register is further connected with the synchronous clock signals and outputs four-bit Lee codes under control of the synchronous clock signals, and the output register is further connected with reset signals capable of resetting the circuit. The code system conversion circuit for converting the BCD codes to the Lee restrict competition count codes can achieve reset control and convert the input BCD codes to the Lee codes fast and accurately.

Description

Binary-coded decimal changes the code system change-over circuit of Li Shi restriction competition counting coding

Technical field

The present invention relates to the code system change-over circuit, particularly a kind of binary-coded decimal changes the code system change-over circuit of Li Shi restriction competition counting coding.

Background technology

At present, binary-coded decimal is widely used in the digital circuit field, changes simultaneously yet binary-coded decimal often has long numeric data; Cause phenomenon of competition and risk easily; Particularly particularly evident in combinational logic circuit, the maximum operating frequency that this has just limited digital circuit becomes the bottleneck that performance improves.

And the Li Shi coding is the same with Gray code, has only the one digit number certificate to change between adjacent encoder at every turn, thereby has fundamentally eliminated the race and hazard phenomenon of circuit, cooperates shown in the table 1.Different with Gray code is that the Li Shi coding has characteristic sequence B0 [0:7]=0111_1111 and B1 [0:7]=0001_1100, can produce the Li Shi coding at an easy rate through these two characteristic sequences, thereby it has higher using value than Gray code.

Table 1

16 system numbers	The Li Shi coding	Binary-coded decimal
			?	B3B2B1B0	B3B2B1B0
0	0000	0000
			1	0001	0001
2	1001	0010
			3	1011	0011
4	0011	0100
			5	0111	0101
6	0101	0110
			7	1101	0111
8	1111	1000
			9	1110	1001
A	0110	1010
			B	0100	1011
C	1100	1100
			D	1000	1101
E	1010	1110
			F	0010	1111

With Li Shi coding and binary-coded decimal common application in digital circuit, with the performance that improves digital circuit widely.The patented technology that binary-coded decimal converts the Li Shi coding into does not also appear being used at present.

Summary of the invention

Technical problem to be solved by this invention provides and a kind ofly can realize the control that resets, and changes the code system change-over circuit of Li Shi restriction competition counting coding to the binary-coded decimal that the binary-coded decimal of input converts the Li Shi coding quickly and accurately into.

The present invention adopts following technical scheme for solving the problems of the technologies described above: the present invention has designed the code system change-over circuit that a kind of binary-coded decimal changes Li Shi restriction competition counting coding, it is characterized in that: comprise input register, decoding logic circuit and output register;

The input of said input register is used to import binary-coded decimal to be converted, and imports decoding logic circuit through synchronizing clock signals synchronously;

Said decoding logic circuit is sent into output register with aforementioned after synchronous binary-coded decimal is deciphered;

Said output register also is connected with synchronizing clock signals, and 4 Li Shi of output encode under its control;

Said output register also is connected with the reset signal that can make circuit reset.

The present invention adopts above technical scheme compared with prior art, has following technique effect:

1. the binary-coded decimal that the present invention designed changes the code system change-over circuit of Li Shi restriction competition counting coding can realize resetting controlled function;

2. the code system change-over circuit that the binary-coded decimal that the present invention designed changes Li Shi restriction competition counting coding has synchronization control function, can effectively reduce the race and hazard phenomenon of input signal;

3. the code system change-over circuit simplicity of design that the binary-coded decimal that the present invention designed changes Li Shi restriction competition counting coding is prone to row, and chip area is little, and cost is low;

4. the code system change-over circuit of the binary-coded decimal commentaries on classics Li Shi restriction competition counting coding that the present invention designed is changed accurately, and speed is fast.

Description of drawings

Fig. 1 is that the binary-coded decimal that the present invention designs changes the structural framing figure that the code system change-over circuit of coding is counted in Li Shi restriction competition;

Fig. 2 is that the binary-coded decimal that the present invention designs changes the functional simulation sequential chart that the code system change-over circuit of coding is counted in Li Shi restriction competition;

Fig. 3 is that the binary-coded decimal that the present invention designs changes the gate level circuit figure that the decoding logic circuit part of the code system change-over circuit of encoding is counted in Li Shi restriction competition.

Embodiment

Below in conjunction with accompanying drawing technical scheme of the present invention is done further detailed description:

As shown in Figure 1, the present invention has designed the code system change-over circuit that a kind of binary-coded decimal changes Li Shi restriction competition counting coding, comprises input register, decoding logic circuit and output register, wherein:

Deposit input register in after 4 the binary-coded decimal input, decipher through clock signal back input synchronously decoding logic circuit, and deposit decoding architecture in output register, then 4 Li Shi codings of output under the control of synchronizing clock signals.

As shown in Figure 2, when reset signal Rst_n was low level, output was reset to 0000; When reset signal was invalid, at the rising edge of synchronizing clock signals CLK, 4 BCD of input were deposited in input register, got into decoding logic circuit decoding then, and decode results deposits output register in, exported 4 Li Shi codings then.As can be seen from the figure, 4 Li Shi coding Li [3:0] of output are corresponding one by one with 4 bit code BCD [3:0] of input, explain that this circuit completes successfully the code system translation function.

As shown in Figure 3, the 3rd output L3 of Li Shi coding be 4 input signals mutually or output, and these 4 input signals are 4 binary-coded decimal interdigits with the result.Equally, L2 be 4 input signals mutually or output, and these 4 input signals are 4 binary-coded decimal interdigits with the result; L1 be 5 input signals mutually or output, and these 5 input signals are 4 binary-coded decimal interdigits with the result.L0 then be binary-coded decimal interdigit earlier mutually or, then with output.

Claims (1)

1. a binary-coded decimal changes the code system change-over circuit that Li Shi restriction competition counting is encoded, and it is characterized in that: comprise input register, decoding logic circuit and output register;

The input of said input register is used to import binary-coded decimal to be converted, and imports decoding logic circuit through synchronizing clock signals synchronously;

Said decoding logic circuit is sent into output register with aforementioned after synchronous binary-coded decimal is deciphered;

Said output register also is connected with synchronizing clock signals, and 4 Li Shi of output encode under its control;

Said output register also is connected with the reset signal that can make circuit reset.

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