CN1972131A - Restraint competition count code circuit with mode of reverse phase shift - Google Patents

Abstract

This invention discloses one phase reverse type to control compete Nance meter codes circuit, which comprises two sets of preset switch logic circuits, two sets of eight bits displacement register A and B and its displacement switch, four inverse phase, one four bits output lock registers, wherein, each set switch is relative to displacement register connection and presets sequence level for lock memory with A group sequence for 01111111 and B group for 00011100; each highest bit is connected to lowest bit of the inverse device end by end.

Description

The restraint competition count code circuit of mode of reverse phase shift

Technical field

The present invention relates to the restraint competition count code circuit that a kind of mode of reverse phase shift that restricts 16 scale codings of competition is realized.

Background technology

At present, known 16 scale codings are 8421 yards, this is one group of weight sign indicating number on the natural binary basis, 8421 yards is the nibble in the data, the basic data form of byte (Byte), word modern information technologies such as (Word) can be formed easily, counting, calculating, storage and the exchange of logical circuit can be used for easily.But 8421 yards is one group of 16 system cyclic code, when its adjacent interdigit of encoding is changed, and the chance that has the data more than two to change simultaneously.When being used in counting mode, some the time, for example following table is when 7 (corresponding 8421 yards are 0111) of 16 system numbers become 8 (corresponding 8421 yards is 1000), saltus step all takes place in 8421 yards 4 bit binary data, it is influential to the reliability of data that multidigit changes the competition that brings simultaneously, increased the possibility that data are made mistakes.Can find that by following table 8421 yards adjacent code words that take place to change simultaneously more than 2 amount to 8 times, are respectively 1-2,3-4,5-6,7-8,9-A, B-C, D-E, F-0.Multidigit changes the competition that brings simultaneously, might cause the uncertainty of data.

16 system numbers	8421 yards	Gray code
				bit3 bit2 bit1 bit0	bit3 bit2 bit1 bit0
0	0000	0000
			1	0001	0001
2	0010	0011
			3	0011	0010
4	0100	0110
			5	0101	0111
6	0110	0101
			7	0111	0100
8	1000	1100
			9	1001	1101
A	1010	1111

B	1011	1110
			C	1100	1010
D	1101	1011
			E	1110	1001
F	1111	1000

Gray code of the prior art mainly is an a kind of restriction competition coding, has retrained only to allow one between each code word at every turn and change, but, because Gray code is not a kind of weight sign indicating number, when being used to count, very inconvenient, there is not regularity, promptly lack characteristic sequence.If be used for counting, all relevant register to be set to four sequences, so the circuit more complicated that realizes.

Summary of the invention

The objective of the invention is to address the above problem, a kind of restraint competition count code circuit of mode of reverse phase shift is provided, it can limit the data saltus step more than two when changing between two adjacent encoder groups, improves the reliability of data.

The present invention adopts following technical scheme technical solution problem:

A kind of restraint competition count code circuit of mode of reverse phase shift, comprise 8 bit shift register A, 8 bit shift register B, 4 bit code output register C, initialization initialize switch D, initialization initialize switch E, phase inverter F, G, H, J, the highest order of shift register A and lowest order are end to end by phase inverter F, the highest order of shift register B and lowest order are end to end by phase inverter G, pulse input signal meets the displacement control port CLK of shift register A and shift register B respectively, the shift register A initialize switch D that is initialised is predisposed to fixing characteristic sequence 01111111, the shift register B initialize switch E that is initialised is predisposed to fixing characteristic sequence 00011100, the 4th the highest input of the data position d3 by phase inverter J and sign indicating number output register C from low to high of shift register B and line output is connected, the 4th the inferior high-order d2 of data by phase inverter H and sign indicating number output register C of the little-endian of shift register A and line output is connected, the 0th data time low level d1 with sign indicating number output register C of the lowest order of shift register B and line output is connected, the 0th data lowest order d0 with sign indicating number output register C of the lowest order of shift register A and line output is connected, and exported by 4 restraint competition count codes of high-order d3 to low level d0 by the output control terminal control of sign indicating number output register C.

Coding principle of the present invention is as follows, at first constructs one group of restriction competition coding, and next is according to the characteristics of count code, construct its characteristic sequence, can simplify the design of circuit with this, so, a kind of restraint competition count code, from a high position to the low level, be arranged as bit3 bit2 bit1 bit0, constituting the cycle count of hexadecimal number 0～F, is [bit0]={ 0111,1111 from the bit0 sequence of 0～F, 1000,0000} (hereinafter to be referred as B0), the bit1 sequence is [bit1]={ 0001,1100,1110,0011} (hereinafter to be referred as B1), the bit2 sequence moves down 4 by bit0 by 0～F sequential loop and constitutes [bit2]={ 0000,0111,1111,1000} (hereinafter to be referred as B2), the bit3 sequence moves down 4 by bit1 by 0～F sequential loop and constitutes [bit3]={ 0011,0001,1100,1110} (hereinafter to be referred as B3).Being compared as follows shown in the table of restraint competition count code and 8421 yards:

16 system numbers	8421 yards	Restraint competition count code
				B3B2B1B0	B3B2B1B0
0	0000	0000
			1	0001	0001
2	0010	1001
			3	0011	1011
4	0100	0011
			5	0101	0111
6	0110	0101
			7	0111	1101
8	1000	1111
			9	1001	1110
A	1010	0110
			B	1011	0100
C	1100	1100
			D	1101	1000
E	1110	1010
			F	1111	0010

As seen from the above table, the distinguishing feature of restraint competition count code of the present invention is that counting mode is used restraint, each counting only allows 1bit to change (zero competition), has fundamentally limited the uncertainty that multidigit changes the data that might bring simultaneously.The B2 of this restriction contention code, B3 sequence can obtain from B0, the displacement of B1 sequence, and be exactly its corresponding most-significant byte 10000000 after least-significant byte 01111111 negate of B0, be exactly its corresponding most-significant byte 11100011 after least-significant byte 00011100 negate of B1, the coding that B0, B1, B2, B3 constitute has fixing ordinal relation, the mode that is fit to utilization cyclic shift characteristic sequence realizes counting, constructed two stack features sequences by the least-significant byte of B0, B1 sequence, and obtained complete coding by characteristic sequence.

The sequence table of this coding characteristic is shown B0=01111111, and B1=00011100,8 characteristic sequences are from left to right respectively according to the 0th to the 7th the arrangement from the low level to a high position.

After resetting, B0=01111111, B1=00011100, corresponding count code 0 is if need increase progressively counting, then behind phase inverter ring shift left 5 times, B0=11110000, B1=10011100, then negate B1[4]=0, negate B0[4]=1, get B1[0]=1, get B0[0]=1, constitute restraint competition count code 0111, corresponding to count code 5.If will increase progressively counting once again, then behind phase inverter ring shift left 1 time, B0=111000000, B1=00111000, then negate B1[4]=0, negate B0[4]=1, get B1[0]=0, get B0[0]=1, constitute restraint competition count code 0101, corresponding to count code 6.

After resetting, corresponding count code 0 is if need countdown, then behind the ring shift right 5 times, B0=00000001, B1=00011000, then negate B1[4]=0, negate B0[4]=1, get B1[0]=0, get B0[0]=0, constitute restraint competition count code 0100, corresponding to count code B.If want countdown once again, then behind the ring shift right 1 time, B0=00000000, B1=10001100, then negate B1[4]=0, negate B0[4]=1, get B1[0]=1, get B0[0]=0, formation restraint competition count code 0110 is corresponding to count code A.

Being compared as follows shown in the table of above-mentioned restraint competition count code and Gray code:

16 system numbers	Gray code	Restraint competition count code
				B3B2B1B0	B3B2B1B0
0	0000	0000
			1	0001	0001
2	0011	1001
			3	0010	1011
4	0110	0011
			5	0111	0111
6	0101	0101
			7	0100	1101
8	1100	1111
			9	1101	1110
A	1111	0110
			B	1110	0100
C	1010	1100
			D	1011	1000
E	1001	1010
			F	1000	0010

Compared with prior art, the present invention has the following advantages:

By the comparative result of above-mentioned restraint competition count code and Gray code as can be known, restraint competition count code is made of B0 and two basic sequences of B1, B2, B3 are respectively that B0, B1 negate circulation move down 4 formation, for from the example of front, these characteristics very are fit to realize the coding of counting mode as can be seen.Restraint competition count code of the present invention had both had the characteristics of restriction competition coding, promptly only allowed one digit number according to changing at every turn, had the coding structure of suitable counting mode simultaneously again, can adopt the cyclic shift of characteristic sequence to realize the counting that increases progressively and successively decrease.

Description of drawings

Fig. 1 is the restraint competition count code circuit theory diagram.

Fig. 2 is the restraint competition count code circuit figure that adopts 8 bit shift register modes to realize.

Fig. 3 is the circuit diagram of the register stage implementation of restraint competition count code circuit.

Embodiment

As shown in Figure 1, a kind of restraint competition count code circuit of mode of reverse phase shift, comprise 8 bit shift register A, 8 bit shift register B, 4 bit code output register C, initialization initialize switch D, initialization initialize switch E, phase inverter F, G, H, J, the also line output most significant end of shift register A connects its serial input terminal by phase inverter F, the also line output most significant end of shift register B connects its serial input terminal by phase inverter G, pulse input signal meets the displacement control port CLK of shift register A and shift register B respectively, the shift register A initialize switch D that is initialised is predisposed to fixing characteristic sequence 01111111, the shift register B initialize switch E that is initialised is predisposed to fixing characteristic sequence 00011100, the 4th the highest input of the data position d3 by phase inverter J and sign indicating number output register C from low to high of shift register B and line output is connected, the 4th the inferior low level d2 of data by phase inverter H and sign indicating number output register C of the little-endian of shift register A and line output is connected, the 0th data time high-order d1 with sign indicating number output register C of the lowest order of shift register B and line output is connected, the 0th data lowest order d0 with sign indicating number output register C of the lowest order of shift register A and line output is connected, and exported by 4 restraint competition count codes of high-order d3 to low level d0 by the output control terminal control of sign indicating number output register C.

As shown in Figure 2, above-mentioned sign indicating number output register C adopts latch, above-mentioned shift register A, the serial input terminal Ax of B, Bx links together respectively, the end of the serial input terminal Ax of shift register A by initialization initialize switch D is predisposed to characteristic sequence 01111111 with the input of serial by turn by the antitone sequence 11111110 of characteristic sequence of 8 bit data of register A, the also line output highest order end Q7 of above-mentioned shift register A connects the input of phase inverter F, the output of phase inverter F is by the serial input terminal Ax of another termination shift register A of initialization initialize switch D, the end of the serial input terminal Ax of shift register B by initialization initialize switch E is predisposed to characteristic sequence 00011100 with the input of serial by turn by the antitone sequence 00111000 of characteristic sequence of 8 bit data of register B, the also line output highest order end Q7 of shift register B connects the input of phase inverter G, the output of phase inverter G is by the serial input terminal Ax of another termination shift register B of initialization initialize switch E, shift register A, the clock end CLK of B all links together, connect the step-by-step counting input simultaneously, shift register A, the reset terminal of B

Also all link together and connect high potential, connect the clear terminal of latch C simultaneously

The parallel output terminal Q0 of shift register A meets the data input pin D1 of latch C, the parallel output terminal Q0 of shift register B meets the data input pin D2 of latch C, the parallel output terminal Q4 of shift register A meets the data input D3 of latch C by phase inverter H, the parallel output terminal Q4 of shift register B meets the data input pin D4 of latch C, the output control terminal of latch C by phase inverter J With

End links together, and its output Q4, Q3, Q2, Q1 arrange restraint competition count code d3, d2, d1, the d0 of 4 of outputs from high to low.

As shown in Figure 3, the restraint competition count code circuit of mode of reverse phase shift comprises by two groups of 8 latchs, two groups of 8 initialize switches, and two groups of two groups of each 8 data latch units that two-phase 8 bit shift control switchs constitute, bits per inch comprises an initialize switch according to latch units, a clock switch and a latch, latch is made up of two end to end phase inverters, the input of latch connects the input of initialize switch and the input of clock switch respectively, the output of latch is received the input of the clock switch of next data latch unit, be linked in sequence into the 1st～8 data latch units successively, the output of the 8th data latch units constitutes one first group 8 above-mentioned bit shift register A by the clock switch input that phase inverter F receives the 1st data latch units, two-phase 8 bit shift control switchs are realized by phase inverter respectively, the control end of the transmission gate that 8 two-phase shift switchings are controlled respectively links together separately as the input of pulse, the constituted mode of second group of 8 above-mentioned bit shift register B and first group are identical, the output of its 8th data latch units is received the clock switch input of the 1st data latch units by phase inverter G, first group of shift register A is initialized as characteristic sequence 01111111 by initialize switch, second group of shift register B is initialized as characteristic sequence 00011100 by initialize switch, the output of sign indicating number is the phase inverter H output by the 4th the data latch units LB4 of second group of shift register B, the phase inverter J output of the 4th the data latch units LA4 of first group of shift register A, the 0th the data latch units LB0 output of second group of shift register B, the output of the 0th the data latch units LA0 of first group of shift register A is formed, and forms to arrange 4 restraint competition count code d3 of output from high to low, d2, d1, d0.

When each count pulse arrived, two 8 bit shift register synchronous circulation moved to right one and are the countdown mode; When each count pulse arrived, two 8 bit shift register synchronous circulation moved to left one for increasing progressively counting mode.

The present invention is further described below in conjunction with embodiment.Following table 1 is a restriction competition counting coding schedule.

Table 1 restriction competition counting coding schedule

Table 1 can be summed up the characteristics of this coding thus: the restriction contention code is arranged as bit3-bit0 from a high position to the low level, and constitutes cycle count by 0～F.Bit0, the bit1 of restriction contention code are basic sequences, are [bit0]={ 0111,1111 from the bit0 sequence of 0～F, 1000,0000), the bit1 sequence is [bit1]={ 0001,1100,1110,0011}, the bit2 sequence moves down 4 by bit0 by the 0-F sequential loop and constitutes [bit2]={ 0000,0111,1111,1000}, the bit3 sequence moves down 4 by bit1 by the 0-F sequential loop and constitutes [bit3]={ 0011,0001,1100,1110}.And be exactly its corresponding most-significant byte 10000000 after least-significant byte 01111111 negate of Bit0 sequence, be exactly its corresponding most-significant byte 11100011 after least-significant byte 00011100 negate of Bit1 sequence, the least-significant byte of Bit0 and bit1 sequence is expressed as B0, B1, and B0, B1 sequence are exactly the characteristic sequence of this restriction competition counting coding.B0=01111111, B1=00011100,8 characteristic sequences are from left to right respectively according to the 0th to the 7th the arrangement from the low level to a high position.

Following table 2 is initial value tables of restraint competition count code, and Biao initial value comes to be provided with by the circuit initialize switch characteristic sequence set point of the characteristic sequence value of circuit register: BIT0 and respectively corresponding two eight bit registers of BIT1 thus.

The initial value table of table 2 restraint competition count code

Following table 3 is to implement restriction competition counting coding circuit principle table, Biao register SHTR-BIT0 and SHTR-BIT1 are by the each counting of finishing restraint competition count code of ring shift right (or moving to left) simultaneously of count pulse, by the BIT1[4 of SHTR thus] anti-phase output, BIT0[4] anti-phase output, BIT1[0], BIT0[0] constitute the output result of restriction competition counting coding (RRCC).

Table 3 is implemented restriction competition counting coding circuit principle table

Prime in counting circuit adopts the counting circuit of formation zero competition of restriction competition counting coding.

When being used for counting circuit, restraint competition count code is made of two group of 8 bit shift register of its characteristic sequence correspondence, be respectively SHT-bit0 and SHT-bit1, two groups of shift registers (SHTR) initial value is changed to [SHTR-bit0]={ 0111 respectively, 1111}, [SHTR-bit1]=and 0001,1100}.Each count pulse, the synchronous anti-phase circulation of SHTR-bit0 and SHTR-bit1 move down (moving to right) and are countdown; Each count pulse moves (moving to left) one for increasing progressively counting in the synchronous anti-phase circulation of SHTR-bit0 and SHTR-bit1.

In Fig. 1, shift register A in SHTR-BIT0 in table 2 and the table 3 and the SHTR-1BIT1 corresponding diagram 1 and shift register B, its initial value is exactly a characteristic sequence, finishes by initialize switch D, E.

In Fig. 2, register A in SHTR-BIT0 in table 2 and the table 3 and the SHTR-1BIT1 corresponding diagram 2 and register B, its initial value is exactly a characteristic sequence, finishes by initialize switch D, E.

In Fig. 3, register A in SHTR-BIT0 in table 2 and the table 3 and the SHTR-1BIT1 corresponding diagram 3 and register B, its initial value is exactly a characteristic sequence, finishes by the control of initialize switch K.

When needing the output restraint competition count code, get SHTR-bit0[0 respectively], SHTR-bit1[0], SHTR-bit0[4] anti-phase output, SHTR-bit1[4] anti-phase output restraint competition count code bit0, the bit1, bit2, the bit3 that constitute get final product.

In Fig. 1, the SHTR-bit1[4 in the table 3] anti-phase output, SHTR-bit0[4] anti-phase output, SHTR-bit1[0], SHTR-bit0[0] sign indicating number output d3, d2, d1, the d0 of sign indicating number output register C in the corresponding diagram 1.

In Fig. 2, the SHTR-bit1[4 in the table 3] anti-phase output, SHTR-bit0[4] anti-phase output, SHTR-bit1[0], SHTR-bit0[0] sign indicating number output d3, d2, d1, the d0 of sign indicating number output latch C in the corresponding diagram 2.

In Fig. 3, SHTR-bit1[4 in the table 3] anti-phase output, SHTR-bit0[4] anti-phase output, SHTR-bit1[0], SHTR-bit0[0] in the corresponding diagram 3, respectively by sign indicating number output d3, d2, d1, the d0 of the anti-phase output of latch LB12, the anti-phase output of LA12, LB0, LA0 output.

(embodiment 1)

As shown in Figure 2, after resetting, the end of the serial input terminal Ax of shift register A by characteristic sequence initialization initialize switch D with the antitone sequence 11111110 of characteristic sequence one by one serial import 8 bit shift register A, with its data initialization is characteristic sequence 01111111, the end of the serial input terminal Ax of shift register B by characteristic sequence initialization initialize switch E with the antitone sequence 00111000 of characteristic sequence one by one serial import 8 bit shift register B, with its data initialization is characteristic sequence 00011100, the order of characteristic sequence is the arrangement from low level 0 to a high position 7, this moment the sign indicating number of latch C be output as B[4] negate, A[4] negate, B[0], A[0] }=0000, be 0 of restraint competition count code.

If need increase progressively counting, with the shift register ring shift left.Shift register A, B are by the pre-postpone of switch, when CLK brings out first pulse now, the anti-phase ring shift left of 8 bit data of shift register A once, become 11111111, the anti-phase ring shift left of 8 bit data of shift register B once, become 00111001, this moment, the sign indicating number of latch C was output as 0001, was 1 of restraint competition count code; When CLK brought out second pulse now, the 8 bit data ring shift lefts of shift register 1 and shift register A once became 11111110, the 8 bit data ring shift lefts of shift register B once, become 01110011, this moment, the sign indicating number of latch 5 was output as 1001, was 2 of restraint competition count code; When CLK brings out the 3rd pulse now, the 8 bit data ring shift lefts of shift register A once, become 11111100, the 8 bit data ring shift lefts of shift register B once, become 11100111, this moment, the sign indicating number of latch C was output as 1011, was 3 of restraint competition count code ... go on according to this, when CLK brings out the 15th pulse now, the 8 bit data ring shift lefts of shift register A once become 00111111, and the 8 bit data ring shift lefts of shift register B once, become 10001110, this moment, the sign indicating number of latch C was output as 0010, was the F of restraint competition count code, when CLK brings out the 16th pulse now, the 8 bit data ring shift lefts of shift register A once, become 01111111, the 8 bit data ring shift lefts of shift register B once become 00011100, this and the characteristic sequence that is initially preset by initialize switch are identical, so this moment, the sign indicating number of latch C was output as 0000, was 0 of restraint competition count code, the counting of a beginning new round.

If need countdown, then principle is the shift register ring shift right with above-mentioned identical.When CLK brought out first pulse now, the 8 bit data ring shift rights of shift register A once became 00111111, the 8 bit data ring shift rights of shift register B once, become 10001110, this moment, the sign indicating number of latch C was output as 0010, was the F of restraint competition count code; When CLK brought out second pulse now, the 8 bit data ring shift rights of shift register A once became 00011111, the 8 bit data ring shift rights of shift register B once, become 11000111, this moment, the sign indicating number of latch C was output as 1010, was the E of restraint competition count code; When CLK brings out the 3rd pulse now, the 8 bit data ring shift rights of shift register A once, become 00001111, the 8 bit data ring shift rights of shift register B once, become 01100011, this moment, the sign indicating number of latch C was output as 1000, was the D of restraint competition count code ... go on according to this, when CLK brings out the 15th pulse now, the 8 bit data ring shift rights of shift register A once become 11111111, and the 8 bit data ring shift rights of shift register B once, become 00111001, this moment, the sign indicating number of latch C was output as 0001, was 1 of restraint competition count code, when CLK brings out the 16th pulse now, the 8 bit data ring shift rights of shift register A once, become 01111111, the 8 bit data ring shift rights of shift register B once become 00011100, this and the characteristic sequence that is initially preset by initialize switch are identical, so this moment, the sign indicating number of latch C was output as 0000, was 0 of restraint competition count code, the counting of a beginning new round.

(embodiment 2)

As shown in Figure 3, initialization is by opening initialize switch K the present tube of each latch units to be opened, shift register group A is from LA0～LA7 difference preliminary filling fixed character sequence of electrical potentials 01111111, shift register group B is from LB0～LB7 difference preliminary filling fixed character sequence of electrical potentials 00011100, the order of characteristic sequence is the arrangement from low level 0 to a high position 7, the output code d3d2d1d0 that latch LB4 negate this moment, LA4 negate, LB0, LA0 constitute is output as 0000, is 0 of restraint competition count code.

After the present tube of shift register A, B is closed by initialize switch K, if need increase progressively counting, when CLK brings out first pulse now, the 8 bit data ring shift lefts of shift register A once, become 11111111, the 8 bit data ring shift lefts of shift register B once become 00111001, the output code d3d2d1d0 that latch LB4 negate this moment, LA4 negate, LB0, LA0 constitute is 0001, is 1 of restraint competition count code; When CLK brings out second pulse now, the 8 bit data ring shift lefts of shift register A once, become 11111110, the 8 bit data ring shift lefts of shift register B once, become 01110011, the output code d3d2d1d0 that latch LB4 negate this moment, LA4 negate, LB0, LA0 constitute is 1001, is 2 of restraint competition count code; When CLK brings out the 3rd pulse now, the 8 bit data ring shift lefts of shift register A once, become 11111100, the 8 bit data ring shift lefts of shift register B once, become 11100111, latch LB4 negate this moment, the LA4 negate, LB0, the output code d3d2d1d0 that LA0 constitutes is 1011, be 3 of restraint competition count code, go on according to this, when CLK brings out the 15th pulse now, the 8 bit data ring shift lefts of shift register A once, become 00111111, the 8 bit data ring shift lefts of shift register B once, become 10001110, latch LB4 negate this moment, the LA4 negate, LB0, the output code d3d2d1d0 that LA0 constitutes is 0010, be the F of restraint competition count code, when CLK brings out the 16th pulse now, the 8 bit data ring shift lefts of shift register A once, become 01111111, the 8 bit data ring shift lefts of shift register B once become 00011100, this and the characteristic sequence that is initially preset by initialize switch are identical, so latch LB4 negate this moment, the LA4 negate, LB0, the output code d3d2d1d0 that LA0 constitutes is 0000, is 0 of restraint competition count code, the counting of a beginning new round.

If need countdown, then principle is the shift register ring shift right with above-mentioned identical.When CLK brings out first pulse now, the 8 bit data ring shift rights of shift register A once, become 00111111, the 8 bit data ring shift rights of shift register B once, become 10001110, the output code d3d2d1d0 that latch LB4 negate this moment, LA4 negate, LB0, LA0 constitute is 0010, is the F of restraint competition count code; When CLK brings out second pulse now, the 8 bit data ring shift rights of shift register A once, become 00011111, the 8 bit data ring shift rights of shift register B once, become 11000111, the output code d3d2d1d0 that latch LB4 negate this moment, LA4 negate, LB0, LA0 constitute is 1010, is the E of restraint competition count code; When CLK brings out the 3rd pulse now, the 8 bit data ring shift rights of shift register A once, become 00001111, the 8 bit data ring shift rights of shift register B once, become 01100011, latch LB4 negate this moment, the LA4 negate, LB0, the output code d3d2d1d0 that LA0 constitutes is 1000, be the D of restraint competition count code, go on according to this, when CLK brings out the 15th pulse now, the 8 bit data ring shift rights of shift register A once, become 11111111, the 8 bit data ring shift rights of shift register B once, become 00111001, latch LB4 negate this moment, the LA4 negate, LB0, the output code d3d2d1d0 that LA0 constitutes is 0001, be 1 of restraint competition count code, when CLK brings out the 16th pulse now, the 8 bit data ring shift rights of shift register A once, become 01111111, the 8 bit data ring shift rights of shift register B once become 00011100, this and the characteristic sequence that is initially preset by initialize switch are identical, so latch LB4 negate this moment, the LA4 negate, LB0, the output code d3d2d1d0 that LA0 constitutes is 0000, is 0 of restraint competition count code, the counting of a beginning new round.

It more than is the realization restriction competition counting coding techniques scheme of a reverse phase shift.

The core concept of this programme is according to the characteristic sequence of this restriction competition counting coding, makes up two groups of shift registers, adopts the mode of cyclic shift, realizes the tally function of pulse.

The invention has the beneficial effects as follows, can adopt better simply shift circuit to realize the counting coding circuit, and this counting circuit has the characteristics of restriction competition, has guaranteed the reliability of enumeration data, has higher utilization to be worth in having the counting circuit of extensive use.

Claims (4)

1, a kind of restraint competition count code circuit of mode of reverse phase shift, comprise 8 bit shift register (A), 8 bit shift register (B), 4 bit code output registers (C), initialization initialize switch (D), initialization initialize switch (E), phase inverter (F, G, H, J) is characterized in that

The highest order of shift register (A) and lowest order are end to end by phase inverter (F), the highest order of shift register (B) and lowest order are end to end by phase inverter (G), pulse input signal connects the displacement control port (CLK) of shift register (A) and shift register (B) respectively, shift register (A) initialize switch (D) that is initialised is predisposed to fixing characteristic sequence 01111111, shift register (B) initialize switch (E) that is initialised is predisposed to fixing characteristic sequence 00011100, the 4th the highest input positions of data (d3) by phase inverter (J) and sign indicating number output register (C) from low to high of shift register (B) and line output are connected, the 4th data time high-order (d2) by phase inverter (H) and sign indicating number output register C of the little-endian of shift register (A) and line output are connected, the 0th inferior low level (d1) of the data with sign indicating number output register (C) of the lowest order of shift register (B) and line output is connected, the 0th data lowest order (d0) with sign indicating number output register (C) of the lowest order of shift register (A) and line output is connected, and exports 4 restraint competition count codes to low level (d0) by high-order (d3) by the output control terminal control of sign indicating number output register (C).

2, the restraint competition count code circuit of mode of reverse phase shift according to claim 1 is characterized in that,

Above-mentioned sign indicating number output register (C) adopts latch, above-mentioned shift register (A, B) serial input terminal (Ax, Bx) all link together respectively, the end of the serial input terminal (Ax) of shift register (A) by initialization initialize switch (D) is predisposed to characteristic sequence 01111111 with the input of serial by turn by the antitone sequence 11111110 of characteristic sequence of 8 bit data of shift register (A), the also line output highest order end (Q7) of above-mentioned shift register (A) connects the input of phase inverter (F), the output of phase inverter (F) is by the serial input terminal (Ax) of another termination shift register (A) of initialization initialize switch (D), the end of the serial input terminal (Ax) of shift register (B) by initialization initialize switch (E) is predisposed to characteristic sequence 00011100 with the input of serial by turn by the antitone sequence 00111000 of characteristic sequence of 8 bit data of shift register (B), the also line output highest order end (Q7) of shift register (B) connects the input of phase inverter (G), the output of phase inverter (G) is by the serial input terminal (Ax) of another termination shift register (B) of initialization initialize switch (E), shift register (A, B) clock end (CLK) all links together, connect the step-by-step counting input simultaneously, shift register (A, reset terminal B) (

) also all linking together connects high potential, connect simultaneously latch (C) clear terminal (

), the parallel output terminal (Q0) of shift register (A) connects the data input pin (D1) of latch (C), the parallel output terminal (Q0) of shift register (B) connects the data input pin (D2) of latch (C), the parallel output terminal (Q4) of shift register (A) connects the data input pin (D3) of latch (C) by phase inverter (H), the parallel output terminal (Q4) of shift register (B) connects the data input pin (D4) of latch (C) by phase inverter (J), the output control terminal of latch (C) ( With ) link together, its output (Q4, Q3, Q2, Q1) is arranged the restraint competition count code (d3, d2, d1, d0) of 4 of outputs from high to low.

3, according to the restraint competition count code circuit of the described mode of reverse phase shift of claim l, it is characterized in that,

Comprise by two groups of 8 latchs, two groups of 8 initialize switches, and two groups of two groups of each 8 data latch units that two-phase 8 bit shift control switchs constitute, bits per inch comprises an initialize switch according to latch units, a clock switch and a latch, latch is made up of two end to end phase inverters, the input of latch connects the input of initialize switch and the input of clock switch respectively, the output of latch is received the input of the clock switch of next data latch unit, be linked in sequence into the 1st～8 data latch units successively, the output of the 8th data latch units constitutes one first group above-mentioned 8 bit shift register (A) by the clock switch input that phase inverter F receives the 1st data latch units, two-phase 8 bit shift control switchs are realized by phase inverter respectively, the control end of the transmission gate that 8 two-phase shift switchings are controlled respectively links together separately as the input of pulse, the constituted mode of second group of above-mentioned 8 bit shift register (B) and first group are identical, the output of its 8th data latch units is received the clock switch input of the 1st data latch units by phase inverter (G), first group of shift register (A) is initialized as characteristic sequence 01111111 by initialize switch, second group of shift register (B) is initialized as characteristic sequence 00011100 by initialize switch, the output of sign indicating number is phase inverter (H) output by the 4th the data latch units (LB4) of second group of shift register (B), phase inverter (J) output of the 4th the data latch units (LA4) of first group of shift register (A), the output of the 0th the data latch units (LB0) of second group of shift register (B), the output of the 0th the data latch units (LA0) of first group of shift register (A) is formed, and forms to arrange 4 restraint competition count code (d3 of output from high to low, d2, d1, d0).

4, the restraint competition count code circuit of mode of reverse phase shift according to claim 1 is characterized in that,

When each count pulse arrived, two 8 bit shift register synchronous circulation moved to right one and are the countdown mode; When each count pulse arrived, two 8 bit shift register synchronous circulation moved to left one for increasing progressively counting mode.

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