CN202948443U - Image storage controller for programmable logic controller (PLC) information input, collection and reading - Google Patents

Abstract

An image storage controller for programmable logic controller (PLC) information input, collection and reading comprises a PLC input port and image storage module, a command decoding and operation address information module, a high-speed input bit information control module, bit information reading control module, a data transmission control module, and a data combination storage module. A field programmable gate array (FPGA) is applied to the controller to design a hard-wired control circuit, under the effect of input collecting commands, a pulse distributor is started to emit inner timing sequence pulses, and the data transmission control module automatically completes the combination of all input data with four bits as a set under the control of the inner timing sequence pulses and stores the combination into a data combination storage according to order. In the processes of PLC user program executing bit input bit information reading, high-speed bit information reading and data reading commanding, a WR signal is written into a command, an input element X number and an X class value, and an RD signal sends selected bit information or selected data to a system data bus, and therefore speed of PLC executing instruction sequence is improved.

Description

The PLC input gathers and reading information reflection memory controller

Technical field

The utility model relates to a kind of PLC input and gathers and reading information reflection memory controller, relates in particular to that a kind of hardwired PLC input gathers with FPGA and realizes reading and storing the input message controller based on FPGA parallel work-flow circuit.

Background technology

The control of the input port of PLC mainly adopts input port to be connected with the input modulate circuit, the output of input modulate circuit is connected with the input end of mapped memory, the data output end of mapped memory is connected with the data bus of PLC system, under the effect of the data acquisition signal of PLC input acquisition phase, input port information is once read in mapped memory.In PLC user program implementation, the reflection storer is carried out read operation, the byte/word at information place, need input to be processed position is read in the PLC processor, then application software is taken out this information, maybe need to read in take four information as the information of one group or organize take the information of four information as one group more, the byte/word that will need equally the information of one group to be processed or organize the input message place more is read in the PLC processor, and then application software is taken out one or more groups information; Be directly input message to be read in the PLC processor with the form of byte/word from input modulate circuit output port for the execution of inputting at a high speed instruction, then application software is taken out this information; In using the system of ARM microprocessor as the PLC control core, because ARM does not have special position processing instruction, when PLC actuating logic operational order, obtain whole 16 or whole 32 input messages that comprise this soft element information from mapped memory, then obtain the required position information participation logical operation of this input soft element by displacement mode; The execution of input position information command need to be read in the register of PLC processor from input modulate circuit output port with the form of byte/word at a high speed, obtain this input soft element position information by displacement mode, use the ARM microprocessor as the system of PLC control core, its processing procedure of PLC need to be carried out many ARM instructions, the speed of PLC being carried out user program exerts an influence, and is unfavorable for improving the speed that PLC carries out user program.

Summary of the invention

The purpose of this utility model is to provide a kind of PLC input and reading information reflection storage control circuit and time schedule controller thereof that can realize parallel work-flow; This controller is independently completed the combination of 4 one group input data under inner time sequential pulse is controlled, be stored in order in data-carrier store, the PLC user program is carried out in an input information, high speed position information and data read command process, write order, input element X numbering and X class value to controller, position information or the data chosen are sent to system data bus, can greatly improve the speed that PLC carries out instruction sequence, the problems referred to above that exist to solve prior art.

The technical scheme that solves the problems of the technologies described above is: a kind of PLC input collection and reading information reflection memory controller comprise that PLC input port and reflection memory module, command decoder and operation address information module, high speed are inputted a position information control module, position information reads control module, Data Transmission Controlling module and data combination memory module;

Described PLC input port reads control module and is connected with the Data Transmission Controlling module with operation address information module, a high speed input information control module, position information with command decoder respectively with the reflection memory module; Described PLC input port carries out light isolation, level conversion, filtering with the reflection memory module with PLC input port information, and under the effect of input acquisition storage n position input message;

Also input position information control module, position information read control module to described command decoder respectively with at a high speed, the Data Transmission Controlling module is connected memory module with data and is connected with the operation address information module; When the address value of system address bus is that the PLC input gathers the address value with reading information reflection memory controller, described command decoder and operation address information module are under the effect of the WR of system signal, the memory command word is through the decoding output command signal, and m position X numbering and 3 X class values of storage input X element are also exported;

A described high speed input position information control module is carried out a position information reading order at a high speed, with a certain position communication of the PLC input port D0 position to system data bus, realizes an information acquisition at a high speed;

Institute's rheme information reads control module execute bit information reading order, and the X soft element information of numbering appointment according to m position X is transferred to the D0 position of system data bus from PLC input port and reflection memory module;

Described Data Transmission Controlling module also is connected with data combination memory module; Described Data Transmission Controlling module is under the time sequential pulse effect that this inside modules produces, be one group with the n position information of PLC input port and reflection memory module storage according to 4 information, the mode of initial X numbering and 3 X class value institute standards is controlled and is transferred to data and makes up memory module and stored;

Described data combination memory module canned data is to be one group according to 4 position information, the mode of initial X numbering and 3 X class value institute standards is arranged, during the executing data reading order, under the effect of the RD of system signal, the s bit address that is combined into according to initial X numbering and 3 X class values reads this address location data transmission and arrives system data bus, the span of said n, m and s is: n be 64 or 32, m be 6 or 5, s be 7 or 6; When n is 64, m=6, s=7; When n is 32, m=5, s=6.

Its further technical scheme is: described PLC input port comprises that with the reflection memory module PLC input port, input signal conditioning circuit, FPGA input port and n enter the n position and go out mapped memory; The PLC input port is connected with the input end of PLC input modulate circuit as the link of the outside input switch of PLC or device, the output terminal of PLC input modulate circuit is connected with an end of FPGA input port, and PLC input port information is carried out filtering, photoelectricity isolation and level conversion; The other end of FPGA input port and the input end of input position information control module at a high speed, n enter the n bit data input end that the n position goes out mapped memory and connect;

Described n enters n bit data output terminal that the n position goes out mapped memory and reads control module with position information and be connected with the Data Transmission Controlling module; Input acquisition input end is connected with the operation address information module with command decoder;

Described n enters the n position and goes out mapped memory under the effect of input acquisition signal, and the information exchange that PLC is inputted modulate circuit output is crossed the FPGA input port and is stored in n and enters the n position and go out in mapped memory; Described n enters the n position and goes out the n bit data that mapped memory stores and directly output to n bit data output terminal, and the span of said n is: n is 64 or 32.

Its further technical scheme is: described command decoder and operation address information module comprise module's address recognizer, command register, operating characteristics code translator, not gate I and with the door I; The module's address input end of module's address recognizer is connected with system address bus, if the address value of system address bus is the address value of this module, the CS signal of module's address recognizer output is " 0 ", otherwise is " 1 "; The CS signal output part of module's address recognizer is connected input end and is connected with the not gate I with the Enable Pin of command register;

The reset terminal of command register is connected output terminal and is connected with the not gate I; The command information input end is connected with system data bus, the command information that the system of acceptance sends, m position X number information and 3 X class value information datas; The write signal input end is connected with system WR signal; The command information output terminal is connected with the command information input end of operating characteristics code translator; M position X numbers output terminal and inputs a position information control module with high speed respectively, and position information reads control module and is connected the memory module connection with data; 3 X class value output terminals are connected with data combination memory module; When described command register was enabled, under the effect of " 1 " → " 0 " signal, with the command information of system data bus, m position X number information and 3 X class value information were stored in command register at the WR of system; When not gate I output terminal is " 0 ", reset command register, when command register was reset, the command information output terminal was " 000 ";

The command information input end of operating characteristics code translator is connected with the command information output terminal of command register, obtains command code information; 5 order output terminals of operating characteristics code translator are respectively with PLC input port and reflection memory module, at a high speed an input position information control module, position information read control module, the Data Transmission Controlling module is connected memory module with data and is connected, the reset command output terminal be connected with an input end of door I; When being output as " 000 " when command register is reset, 5 of the operating characteristics code translator signals that order output terminal is all are " 1 "; When command register is output as effective order information, there is an order output terminal to be " 0 " in 5 of the operating characteristics code translator order output terminals, other 4 order output terminals are " 1 ";

Be connected with the systematic reset signal input end with another input end of door I; Be connected with data combination memory module with the reset command output terminal of operation address information module as command decoder with the output terminal of door I, the span of above-mentioned m is: m is 6 or 5.

Its further technical scheme is: a described high speed input information control module comprises 3-8 code translator, triple gate group or door I and triple gate I; The high speed position information reading order output terminal of the high speed position information reading order input end of 3-8 code translator and command decoder and operation address information module is connected; 3 encoded radio input ends of X numbering are connected with low 3 output terminals of m position X numbering of operation address information module with command decoder; 8 decoding value output terminals are connected with 8 control ends of triple gate group;

8 input ends of triple gate group are connected with 8 ports of PLC input port with the FPGA input port of reflection memory module; The position information output is connected with the input end of triple gate I;

Or the high speed position information reading order output terminal of input end of door I and command decoder and operation address information module is connected, and another input end is connected with the RD signal wire of system; Or the output terminal of door I is connected with the control end of triple gate I;

The D0 position of the output terminal of triple gate I and system data bus is connected;

Described high speed input position information control module is carried out position information reading order at a high speed, according to low 3 triple gates that decoding gating triple gate group is corresponding of m position X numbering, under the effect of the RD of system signal, the position information output that PLC input port and the position information exchange of the FPGA input port corresponding ports of reflection memory module are crossed the triple gate group is transferred to the D0 position of system data bus, and the span of above-mentioned m is: m is 6 or 5.

Its further technical scheme is: institute's rheme information reads control module and comprises that n enters 4 and goes out control module, 4 and enter 1 and go out control module or door II and triple gate II; N enters 4 n bit data input ends that go out control module and PLC input port and the n of reflection memory module and enters the n bit data output terminal that the n position goes out mapped memory and be connected; 4 bit data output terminals and 4 enter 14 bit data input end that go out control module and are connected; The m position X high u of the numbering position output terminal of the input end of 4 bit data OPADD and command decoder and operation address information module is connected;

4 enter 11 information output that goes out control module is connected with the input end of triple gate II; The input end of 1 information output address is connected with low 2 output terminals of m position X numbering of operation address information module with command decoder;

Or the door II an input end be connected with the position information reading order output terminal of operation address information module with command decoder, another input end is connected with the RD of system signal line end; Output terminal is connected control end and is connected with the triple gate II;

The D0 position of the output terminal of triple gate II and system data bus is connected;

Institute's rheme information reads control module execute bit information reading order, n enters 44 bit data that go out the specified storage unit in control module output m position X numbering high u position, 4 enter 1 position information that goes out low 2 the specified storage bit unit of control module output m position X numbering, the bit location content delivery of m position X numbering appointment is arrived the D0 position of system data bus under the effect of the RD of system signal, the span of said n, m and u is: n is 64 or 32, m be 6 or 5, u be 4 or 3; When n is 64, m=6, u=4; When n is 32, m=5, u=3.

Its further technical scheme is: described Data Transmission Controlling module comprises that address and time-sequence control module, n enter 4 and go out memory module, 4 and enter 32 and go out memory module and pulsqe distributor;

Described address and time-sequence control module and n enter 4 and go out memory module, 4 and enter 32 and go out memory module, pulsqe distributor, command decoder and be connected memory module with the operation address information module with data and be connected; Described address and time-sequence control module are completed n and are entered 4 data readings that go out memory module under the time sequential pulse effect that pulsqe distributor produces, 4 enter 32 goes out the control operation that memory module and data combination memory module data write and reset;

Described n enters 4 and goes out memory module and also enter the n position with PLC input port and the n of reflection memory module and go out mapped memory, 4 and enter 32 4 bit data input ends that go out memory module and be connected with pulsqe distributor; Described n enters 4 and goes out memory module storage n position information, and n position information is take 4 information as one group of output storage unit that forms 4 bit data, and the n value is 64, and its 4 one group data storage cell address is from 0000H-1111H; The n value is 32, and its 4 one group data storage cell address is from 000H-111H;

Described 4 enter 32 go out memory module also with the pulse of pulsqe distributor 3. output terminal be connected memory module with data and be connected; Described 4 enter 32 4 one group data storage cell addresses that go out memory module from 000H-111H;

Described pulsqe distributor also is connected with data combination memory module, the clock pulse input terminal of pulsqe distributor is connected with system clock, the starting impulse input end is connected with the input acquisition output terminal of operation address information module with command decoder, and the pulse of loop start pulse input end and pulsqe distributor 7. output terminal is connected; Described pulsqe distributor is as the inside sequential control of PLC input collection with the data writing combination memory module data of reading information reflection memory controller, startup work under the effect of input acquisition signal, according to sequential output pulse 1., pulse 2., pulse 3., pulse 4., pulse is 5., pulse 6., pulse is 7.; Under pulse effect 7., circulation output pulse 2., pulse 3., pulse 4., pulse 5., pulse 6., pulse 7., until pulsqe distributor is reset;

Described address and time-sequence control module comprise initial value address counter, read address counter, group number counter, write address counter, data compound storage address counter, with a door II, with a door III, with a door IV, not gate II, not gate III or door III or door IV or door V and or the door VI; The reset signal input end of initial value address counter is connected with the output terminal with the door IV, the count pulse input end be connected the output terminal of door III and connect, the u position of the u position counting initial value output terminal of initial value address counter and read address counter is counted the initial value input end and is connected;

The reset signal input end of read address counter is connected with the output terminal with the door IV, the presetting pulse input end be connected the output terminal of door IV and connect, count pulse input end and pulse 5. output terminal are connected; U bit address output terminal and the n of 4 bit data of read address counter enters 4 u bit address input ends that go out input 4 bit data of memory module and is connected;

The reset signal input end of group number counter is connected with the output terminal with the door II, and count pulse input end and pulse 2. output terminal are connected, and the counting of group number counter overflows output terminal is connected input end and connects with not gate, and the counting overflow value of group number counter is 08H;

The RESET input of write address counter is connected with output terminal with the door III, count pulse input end and pulse 5. output terminal are connected, and 3 of write address counter write 4 bit data address output ends and 4 and enter 32 4 bit data address input ends that go out memory module and be connected;

The RESET input of data compound storage address counter is connected with the output terminal with the door IV, count pulse input end and pulse 5. output terminal are connected, counting overflows output terminal is connected input end and connects with not gate, the s bit address output terminal of input 32 bit data of data compound storage address counter is connected with the s bit address input end of input 32 bit data of data combination memory module, and the counting overflow value of data compound storage address counter is wH;

With two input ends of door II respectively with the door IV and or the output terminal of door V be connected;

With two input ends of door III respectively with the door IV and or the output terminal of door IV be connected;

With two input ends of door IV respectively with the input acquisition output terminal of command decoder and operation address information module and or the output terminal of door VI be connected, with the output terminal of door IV as the module reset signal, when the module reset signal is " 0 ", the initial value address counter that resets, read address counter, group number counter, write address counter and data compound storage address counter;

The output terminal of not gate II be connected input end of door III or door IV an input end and or an input end of door V connect; The output of not gate II is as the counting spill over of group number counter;

The output terminal of not gate III be connected input end of door VI and connect;

Or another input end and the pulse of door III 3. output terminal be connected, or the output terminal of an III also enters 32 reset signal input ends that go out memory module and is connected with 4;

Or another input end and the pulse of door IV 4. output terminal be connected;

Or another input end and the pulse of door V 5. output terminal be connected;

Or another input end and the pulse of door VI 6. output terminal be connected, or the output terminal of door VI also waits for that with resetting of pulsqe distributor the enabling signal input end is connected, and the span of said n, u, s and w is: n be 64 or 32, u be 4 or 3, s be 7 or 6, w be 79 or 39; When n is 64, m=6, u=4, s=7, w=79; When n is 32, m=5, u=3, s=6, w=39.

its further technical scheme is: described data combination memory module comprise data compound storage ,-1 counter and or the door VII, the s bit address input end of data compound storage input 32 bit data is connected with the s bit address output terminal of input 32 bit data of data compound storage address counter, 32 bit data input ends and 4 enter 32 32 bit data output terminals that go out memory module and are connected, data write signal input end and pulse 4. output terminal are connected, the low 3 bit address input end A2 A1 A0 of 32 output data addresses are connected with the terminal count output of-1 counter, the output terminal that high u bit address input end and the command decoder of 32 output data addresses and the m position X of operation address information module number high u position is connected, the n value is 64, u=4, its high 4 bit address input ends are A6 A5 A4 A3, the n value is 32, u=3, and its high 3 bit address input ends are A5 A4 A3, the data reading signal input part be connected the output terminal of door VII and connect, 32 bit data output terminals of data compound storage are connected with system data bus, and the reset signal input end is connected with the reset command output terminal of operation address information module with command decoder,

The count value input end of-1 counter is connected with 3 X class value output terminals of operation address information module with command decoder, and-1 count pulse input end is connected with the data read command output terminal of operation address information module with command decoder;

Or the door VII two input ends be connected with data read command output terminal and system's RD signal of operation address information module with command decoder respectively, the span of said n, m, u and s is: n be 64 or 32, m be 65, u be 4 or 3, s be 7 or 6; When n is 64, m=6, u=4, s=7; When n is 32, m=5, u=3, s=6.

Its further technical scheme be: under the effect of the input collection signal of command decoder and operation address information module, the initial value address counter of described Data Transmission Controlling module, read address counter, group number counter, write address counter and data compound storage address counter are reset and the work of starting impulse divider;

When the output pulse 1. the time:

It is effective that the n position enters 4 n bit data write signals that go out memory module, n entered n bit data that the n position goes out mapped memory write the n position and enter 4 and go out in memory module;

When the output pulse 2. the time:

It is effective that n enters 44 bit data read output signals that go out memory module, according to the u bit address value of input 4 bit data of read address counter output, 4 bit data is transferred to 4 and enters 32 4 bit data input ends that go out memory module;

The group number counter adds 1, i.e. K value+1;

When the output pulse 3. the time:

4 to enter 32 4 bit data write signals that go out memory module effective, writes 4 bit data address values according to 3 of write address counter output and 4 bit data are written to 4 enter 32 and go out memory module;

If the count value of group number counter is 08H when sending spill over, the initial value address counter adds 1, namely enters next group Y numbering first address, resets 4 to enter 32 and go out memory module, and making 32 storage unit is all " 0 ";

When the output pulse 4. the time:

32 bit data write signals of data compound storage are effective, enter 32 32 bit data data writing compound storages that go out memory module output according to 32 bit data address values of data compound storage address counter output s position with 4;

If the count value of group number counter is 08H when sending spill over, send presetting pulse to read address counter, the counting initial value of initial value address counter output is preset to read address counter, make the value of read address counter output u bit address be the counting initial value, write address counter resets;

When the output pulse 5. the time:

Write address counter adds 1, and read address counter adds 1, and data compound storage address counter adds 1;

If the count value of group number counter is 08H when sending spill over, the group number that resets counter;

When the output pulse 6. the time:

If the count value of data compound storage address counter is wH when sending spill over, the initial value address counter that resets, read address counter, group number counter, write address counter, data compound storage address counter and pulsqe distributor;

When the output pulse 7. the time:

Loop start pulsqe distributor, pulsqe distributor send 2. signal of pulse, and the span of said n, u, s and w is: n be 64 or 32, u be 43, s be 7 or 6, w be 79 or 39; When n is 64, m=6, u=4, s=7, w=79; When n is 32, m=5, u=3, s=6, w=39.

Due to the above structure of employing, the PLC of the utility model inputs and reads input message reflection storage control and has following beneficial effect:

One. can independently complete combination, storage to input message, not take the time of PLC system

In the utility model, controller has the function of 4 one group input data of autonomous tissue, starting impulse divider under the effect of input collection signal, the Data Transmission Controlling module is under inner time sequential pulse effect, independently complete the combination of all data of 4 one group input data, and be stored in order in the data compound storage.

Two. operating speed is fast

In the utility model, no matter be to read an input information, still read input position information at a high speed, only need to will order under the effect of the WR of system signal, input element X numbers and writes command register, the bit location information of choosing sent to the D0 position of system data bus under the effect of system's RD signal subsequently; Be that PLC is when execution need to be read the input soft element or read the instruction of inputting at a high speed soft element participation computing, 2 clocks of system can be read the position information state of input soft element, rather than read the byte at input soft element bit location place or the data of word cell, then read this information state according to the bit location address from byte or word cell, improved operating speed.

Three. during program is carried out, reading out data is quick, has improved the speed of executive routine

In the utility model, in the process of input data instruction is read in the execution of PLC program, controller is chosen by system address, the designated command that to read the input data under the effect of the WR of system signal writes command register, and the location information with the data compound storage chosen under the effect of system's RD signal subsequently sends on system data bus; Avoided carrying out in the process of the instruction of reading the input data, need to read the byte of input soft element or the data of word cell, then according to the requirement of instruction from byte or word cell sense data, reduce the operation that the PLC microprocessor data is processed, improved the speed that the PLC program is carried out;

Four. cost performance is high

The utility model under the inner time sequential pulse effect that produces of controller, has the function of 4 one group input data of autonomous tissue take the hard connection control circuit of FPGA as core; In PLC user program implementation, read input position, a certain position information, high speed input position, a certain position information, read two clock period that the input data all only need the PLC system, improved the speed of PLC execution instruction sequence, make control function and the property enhancement of this small-sized programmable controller, possess higher cost performance.

Below in conjunction with drawings and Examples, the PLC input collection of the utility model and the technical characterictic of reading information reflection memory controller are further described.

Description of drawings

Fig. 1: the PLC input of the utility model gathers the system architecture diagram with reading information reflection memory controller;

Fig. 2: the PLC input of the utility model gathers and the PLC input port of reading information reflection memory controller and the hardware connection layout of reflection memory module;

Fig. 3: the PLC input collection of the utility model and command decoder and the operation address information module of reading information reflection memory controller, a high speed input information control module, position information reads the hardware connection layout of control module;

Fig. 4: the PLC input of the utility model gathers and the Data Transmission Controlling module of reading information reflection memory controller and the hardware connection layout of data combination memory module;

Fig. 5: the PLC of the utility model input gather with reading information reflection memory controller the pulse output waveform figure of pulsqe distributor;

Fig. 6: the utility model embodiment two PLC inputs gather the system architecture diagram with reading information reflection memory controller.

In figure:

I-PLC input port and reflection memory module, II-command decoder and operation address information module, III-high speed input information control module, IV-position information reads control module, V-Data Transmission Controlling module, V A-address and time-sequence control module, V B-64 enter 4 and go out memory module, V C-4 enter 32 and go out memory module, V D pulsqe distributor, VI-data combination memory module;

1-PLC input port, 2-input signal conditioning circuit, 3-FPGA input port, 4-64 enter 64 goes out mapped memory, 5-module's address identification, 6-command register, 7-operating characteristics code translator, 8-not gate I, 9-with an I,

10-3-8 code translator, 11-triple gate group, 12-or the door I, 13-triple gate I, 14-64 enter 4 goes out control module, 15-4 enter 1 goes out control module, 16-or the door II, 17-triple gate II, 18-initial value address counter, 19-read address counter, 20-group number counter, 21-write address counter, 22-data combination memory address counter, 23-with the door II, 24-with the door III, 25-with the door IV, 26-not gate II, 27-not gate III, 28-or the door III, 29-or the door IV, 30-or the door V, 31-or the door VI, 32-data compound storage, 33--1 counters, 34-or the door VII.

In figure: n be 64 or 32, u be 43, s be 7 or 6, w be 79 or 39; When n is 64, m=6, u=4, s=7, w=79; When n is 32, m=5, u=3, s=6, w=39.

The module port explanation

PLC input port and reflection memory module I: I a: input acquisition input end; I b:n bit data output terminal; I c:X0 output port; I d:X1 output port; I e:X2 output port; I f:X3 output port; I g:X4 output port; I h:X5 output port; I i:X6 output port; I j:X7 output port;

Command decoder and operation address information module II: II a: input acquisition output terminal, II b: a high speed information reading order output terminal, II c: position information reading order output terminal, II d: data read command output terminal, II e: reset command output terminal, II f:X numbers output terminal, II g:X class value output terminal, II h: data bus input end, II i: systematic reset signal input end, II j: write signal input end, II k: module's address input end;

Input at a high speed position information control module III: III a: a high speed information reading order input end, III b:X numbers 3 encoded radio input ends, III c:X0 input port; III d:X1 input port; III e:X2 input port; III f:X3 input port; III g:X4 input port; III h:X5 input port; III i:X6 input port; III j:X7 input port; III k: a high speed information output, III l: system RD signal input part;

Position information reads control module IV: IV a: position information reading order input end, and IV b:n bit data input end, IV c:X numbers input end, IV d: position information output, IV e: system RD signal input part;

Data Transmission Controlling module V: V a:n bit data input end; V b:32 bit data output terminal; V c:s bit address output terminal; V d: input acquisition input end; V e: system clock input end; V f: pulse is output terminal 4.;

Address and time-sequence control module V A: V Aa:u bit address output terminal; V Ab: write 4 bit data address output ends; V Ac:s bit address output terminal; V Ad: input acquisition input end; V Ae:4 enters 32 and goes out memory module reset signal output terminal; V Af: pulsqe distributor reset signal output terminal; V A is 2.: pulse is input end 2.; V A is 3.: pulse is input end 3.; V A is 4.: pulse is input end 4.; V A is 5.: pulse is input end 5.; V A is 6.: pulse is input end 6.;

64 enter 4 goes out memory module V B: V Ba:n bit data input end; V Bb:4 bit data output terminal; V Bc:u bit address input end; V Bd: pulse is input end 2.;

4 enter 32 goes out memory module V C: V Ca:32 bit data output terminal; V Cb:4 bit data input end; V Cc:4 bit data address input end; V Cd: reset signal input end; V C is 3.: pulse is input end 3.;

Pulsqe distributor V D: V Da: reset and wait for the enabling signal input end; V Db: starting impulse input end; V Dc: clock pulse input terminal; V Dd: loop start pulse input end; V D is 1.: pulse is output terminal 1.; V D is 2.: pulse is output terminal 2.; V D is 3.: pulse is output terminal 3.; V D is 4.: pulse is output terminal 4.; V D is 5.: pulse is output terminal 5.; V D is 6.: pulse is output terminal 6.; V D is 7.: pulse is output terminal 7.;

Data combination memory module VI: VI a:32 bit data output terminal; VI b: system RD signal input part; VI c: reset signal input end; VI d: high u bit address input end; VI e: count value input end; VI f:-1 count pulse input end; VI g:s bit address input end; VI h:32 bit data input end; VI is 4.: data write signal input end;

The span of said n, u and s is: n be 64 or 32, u be 4 or 3, s be 7 or 6; When n is 64, u=4, s=7; When n is 32, u=3, s=6.

Abbreviation explanation in literary composition, in figure:

PLC-Programmable Logical Controller, programmable logic controller (PLC) is called for short Programmable Logic Controller;

FPGA-Field Programmable Gate Array, field programmable gate array;

RD signal-ReaD signal, read signal;

CS signal-Chip Select signal, chip selection signal;

WR signal-WRite signal, write signal;

D0 position-Data0, the 0th bit location;

Embodiment

A kind of PLC input gathers and reading information reflection memory controller.

As shown in Figure 1, this PLC input collection and reading information reflection memory controller comprise that PLC input port and reflection memory module I, command decoder and operation address information module II, high speed are inputted a position information control module III, position information reads control module IV, Data Transmission Controlling module V and data combination memory module VI;

Described PLC input port reads the control module IV and is connected with Data Transmission Controlling module V with operation address information module II, a high speed input information control module III, position information with command decoder respectively with reflection memory module I; Described PLC input port carries out light isolation, level conversion, filtering with reflection memory module I with PLC input port information, and under the effect of input acquisition storage n position input message;

Also input position information control module III, position information read the control module IV to described command decoder respectively with at a high speed, Data Transmission Controlling module V is connected the memory module VI and is connected with data with operation address information module II; When the address value of system address bus is that the PLC input gathers the address value with reading information reflection memory controller, described command decoder and operation address information module II are under the effect of the WR of system signal, the memory command word is through the decoding output command signal, and m position X numbering and 3 X class values of storage input X element are also exported;

A described high speed input position information control module III is carried out a position information reading order at a high speed, with a certain position communication of the PLC input port D0 position to system data bus, realizes an information acquisition at a high speed;

Institute's rheme information reads control module IV execute bit information reading order, and the X soft element information of numbering appointment according to m position X is transferred to the D0 position of system data bus from PLC input port and reflection memory module I;

Described Data Transmission Controlling module V also is connected with data combination memory module VI; Described Data Transmission Controlling module V is under the time sequential pulse effect that this inside modules produces, be one group with the n position information of PLC input port and the storage of reflection memory module I according to 4 information, the mode of initial X numbering and 3 X class value institute standards is controlled and is transferred to data and makes up the memory module VI and stored;

described data combination memory module (VI) canned data is to be one group according to 4 position information, the mode of initial X numbering and 3 X class value institute standards is arranged (referring to subordinate list one " the PLC input of the utility model embodiment one gathers with the data of the data compound storage of reading information reflection memory controller and stores permutation table ", subordinate list two " the PLC input collection of the utility model embodiment two and the data storage permutation table of the data compound storage of reading information reflection memory controller "), during the executing data reading order, under the effect of the RD of system signal, the s bit address that is combined into according to initial X numbering and 3 X class values reads this address location data transmission and arrives system data bus, said n, the span of m and s is: n is 64 or 32, m is 6 or 5, s is 7 or 6, when n is 64, m=6, s=7, when n is 32, m=5, s=6.

As shown in Figure 2, described PLC input port and reflection memory module I comprise that PLC input port 1, input signal conditioning circuit 2, FPGA input port 3 and n enter the n position and go out mapped memory 4; PLC input port 1 is connected with the input end of PLC input modulate circuit 2 as the link of the outside input switch of PLC or device, the output terminal of PLC input modulate circuit 2 is connected with an end of FPGA input port 3, and PLC input port 1 information is carried out filtering, photoelectricity isolation and level conversion; The other end of FPGA input port 3 and the input end of input position information control module III at a high speed, n enter the n bit data input end that the n position goes out mapped memory 4 and connect;

Described n enters n bit data output terminal that the n position goes out mapped memory 4 and reads the control module IV with position information and be connected with Data Transmission Controlling module V; Input acquisition input end is connected with operation address information module II with command decoder;

Described n enters the n position and goes out mapped memory 4 under the effect of input acquisition signal, and the information exchange that PLC is inputted modulate circuit 2 outputs is crossed FPGA input port 3 and is stored in n and enters the n position and go out in mapped memory 4; Described n enters the n position and goes out the n bit data that mapped memory 4 stores and directly output to n bit data output terminal, and the span of said n is: n is 64 or 32.

As shown in Figure 3, described command decoder and operation address information module II comprise module's address recognizer 5, command register 6, operating characteristics code translator 7, not gate I 8 and with door I 9; The module's address input end of module's address recognizer 5 is connected with system address bus, if the address value of system address bus is the address value of this module, the CS signal of module's address recognizer 5 outputs is " 0 ", otherwise is " 1 "; The CS signal output part of module's address recognizer 5 is connected with the input end that the Enable Pin of command register 6 is connected with the not gate I;

The output terminal that the reset terminal of command register 6 is connected with the not gate I connects; The command information input end is connected with system data bus, the command information that the system of acceptance sends, m position X number information and 3 X class value information datas; The write signal input end is connected with system WR signal; The command information output terminal is connected with the command information input end of operating characteristics code translator 7; M position X numbers output terminal and inputs a position information control module III with high speed respectively, and position information reads the control module IV and is connected the connection of memory module VI with data; 3 X class value output terminals are connected with data combination memory module VI; When described command register 6 was enabled, under the effect of " 1 " → " 0 " signal, with the command information of system data bus, m position X number information and 3 X class value information were stored in command register 6 at the WR of system; When not gate I 8 output terminals are " 0 ", the reset command register 6, and when command register 6 was reset, the command information output terminal was " 000 ";

The command information input end of operating characteristics code translator 7 is connected with the command information output terminal of command register 6, obtains command code information; 5 order output terminals of operating characteristics code translator 7 are respectively with PLC input port and reflection memory module I, an input position information control module III, position information read the control module IV at a high speed, Data Transmission Controlling module V is connected the memory module VI and is connected with data, the reset command output terminal be connected with an input end of door I 9; When command register 6 is reset when being output as " 000 ", 5 of operating characteristics code translator 7 signals that order output terminal is all are " 1 "; When command register 6 is output as effective order information, there is an order output terminal to be " 0 " in 5 of operating characteristics code translator 7 order output terminals, other 4 order output terminals are " 1 ";

Be connected with the systematic reset signal input end with another input end of door I 9; Be connected with data combination memory module VI with the reset command output terminal of operation address information module II as command decoder with the output terminal of door I 9, in Fig. 3, the span of m is: m is 6 or 5.

Described high speed input position information control module III comprises 3-8 code translator 10, triple gate group 11 or door I 12 and triple gate I 13; The high speed position information reading order output terminal of the high speed position information reading order input end of 3-8 code translator 10 and command decoder and operation address information module II is connected; 3 encoded radio input ends of X numbering are connected with low 3 output terminals of m position X numbering of operation address information module II with command decoder; 8 decoding value output terminals are connected with 8 control ends of triple gate group 11;

8 input ends of triple gate group 11 are connected with 8 ports of PLC input port with the FPGA input port 3 of reflection memory module I; The position information output is connected with the input end of triple gate I 13;

Or the high speed position information reading order output terminal of input end of door I 12 and command decoder and operation address information module II is connected, and another input end is connected with the RD signal wire of system; Or the output terminal of door I 12 is connected with the control end of triple gate I 13;

The D0 position of the output terminal of triple gate I 13 and system data bus is connected;

Described high speed input position information control module III is carried out position information reading order at a high speed, a triple gate according to low 3 decoding gating triple gate group 11 correspondences of m position X numbering, under the effect of the RD of system signal, the position information output that PLC input port and the position information exchange of FPGA input port 3 corresponding ports of reflection memory module I are crossed triple gate group 11 is transferred to the D0 position of system data bus; Referring to Fig. 3, in figure, the span of m is: m is 6 or 5.

Institute's rheme information reads the control module IV and comprises that n enters 4 and goes out control module 14,4 and enter 1 and go out control module 15 or door II 16 and triple gate II 17; N enters 4 n bit data input ends that go out control module 14 and PLC input port and the n of reflection memory module I and enters the n bit data output terminal that the n position goes out mapped memory 4 and be connected; 4 bit data output terminals and 4 enter 14 bit data input end that go out control module 15 and are connected; The m position X high u of the numbering position output terminal of the input end of 4 bit data OPADD and command decoder and operation address information module II is connected;

4 enter 11 information output that goes out control module 15 is connected with the input end of triple gate II 17; The input end of 1 information output address is connected with low 2 output terminals of m position X numbering of operation address information module II with command decoder;

Or the door II 16 an input end be connected with the position information reading order output terminal of operation address information module II with command decoder, another input end is connected with the RD of system signal line end; The control end that output terminal is connected with the triple gate II connects;

The D0 position of the output terminal of triple gate II 17 and system data bus is connected;

Institute's rheme information reads control module IV execute bit information reading order, n enters 44 bit data that go out the control module 14 specified storage unit in output m position X numbering high u position, 4 enter 1 position information that goes out control module 15 low 2 the specified storage bit unit of output m position X numbering, the bit location content delivery of m position X numbering appointment is arrived the D0 position of system data bus under the effect of the RD of system signal, referring to Fig. 3, the span of said n, m and u is: n be 64 or 32, m be 6 or 5, u be 4 or 3; When n is 64, m=6, u=4; When n is 32, m=5, u=3.

As shown in Figure 4, described Data Transmission Controlling module V comprises that address and time-sequence control module V A, n enter 4 and go out memory module V B, 4 and enter 32 and go out memory module V C and pulsqe distributor V D;

Described address and time-sequence control module V A and n enter 4 go out memory module V B, 4 enter 32 go out memory module V C, pulsqe distributor V D, command decoder is connected the memory module VI with operation address information module II and is connected with data; Described address and time-sequence control module V A complete n and enter 4 data readings that go out memory module V B under the time sequential pulse effect that pulsqe distributor V D produces, 4 enter 32 goes out the control operation that memory module V C and data combination memory module VI data write and reset;

Described n enters 4 and goes out memory module V B and also enter the n position with PLC input port and the n of reflection memory module I and go out mapped memory 4 and is connected with pulsqe distributor V D, 4 enters 32 4 bit data input ends that go out memory module V C and be connected 2. output terminal connection of pulse with pulsqe distributor V D; Described n enters 4 and goes out memory module V B storage n position information, and n position information is take 4 information as one group of output storage unit that forms 4 bit data, and when the n value is 64, its 4 one group data storage cell address is from 0000H-1111H; When the n value is 32, its 4 one group data storage cell address is from 000H-111H;

Described 4 enter 32 go out memory module V C also with the pulse of pulsqe distributor V D 3. output terminal be connected the memory module VI with data and be connected; Described 4 enter 32 4 one group data storage cell addresses that go out memory module V C from 000H-111H;

Described pulsqe distributor V D also is connected with data combination memory module VI, the clock pulse input terminal of pulsqe distributor V D is connected with system clock, the starting impulse input end is connected with the input acquisition output terminal of operation address information module II with command decoder, and the pulse of loop start pulse input end and pulsqe distributor V D 7. output terminal is connected; Described pulsqe distributor V D is as the inside sequential control of PLC input collection with the data writing combination memory module VI data of reading information reflection memory controller, startup work under the effect of input acquisition signal, according to sequential output pulse 1., pulse 2., pulse 3., pulse 4., pulse is 5., pulse 6., pulse is 7.; Under pulse effect 7., circulation output pulse 2., pulse 3., pulse 4., pulse 5., pulse 6., pulse 7., until pulsqe distributor V D is reset;

Described address and time-sequence control module V A comprise initial value address counter 18, read address counter 19, group number counter 20, write address counter 21, data compound storage address counter 22, with a door II 23, with a door III 24, with a door IV 25, not gate II 26, not gate III 27 or door III 28 or door IV 29 or door V 30 and or door VI 31; The reset signal input end of initial value address counter 18 is connected with the output terminal with door IV 25, the count pulse input end be connected the output terminal of door III 28 and connect, the u position of the u position counting initial value output terminal of initial value address counter 18 and read address counter 19 is counted the initial value input end and is connected;

The reset signal input end of read address counter 19 is connected with the output terminal with door IV 25, the presetting pulse input end be connected the output terminal of door IV 29 and connect, count pulse input end and pulse 5. output terminal are connected; U bit address output terminal and the n of 4 bit data of read address counter 19 enters 4 u bit address input ends that go out input 4 bit data of memory module V B and is connected;

The reset signal input end of group number counter 20 is connected with the output terminal with door II 23, count pulse input end and pulse 2. output terminal are connected, the counting of group number counter 20 overflows the input end connection that output terminal is connected with not gate, and the counting overflow value of group number counter 20 is 08H;

The RESET input of write address counter 21 is connected with output terminal with door III 24, count pulse input end and pulse 5. output terminal are connected, and 3 of write address counter 21 write 4 bit data address output ends and 4 and enter 32 4 bit data address input ends that go out memory module V C and be connected;

The RESET input of data compound storage address counter 22 is connected with the output terminal with door IV 25, count pulse input end and pulse 5. output terminal are connected, counting overflows the input end connection that output terminal is connected with not gate, the s bit address output terminal of input 32 bit data of data compound storage address counter 22 is connected with the s bit address input end of input 32 bit data of data combination memory module VI, and the counting overflow value of data compound storage address counter 22 is wH;

With two input ends of door II 23 respectively with door IV 25 and or the output terminal of door V 30 be connected;

With two input ends of door III 24 respectively with door IV 25 and or the output terminal of door IV 29 be connected;

With two input ends of door IV 25 respectively with the input acquisition output terminal of command decoder and operation address information module II and or the output terminal of door VI 31 be connected, with the output terminal of door IV 25 as the module reset signal, when the module reset signal is " 0 ", the initial value address counter 18 that resets, read address counter 19, group number counter 20, write address counter 21 and data compound storage address counter 22;

The output terminal of not gate II 26 be connected input end of door III 28 or door IV 29 an input end and or an input end of door V 30 connect; The output of not gate II 26 is as the counting spill over of group number counter 20;

The output terminal of not gate III 27 be connected input end of door VI 31 and connect;

Or another input end and the pulse of door III 28 3. output terminal be connected, or the output terminal of an III 28 also enters 32 reset signal input ends that go out memory module V C and is connected with 4;

Or another input end and the pulse of door IV 29 4. output terminal be connected;

Or another input end and the pulse of door V 30 5. output terminal be connected;

Or another input end and the pulse of door VI 31 6. output terminal be connected, or the output terminal of door VI 31 also waits for that with resetting of pulsqe distributor V D the enabling signal input end is connected, and the span of said n, u, s and w is: n be 64 or 32, u be 4 or 3, s be 7 or 6, w be 79 or 39; When n is 64, m=6, u=4, s=7, w=79; When n is 32, m=5, u=3, s=6, w=39.

described data combination memory module VI comprise data compound storage 32 ,-1 counter 33 and or door VII 34, the s bit address input end of data compound storage 32 input 32 bit data is connected with the s bit address output terminal of input 32 bit data of data compound storage address counter 22, 32 bit data input ends and 4 enter 32 32 bit data output terminals that go out memory module V C and are connected, data write signal input end and pulse 4. output terminal are connected, the low 3 bit address input end A2 A1 A0 of 32 output data addresses are connected with the terminal count output of-1 counter 33, the output terminal that high u bit address input end and the command decoder of 32 output data addresses and the m position X of operation address information module II number high u position is connected, the n value is 64, u=4, its high 4 bit address input ends are A6 A5 A4 A3, the n value is 32, u=3, and its high 3 bit address input ends are A5 A4 A3, the data reading signal input part be connected the output terminal of door VII 34 and connect, 32 bit data output terminals of data compound storage 32 are connected with system data bus, and the reset signal input end is connected with the reset command output terminal of command decoder with operation address information module II,

The count value input end of-1 counter 33 is connected with 3 X class value output terminals of operation address information module II with command decoder, and-1 count pulse input end is connected with the data read command output terminal of command decoder with operation address information module II;

Or the door VII 34 two input ends be connected with data read command output terminal and system's RD signal of operation address information module II with command decoder respectively, the span of said n, m, u and s is: n be 64 or 32, m be 65, u be 4 or 3, s be 7 or 6; When n is 64, m=6, u=4, s=7; When n is 32, m=5, u=3, s=6.(referring to Fig. 4)

The utility model PLC input gathers with the course of work of reading information reflection memory controller as follows:

Under the effect of the input collection signal of command decoder and operation address information module II, the initial value address counter 18 of described Data Transmission Controlling module V, read address counter 19, group number counter 20, write address counter 21 and data compound storage address counter 22 are reset and starting impulse divider V D work;

When the output pulse 1. the time:

It is effective that the n position enters 4 n bit data write signals that go out memory module V B, n entered n bit data that the n position goes out mapped memory 4 write the n position and enter 4 and go out in memory module V B;

When the output pulse 2. the time:

It is effective that n enters 44 bit data read output signals that go out memory module V B, according to the u bit address value of input 4 bit data of read address counter 19 output, 4 bit data is transferred to 4 and enters 32 4 bit data input ends that go out memory module V C;

Group number counter 20 adds 1, i.e. K value+1;

When the output pulse 3. the time:

4 to enter 32 4 bit data write signals that go out memory module V C effective, writes 4 bit data address values according to 3 of write address counter 21 outputs and 4 bit data are written to 4 enter 32 and go out memory module V C;

If the count value of group number counter 20 is 08H when sending spill over, initial value address counter 18 adds 1, namely enters next group Y numbering first address, resets 4 to enter 32 and go out memory module V C, and making 32 storage unit is all " 0 ";

When the output pulse 4. the time:

32 bit data write signals of data compound storage 32 are effective, enter 32 32 bit data data writing compound storages 32 that go out memory module V C output according to 32 bit data address values of data compound storage address counter 22 output s position with 4;

If the count value of group number counter 20 is 08H when sending spill over, send presetting pulse to read address counter 19, the counting initial value of initial value address counter 18 outputs is preset to read address counter 19, make the value of read address counter 19 output u bit address be the counting initial value, write address counter 21 resets;

When the output pulse 5. the time:

Write address counter 21 adds 1, and read address counter 19 adds 1, and data compound storage address counter 22 adds 1;

If the count value of group number counter 20 is 08H when sending spill over, the group number that resets counter 20;

When the output pulse 6. the time:

If the count value of data compound storage address counter 22 is wH when sending spill over, the initial value address counter 18 that resets, read address counter 19, group number counter 20, write address counter 21, data compound storage address counter 22 and pulsqe distributor V D;

When the output pulse 7. the time:

Loop start pulsqe distributor V D, pulsqe distributor V D sends 2. signal of pulse, the span of said n, u, s and w is: n be 64 or 32, u be 43, s be 7 or 6, w be 79 or 39; When n is 64, m=6, u=4, s=7, w=79; When n is 32, m=5, u=3, s=6, w=39.

As required, the utility model can have following two kinds of embodiments.

Embodiment one: a kind of 64 PLC input gathers and reading information reflection memory controller

The PLC input port 1 that this 64 PLC input gathers with the PLC input port of reading information reflection memory controller and reflection memory module I be X00～X63, and described PLC inputs modulate circuit 2, FPGA input port 3, n and enters the n position to go out mapped memory 4 be 64; The n that institute's rheme information reads the control module IV enters 4, and to go out control module 14 be 64 to enter 4 and go out control module; The n of described Data Transmission Controlling module V enters 4 and goes out memory module V B and 64 enter 4 and go out memory module V B, the data storage of the data compound storage 32 of described data combination memory module VI is arranged referring to subordinate list one, the output data address is A0-A6, the m position X numbering output terminal of described address command writing module III is 6 X numbering output terminals, the u position counting initial value of described initial value address counter 18 is 4 initial value address outputs, and the input u bit data address of described read address counter 19 is 4 counting initial values; The counting overflow value WH of described data compound storage address counter 22 is that 79H sends spill over, and s bit address value is 7 bit address (referring to Fig. 1～Fig. 5, subordinate list one, in Fig. 1～Fig. 5, subordinate list one, the present embodiment is got n=64, m=6, u=4, s=7, w=79).

Embodiment two: a kind of 32 PLC input gathers and reading information reflection memory controller

The PLC input port 1 that this 32 PLC input gathers with the PLC input port of reading information reflection memory controller and reflection memory module I be X00～X31, and described PLC inputs modulate circuit 2, FPGA input port 3, n and enters the n position to go out mapped memory 4 be 32; The n that institute's rheme information reads the control module IV enters 4, and to go out control module 14 be 32 to enter 4 and go out control module; The n of described Data Transmission Controlling module V enters 4 and goes out memory module V B and 32 enter 4 and go out memory module V B, the data storage of the data compound storage 32 of described data combination memory module VI is arranged referring to subordinate list two, the output data address is A0-A5, the m position X numbering output terminal of described address command writing module III is 5 X numbering output terminals, the u position counting initial value of described initial value address counter 18 is 3 initial value address outputs, and the input u bit data address of described read address counter 19 is 3 counting initial values; The counting overflow value WH of described data compound storage address counter 22 is that 39H sends spill over, s bit address value be 6 bit address (referring to Fig. 1～Fig. 4, Fig. 5～Fig. 6, subordinate list two, Fig. 1～Fig. 4, among Fig. 6, subordinate list two, the present embodiment is got n=32, m=5, u=3, s=6, w=39.

Subordinate list one

" the PLC input collection of the utility model embodiment one and the data storage permutation table of the data compound storage of reading information reflection memory controller "

Subordinate list two

" the PLC input collection of the utility model embodiment two and the data storage permutation table of the data compound storage of reading information reflection memory controller "

Claims (8)

1. a PLC inputs collection and reading information reflection memory controller, comprises that PLC input port and video memory module (I), command decoder and operation address information module (II), high speed are inputted a position information control module (III), position information reads control module (IV), Data Transmission Controlling module (V) and data and makes up memory module (VI);

Described PLC input port and reflection memory module (I) are respectively with command decoder and operation address information module (II), an input position information control module (III), an information read control module (IV) and is connected V with the Data Transmission Controlling module at a high speed) be connected; Described PLC input port carries out light isolation, level conversion, filtering with reflection memory module (I) with PLC input port information, and under the effect of input acquisition storage n position input message;

Also input position information control module (III), position information read control module (IV) to described command decoder respectively with at a high speed, Data Transmission Controlling module (V) is connected memory module (VI) and is connected with data with operation address information module (II); When the address value of system address bus is that the PLC input gathers the address value with reading information reflection memory controller, described command decoder and operation address information module (II) are under the effect of the WR of system signal, the memory command word is through the decoding output command signal, and m position X numbering and 3 X class values of storage input X element are also exported;

A described high speed input position information control module (III) is carried out a position information reading order at a high speed, with a certain position communication of the PLC input port D0 position to system data bus, realizes an information acquisition at a high speed;

Institute's rheme information reads control module (IV) execute bit information reading order, and the X soft element information of numbering appointment according to m position X is transferred to the D0 position of system data bus from PLC input port and reflection memory module (I);

Described Data Transmission Controlling module (V) also is connected with data combination memory modules (VI); Described Data Transmission Controlling module (V) is under the time sequential pulse effect that this inside modules produces, be one group with the n position information of PLC input port and reflection memory module (I) storage according to 4 information, the mode of initial X numbering and 3 X class value institute standards is controlled and is transferred to data and makes up memory modules (VI) and stored;

Described data combination memory module (VI) canned data is to be one group according to 4 position information, the mode of initial X numbering and 3 X class value institute standards is arranged, during the executing data reading order, under the effect of the RD of system signal, the s bit address that is combined into according to initial X numbering and 3 X class values reads this address location data transmission and arrives system data bus, the span of said n, m and s is: n be 64 or 32, m be 6 or 5, s be 7 or 6; When n is 64, m=6, s=7; When n is 32, m=5, s=6.

2. PLC as claimed in claim 1 input gathers and reading information reflection memory controller, it is characterized in that: described PLC input port and reflection memory module (I) comprise that PLC input port (1), input signal conditioning circuit (2), FPGA input port (3) and n enter the n position and go out mapped memory (4); PLC input port (1) is connected with the input end of PLC input modulate circuit (2) as the link of the outside input switch of PLC or device, the output terminal of PLC input modulate circuit (2) is connected with an end of FPGA input port (3), and PLC input port (1) information is carried out filtering, photoelectricity isolation and level conversion; The other end of FPGA input port (3) and the input end of input position information control module (III) at a high speed, n enter the n bit data input end that the n position goes out mapped memory (4) and connect;

Described n enters n bit data output terminal that the n position goes out mapped memory (4) and position information and reads control module (IV) and be connected V with the Data Transmission Controlling module) be connected; Input acquisition input end is connected with operation address information module (II) with command decoder;

Described n enters the n position and goes out mapped memory (4) under the effect of input acquisition signal, and the information exchange that PLC is inputted modulate circuit (2) output is crossed FPGA input port (3) and is stored in n and enters the n position and go out in mapped memory (4); Described n enters the n position and goes out the n bit data that mapped memory (4) stores and directly output to n bit data output terminal, and the span of said n is: n is 64 or 32.

3. PLC as claimed in claim 1 input gathers and reading information reflection memory controller, it is characterized in that: described command decoder and operation address information module (II) comprise module's address recognizer (5), command register (6), operating characteristics code translator (7), not gate I (8) and with door I (9); The module's address input end of module's address recognizer (5) is connected with system address bus, if the address value of system address bus is the address value of this module, the CS signal of module's address recognizer (5) output is " 0 ", otherwise is " 1 "; The CS signal output part of module's address recognizer (5) is connected 8 with the Enable Pin of command register (6) with the not gate I) input end be connected;

The reset terminal of command register (6) is connected 8 with the not gate I) output terminal connect; The command information input end is connected with system data bus, the command information that the system of acceptance sends, m position X number information and 3 X class value information datas; The write signal input end is connected with system WR signal; The command information output terminal is connected with the command information input end of operating characteristics code translator (7); M position X numbers output terminal and inputs a position information control module (III) with high speed respectively, and position information reads control module (IV) and is connected memory module (VI) connection with data; 3 X class value output terminals are connected with data combination memory modules (VI); Described command register (6) is when being enabled, and under the effect of " 1 " → " 0 " signal, with the command information of system data bus, m position X number information and 3 X class value information are stored in command register (6) at the WR of system; When not gate I (8) output terminal is " 0 ", reset command register (6), command register (6) is when being reset, and the command information output terminal is " 000 ";

The command information input end of operating characteristics code translator (7) is connected with the command information output terminal of command register (6), obtains command code information; 5 order output terminals of operating characteristics code translator (7) are respectively with PLC input port and reflection memory module (I), at a high speed an input position information control module (III), position information read control module (IV), Data Transmission Controlling module (V) is connected memory module (VI) and is connected with data, the reset command output terminal be connected with an input end of door I (9); When command register (6) is reset when being output as " 000 ", all signals of 5 order output terminals of operating characteristics code translator (7) are " 1 "; When command register (6) is output as effective order information, there is an order output terminal to be " 0 " in 5 order output terminals of operating characteristics code translator (7), other 4 order output terminals are " 1 ";

Be connected with the systematic reset signal input end with another input end of door I (9); Be connected with data combination memory modules (VI) with the reset command output terminal of operation address information module (II) as command decoder with the output terminal of door I (9), the span of above-mentioned m is: m is 6 or 5.

4. PLC input as claimed in claim 1 gathers and reading information reflection memory controller, and it is characterized in that: described high speed input position information control module (III) comprises 3-8 code translator (10), triple gate group (11) or door I (12) and triple gate I (13); The high speed position information reading order output terminal of the high speed position information reading order input end of 3-8 code translator (10) and command decoder and operation address information module (II) is connected; 3 encoded radio input ends of X numbering are connected with low 3 output terminals of m position X numbering of operation address information module (II) with command decoder; 8 decoding value output terminals are connected with 8 control ends of triple gate group (11);

8 input ends of triple gate group (11) are connected with 8 ports of PLC input port with the FPGA input port (3) of reflection memory module (I); The position information output is connected with the input end of triple gate I (13);

Or the high speed position information reading order output terminal of input end of door I (12) and command decoder and operation address information module (II) is connected, and another input end is connected with the RD signal wire of system; Or the output terminal of door I (12) is connected with the control end of triple gate I (13);

The D0 position of the output terminal of triple gate I (13) and system data bus is connected;

Described high speed input position information control module (III) is carried out position information reading order at a high speed, according to a triple gate corresponding to low 3 the decoding gating triple gate groups (11) of m position X numbering, under the effect of the RD of system signal, the position information output that PLC input port and the position information exchange of FPGA input port (3) corresponding ports of reflection memory module (I) are crossed triple gate group (11) is transferred to the D0 position of system data bus, and the span of above-mentioned m is: m is 6 or 5.

5. PLC as claimed in claim 1 input gathers and reading information reflection memory controller, it is characterized in that: institute's rheme information reads control module (IV) and comprises that n enters 4 and goes out control module (14), 4 and enter 1 and go out control module (15) or door II (16) and triple gate II (17); N enters 4 n bit data input ends that go out control module (14) and PLC input port and the n of reflection memory module (I) and enters the n bit data output terminal that the n position goes out mapped memory (4) and be connected; 4 bit data output terminals and 4 enter 14 bit data input end that go out control module (15) and are connected; The m position X high u of the numbering position output terminal of the input end of 4 bit data OPADD and command decoder and operation address information module (II) is connected;

4 enter 11 information output that goes out control module (15) is connected with the input end of triple gate II (17); The input end of 1 information output address is connected with low 2 output terminals of m position X numbering of operation address information module (II) with command decoder;

Or the door II (16) an input end be connected with the position information reading order output terminal of operation address information module (II) with command decoder, another input end is connected with the RD of system signal line end; Output terminal is connected 17 with the triple gate II) control end connect;

The D0 position of the output terminal of triple gate II (17) and system data bus is connected;

Institute's rheme information reads control module (IV) execute bit information reading order, n enters 44 bit data that go out the specified storage unit in control module (14) output m position X numbering high u position, 4 enter 1 position information that goes out low 2 the specified storage bit unit of control module (15) output m position X numbering, the bit location content delivery of m position X numbering appointment is arrived the D0 position of system data bus under the effect of the RD of system signal, the span of said n, m and u is: n is 64 or 32, m be 6 or 5, u be 4 or 3; When n is 64, m=6, u=4; When n is 32, m=5, u=3.

6. a kind of PLC input as claimed in claim 1 gathers and reading information reflection memory controller, it is characterized in that: described Data Transmission Controlling module (V) comprises that address and time-sequence control module (V A), n enter 4 and go out memory module (V B), 4 and enter 32 and go out memory module (V C) and pulsqe distributor (V D);

Described address and time-sequence control module (V A) and n enter 4 and go out memory module (V B), 4 and enter 32 and go out memory module (V C), pulsqe distributor (V D), command decoder and be connected memory module (VI) with data with operation address information module (II) and be connected; Described address and time-sequence control module (V A) are completed n and are entered 4 data readings that go out memory module (V B) under the time sequential pulse effect that pulsqe distributor (V D) produces, 4 enter 32 goes out memory module (V C) and data make up the control operation that memory module (VI) data write and reset;

Described n enters 4 and goes out memory module (V B) and also enter the n position with PLC input port and the n of reflection memory module (I) and go out mapped memory (4), 4 and enter 32 4 bit data input ends that go out memory module (V C) and be connected V D with pulsqe distributor) pulse 2. output terminal be connected; Described n enters 4 and goes out memory module (V B) storage n position information, and n position information is take 4 information as one group of output storage unit that forms 4 bit data, and when the n value is 64, its 4 one group data storage cell address is from 0000H-1111H; When the n value is 32, its 4 one group data storage cell address is from 000H-111H;

Described 4 enter 32 go out memory module (V C) also with the pulse of pulsqe distributor (V D) 3. output terminal be connected memory module (VI) with data and be connected; Described 4 enter 32 4 one group data storage cell addresses that go out memory module (V C) from 000H-111H;

Described pulsqe distributor (V D) also is connected with data combination memory modules (VI), the clock pulse input terminal of pulsqe distributor (V D) is connected with system clock, the starting impulse input end is connected with the input acquisition output terminal of operation address information module (II) with command decoder, and the pulse of loop start pulse input end and pulsqe distributor (V D) 7. output terminal is connected; Described pulsqe distributor (V D) is as the inside sequential control of PLC input collection with data writing combination memory module (VI) data of reading information reflection memory controller, startup work under the effect of input acquisition signal, according to sequential output pulse 1., pulse 2., pulse 3., pulse 4., pulse is 5., pulse 6., pulse is 7.; Under pulse effect 7., circulation output pulse 2., pulse 3., pulse 4., pulse 5., pulse 6., pulse 7., until pulsqe distributor (V D) is reset;

Described address and time-sequence control module (V A) comprise initial value address counter (18), read address counter (19), group number counter (20), write address counter (21), data compound storage address counter (22), with a door II (23), with a door III (24), with a door IV (25), not gate II (26), not gate III (27) or door III (28) or door IV (29) or door V (30) and or a VI (31); The reset signal input end of initial value address counter (18) is connected with output terminal with door IV (25), the count pulse input end be connected the output terminal of door III (28) and connect, the u position of the u position counting initial value output terminal of initial value address counter (18) and read address counter (19) is counted the initial value input end and is connected;

The reset signal input end of read address counter (19) is connected with output terminal with door IV (25), the presetting pulse input end be connected the output terminal of door IV (29) and connect, count pulse input end and pulse 5. output terminal are connected; U bit address output terminal and the n of 4 bit data of read address counter (19) enters 4 u bit address input ends that go out input 4 bit data of memory module (V B) and is connected;

The reset signal input end of group number counter (20) is connected with output terminal with door II (23), count pulse input end and pulse 2. output terminal are connected, the counting of group number counter (20) overflows output terminal is connected 26 with not gate) input end connect, the counting overflow value of group number counter (20) is 08H;

The RESET input of write address counter (21) is connected with output terminal with door III (24), count pulse input end and pulse 5. output terminal are connected, and 3 of write address counter (21) write 4 bit data address output ends and 4 and enter 32 4 bit data address input ends that go out memory module (V C) and be connected;

The RESET input of data compound storage address counter (22) is connected with output terminal with door IV (25), count pulse input end and pulse 5. output terminal are connected, counting overflows output terminal and is connected 27 with not gate) input end connect, the s bit address output terminal of input 32 bit data of data compound storage address counter (22) is connected with the s bit address input end of input 32 bit data of data combination memory modules (VI), and the counting overflow value of data compound storage address counter (22) is wH;

With two input ends of door II (23) respectively with door IV (25) and or the output terminal of door V (30) be connected;

With two input ends of door III (24) respectively with door IV (25) and or the output terminal of door IV (29) be connected;

With two input ends of door IV (25) respectively with the input acquisition output terminal of command decoder and operation address information module (II) and or the output terminal of door VI (31) be connected, with the output terminal of door IV (25) as the module reset signal, when the module reset signal is " 0 ", the initial value address counter (18) that resets, read address counter (19), group number counter (20), write address counter (21) and data compound storage address counter (22);

The output terminal of not gate II (26) be connected input end of door III (28) or door IV (29) an input end and or an input end of door V (30) connect; The output of not gate II (26) is as the counting spill over of group number counter (20);

The output terminal of not gate III (27) be connected input end of door VI (31) and connect;

Or another input end and the pulse of door III (28) 3. output terminal be connected, or the output terminal of an III (28) also enters 32 reset signal input ends that go out memory module (V C) and is connected with 4;

Or another input end and the pulse of door IV (29) 4. output terminal be connected;

Or another input end and the pulse of door V (30) 5. output terminal be connected;

Or another input end and the pulse of door VI (31) 6. output terminal be connected, or the output terminal of door VI (31) also waits for that with resetting of pulsqe distributor (V D) the enabling signal input end is connected, the span of said n, u, s and w is: n is 64 or 32, u is 4 or 3, s be 7 or 6, w be 79 or 39; When n is 64, m=6, u=4, s=7, w=79; When n is 32, m=5, u=3, s=6, w=39.

7. PLC as claimed in claim 1 input gathers and reading information reflection memory controller, it is characterized in that: described data combination memory modules (VI) comprise data compound storage (32) ,-1 counter (33) and or a VII (34), the s bit address input end of data compound storage (32) input 32 bit data is connected with the s bit address output terminal of input 32 bit data of data compound storage address counter (22), 32 bit data input ends and 4 enter 32 32 bit data output terminals that go out memory module (V C) and are connected, data write signal input end and pulse 4. output terminal are connected, the low 3 bit address input end A2 A1 A0 of 32 output data addresses are connected with the terminal count output of-1 counter (33), the output terminal that high u bit address input end and the command decoder of 32 output data addresses and the m position X of operation address information module (II) number high u position is connected, the n value is 64, u=4, its high 4 bit address input ends are A6 A5 A4 A3, the n value is 32, u=3, and its high 3 bit address input ends are A5 A4 A3, the data reading signal input part be connected the output terminal of door VII (34) and connect, 32 bit data output terminals of data compound storage (32) are connected with system data bus, and the reset signal input end is connected with the reset command output terminal of command decoder with operation address information module (II),

The count value input end of-1 counter (33) is connected with 3 X class value output terminals of operation address information module (II) with command decoder, and-1 count pulse input end is connected with the data read command output terminal of command decoder with operation address information module (II);

Or two input ends of door VII (34) are connected with data read command output terminal and system's RD signal of operation address information module (II) with command decoder respectively, the span of said n, m, u and s is: n is 64 or 32, m be 6 or 5, u be 4 or 3, s be 7 or 6; When n is 64, m=6, u=4, s=7; When n is 32, m=5, u=3, s=6.

8. PLC input as claimed in claim 6 gathers and reading information reflection memory controller, it is characterized in that: under the effect of the input collection signal of command decoder and operation address information module (II), the initial value address counter (18) of described Data Transmission Controlling module (V), read address counter (19), group number counter (20), write address counter (21) and data compound storage address counter (22) are reset and starting impulse divider (V D) work;

When the output pulse 1. the time:

It is effective that the n position enters 4 n bit data write signals that go out memory module (V B), n entered n bit data that the n position goes out mapped memory (4) write the n position and enter 4 and go out in memory module (V B);

When the output pulse 2. the time:

It is effective that n enters 44 bit data read output signals that go out memory module (V B), according to the u bit address value of input 4 bit data of read address counter (19) output, 4 bit data is transferred to 4 and enters 32 4 bit data input ends that go out memory module (V C);

Group number counter (20) adds 1, i.e. K value+1;

When the output pulse 3. the time:

4 to enter 32 4 bit data write signals that go out memory module (V C) effective, writes 4 bit data address values according to 3 of write address counter (21) output and 4 bit data are written to 4 enter 32 and go out memory module (V C);

If the count value of group number counter (20) is 08H when sending spill over, initial value address counter (18) adds 1, namely enters next group Y numbering first address, resets 4 to enter 32 and go out memory module (V C), and making 32 storage unit is all " 0 ";

When the output pulse 4. the time:

32 bit data write signals of data compound storage (32) are effective, enter 32 32 bit data data writing compound storages (32) that go out memory module (V C) output according to 32 bit data address values of data compound storage address counter (22) output s position with 4;

If the count value of group number counter (20) is 08H when sending spill over, send presetting pulse to read address counter (19), the counting initial value of initial value address counter (18) output is preset to read address counter (19), make the value of read address counter (19) output u bit address be counting initial value, the write address counter that resets (21);

When the output pulse 5. the time:

Write address counter (21) adds 1, and read address counter (19) adds 1, and data compound storage address counter (22) adds 1;

If the count value of group number counter (20) is 08H when sending spill over, the group number that resets counter (20);

When the output pulse 6. the time:

If the count value of data compound storage address counter (22) is wH when sending spill over, initial value address counter (18) resets, read address counter (19), group number counter (20), write address counter (21), data compound storage address counter (22) and pulsqe distributor (V D);

When the output pulse 7. the time:

Loop start pulsqe distributor (V D), pulsqe distributor (V D) sends 2. signal of pulse, the span of said n, u, s and w is: n be 64 or 32, u be 43, s be 7 or 6, w be 79 or 39; When n is 64, m=6, u=4, s=7, w=79; When n is 32, m=5, u=3, s=6, w=39.

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