CN103065188A

CN103065188A - Decoding circuit of non-contact integrated circuit (IC) card

Info

Publication number: CN103065188A
Application number: CN 201310018338
Authority: CN
Inventors: 卢小冬; 苏建南; 于向红; 刘维
Original assignee: WUXI ZHONGKE WOPURUI TECHNOLOGY CO LTD
Current assignee: WUXI ZHONGKE WOPURUI TECHNOLOGY CO LTD
Priority date: 2013-01-18
Filing date: 2013-01-18
Publication date: 2013-04-24

Abstract

The invention discloses a decoding circuit of a non-contact integrated circuit (IC) card. The circuit comprises a resetting module RSTX, a frequency divider DIVX with resetting control, a counter CT1, a module X counter CT 2, a decoding state module DECODE_STATE, a coding module ETUX and a decoding signal sampling module DECODE_SAMPLE. The design of the decoding circuit adopts a forward-direction design without feedback, supports accurate unit coding clock recovery and delayed non-return-to-zero code decoding output of 7/ 8 unit coding clocks, and can support data decoding of different communication speeds. The edges of the unit coding clocks and the edges of signal input grooves are overlapped, and differ 1/8 unit coding clocks, and therefore the decoding circuit of the non-contact IC card is high in anti-jamming ability of power supply burrs caused by the signal grooves.

Description

A kind of decoding circuit of non-contact IC card

Technical field

The present invention relates to the contactless communication integrated circuit, be specifically related to a kind of decoding circuit of non-contact IC card.

Background technology

Meet the high frequency non-contact card of ISO/IEC 14443 standards since coming out, penetrated into the every field of daily life, be widely used in the every field such as identification, ticket, gate inhibition, bank card, stored value card.Wherein from the Mifare system of Philips/NXP company develop and the ISO/IEC14443 A type non-contact card that comes because coded system is unique, decoding circuit is simple, obtained comprising the support of a lot of integrated circuit manufacturer of Philips/NXP, product type is numerous, multi-size well satisfies various demands.For needs and the realization technology upgrading that better adapts to emerging service, revise on the basis of the standard that the second portion of describing ISO/IEC14443 standard radio frequency interface is also promulgated in June calendar year 2001, one of content of revision is exactly to say that data communication rates brings up to 212Kbps, 424Kbps and 847Kbps from single 106Kbps, and with 106Kbps as default traffic rate.

For the A system of ISO/IEC1443 standard, its coded system has adopted improved Miller coding, uses the 100%ASK modulated transmit signal.Such as Fig. 1, the sequence X of " groove "/" time-out-Pause " (appellation of different documents is different, hereinafter unified be called " groove ") of radio-frequency (RF) energy interruption appears in the centre position of a code bit (ETU); The sequence Y that " groove " of radio-frequency (RF) energy interruption in a code bit (ETU), do not occur all the time; The sequence Z that occurs " groove " of radio-frequency (RF) energy interruption in a code bit (ETU) starting position; With the combination of sequence X, Y and Z represent to communicate by letter beginning (SOC), logical zero, logical one and sign off (EOC).

Coding rule according to ISO/IEC14443, the reader acknowledges requests instruction REQA of A type is sexadecimal 0x26, the mode that adopts low level to send out first, Fig. 2 shows radio frequency clock signal RF_CLK, radio frequency input restituted signal RF_IN and a corresponding unit encoding clock ETU_CLK waveform that complete REQA instruction is corresponding.Clock after the corresponding non-contact card of RF_CLK or the shaping of RFID tag receiving end radiofrequency signal is the output behind analog signal figure corresponding to Fig. 1; Radio frequency input restituted signal RF_IN be the corresponding simulating signal demodulation of Fig. 1 out and the envelope after the digitizing, be the local demodulation of non-contact card or RFID tag receiving end digital signal output out; These two signals are that non-contact card or RFID tag integrated circuit are to the main input signal of improved Miller coding decoder.The ETU_CLK signal is used for identifying single code bit, does not exist in wireless signals, need to recover in demoder.

Fig. 3 shows the specification of 106Kbps range signal modulation groove.The width of groove is not fixed, and certain scope is arranged.

Although the demodulator circuit of ISO/IEC14443A signal is simple, but during the signal of identification information " groove ", the receiving integrate circuit of contactless communication can not be from the antenna-coupled to the energy and clock, therefore, the decoding circuit of ISO/IEC14443 standard A type product is complicated, and design difficulty is large.After particularly the speed of data communication improves, use same set of decoding circuit to be applicable to the difficult point that various code checks are integrated circuit related with same decoder design.

In the people's such as Qiu Zujiang " a kind of implementation method of improved Miller encoding and decoding (microelectronics, the 30th volume, the 3rd phase, in June, 2000,176-178 page or leaf) ", the author provides a kind of simple, effective decoding circuit for 106Kbps, such as Fig. 4.Its signal signal and internal_clk are corresponding respectively radio frequency input restituted signal RF_IN and the radio frequency clock signal RF_CLK among Fig. 2.The document has used " clock circuit " to obtain clk_128, and clk_128 is equivalent to the ETU_CLK among Fig. 2.Different with general counter frequency division, during " groove ", the RF_CLK/internal_clk signal stops, therefore, the way of this design is when " groove " be arranged, and low 4 of counter that will " clock circuit " resets, and will hang down position, 2 position among 3 of remainder, most significant digit remains unchanged, and " groove " just can not appear on the variation edge of clk_128/ETUCLK like this.This design uses " pulsing circuit " to produce " groove " the identification signal signal that width is 8 carrier frequency clocks.This design is at " groove " when signal occurs, by force frequency counter is carried out set/reset and recover signal to fixing numerical value, different code checks need to arrange different counter reset/set numerical value, application has two defectives for high-speed data communication: one, " groove " width is not constant, such as Fig. 3, " groove " width of different size will recover the different clk_128 of dutycycle (corresponding 212/424/827Kbps, correspondence becomes clk_64/clk_32/clk_16 respectively); Two, in order to stagger " groove " and the edge of signal signal, " groove " identification signal signal occupies 8 carrier frequency clocks, and it is inapplicable that this design only has the 847Kbps high speed situations of 16 carrier frequency clocks for an ETUCLK.

In US Patent No. 6962293, the inventor has proposed a kind of decoder design that is applicable to various code checks.Such as Fig. 5, in this patent, used a pre-frequency counter Divider that nothing resets, with radio frequency clock signal RF_CLK signal frequency split, select signal SEL according to speed, the DIV_CLK of output ETUCLK quadruple; Use one three count pick up device RX_IN_CNT, this counter can be resetted by " groove " signal of systematic reset signal SYS_RST or radio frequency input restituted signal RF_IN; One two counter STATE_CNT, the generation state; A clock generates decoder module, and output improves the decoded non-return-to-zero output of Miller RX_IN, code bit clock ETU_RX_CLK, decoded state indication END_OF_RX; One is used ETU_RX_CLK to generate " Reset Controller " module that the STATE_CNT counter resets.

This patent can be closed according to the output data groups of counter RX_IN_CNT sum counter STATE_CNT, obtains respectively the state of the logical zero of the rising edge of ETU_RX_CLK and negative edge, RX_IN and logical one, END_OF_RX.

Compare with the technology of previous document, this patented technology can obtain the recruiting unit encoded clock ETU_RX_CLK consistent with desirable ETUCLK, and can use the DIV_CLK of code check quadruple, in conjunction with count pick up device RX_IN_CNT and state counter STATE_CNT, provide output data RX_IN and the sign off indicator signal END_OF_RX of demoder non return-to-zero code.This patent has also provided the mapping table of detailed RX_IN_CNT and STATE_CNT counter values and RX_IN, ETU_RX_CLK and END_OF_RX output signal.

Decoding output RX_IN, the unit encoding clock ETU_RX_CLK of this Patent design and the corresponding states more complicated between end communication END_OF_RX and the counter are such as respectively corresponding 7 RX_IN_CNT and the STATE_CNT combination of rising and falling edges of ETU_RX_CLK; 3 and 4 combinations of states of the logical zero of RX_IN and the logical one corresponding RX_IN_CNT of difference and STATE_CNT.

Fig. 6 has provided patent application number: 201210287560.0 " a kind of decoding circuits of non-contact IC card " that provide have proposed a kind of decode forward circuit design without feedback.This design can support accurate unit encoding clock ETU_CLK to recover and fix the non return-to-zero code decoding output RX_NRZ that 1 unit encoding clock ETU_CLK lags behind, and can support the data decode of different communication speed and reply base when providing accurate for anti-collision.The edge of the unit encoding clock ETU_CLK that this decoding circuit recovers and non return-to-zero code decoding output RX_NRZ signal overlaps with the edge of groove signal, therefore, needs good on-chip power supply design, the power supply burr impact that causes to reduce groove signal.

Summary of the invention

The present invention proposes a kind of decoding circuit of non-contact IC card, the forward direction design without feedback is used in this decoding circuit design, support accurate unit encoding clock recovery and 7/8 unit encoding clock delay non return-to-zero code decoding output afterwards, can support the data decode of different communication speed, and unit encoding clock edge and input signal groove edge differ 1/8 unit encoding clock, and the power supply burr antijamming capability that the signal groove is caused is strong.

According to an aspect of the present invention, a kind of decoding circuit of non-contact IC card is disclosed, the input signal of this decoding circuit comprises systematic reset signal SYS_RST, radio frequency input restituted signal RF_IN, radio frequency clock signal RF_CLK, code rate selection signal SEL, output signal comprises non return-to-zero code output signal RX_NRZ, unit encoding clock signal ETUCLK and receives indicator signal DATRDY that this circuit comprises:

Reseting module RSTX is configured to produce reset signal RSTN according to systematic reset signal SYS_RST and radio frequency input restituted signal RF_IN;

The frequency divider DIVX that band resets and controls, be configured to radio frequency clock signal RF_CLK is carried out frequency division, triggered by radio frequency clock signal RF_CLK negative edge, according to code rate selection signal SEL output frequency division signal DIV_CLK, and the two divided-frequency signal RF_CLK/2 of 1/2 radio frequency clock signal RF_CLK frequency, two output signals are resetted by reset signal RSTN;

Counter CT1 is configured to fractional frequency signal DIV_CLK is counted, and is triggered by fractional frequency signal DIV_CLK rising edge, exports count signal CNT1, and is resetted by reset signal RSTN;

Mould X counter CT2 is configured to fractional frequency signal DIV_CLK is carried out mould X counting, is triggered by fractional frequency signal DIV_CLK rising edge, exports count signal CNT2, and is resetted by reset signal RSTN;

Decoded state module DECODE_STATE is configured to trigger according to the negative edge of two divided-frequency signal RF_CLK/2, produces and receives indicator signal DATRDY;

Decoding module ETUX is configured to according to systematic reset signal SYS_RST, receives indicator signal DATRDY, fractional frequency signal DIV_CLK, count signal CNT1 and count signal CNT2 output unit encoded clock ETUCLK signal;

Decoded signal sampling module DECODE_SAMPLE, this module is configured to according to systematic reset signal SYS_RST, reset signal RSTN and unit encoding clock ETUCLK signal, the decoded output signal of output non return-to-zero code RX_NRZ.

Description of drawings

By becoming more obvious to the more detailed description of embodiment of the invention mode in the accompanying drawing above-mentioned and other purpose of the present invention, Characteristics and advantages, wherein, identical reference number represents the same parts in the illustrated embodiments of the invention mode usually.

Fig. 1 shows the improved Miller modulation signals waveform that typical contactless communication integrated circuit receives;

Fig. 2 shows complete REQA instruction radio frequency clock signal RF_CLK, radio frequency input restituted signal RF_IN and corresponding unit encoding clock ETU_CLK waveform;

Fig. 3 shows the specification of ISO14443 standard 106Kbps range signal modulation groove;

Fig. 4 shows a kind of decoding circuit design that simply is applicable to the low speed code check;

Fig. 5 shows a kind of decoding circuit design that is applicable to a plurality of speed;

Fig. 6 shows patent application number 201210287560.0 " a kind of decoding circuits of non-contact IC card " that provide;

Fig. 7 shows the improved Miller coding and decoding of many speed of the present invention circuit;

Fig. 8 shows CNT1 and the CNT2 coding of decoding module output ETUCLK of the present invention;

Fig. 9 shows and uses corresponding each signal of the short frame of reader acknowledges requests REQA instruction of demoder decoding of the present invention.

Embodiment

Describe in further detail with reference to the accompanying drawings preferred implementation of the present invention, shown in the accompanying drawings preferred case study on implementation of the present invention.Yet the present invention can should not be construed the case study on implementation of being set forth here with the various forms realization and limit.On the contrary, it is in order to make the present invention more thorough and complete that these case study on implementation are provided, and, fully scope of the present invention is conveyed to those skilled in the art.

The below illustrates the present invention further combined with chart.

Fig. 7 shows the decoding circuit of a kind of non-contact IC card of one embodiment of the present invention, and this circuit is a kind of improved Miller coding and decoding circuit.The input signal of this decoding circuit comprises systematic reset signal SYS_RST, radio frequency input restituted signal RF_IN, radio frequency clock signal RF_CLK, code rate selection signal SEL, output signal comprises non return-to-zero code output signal RX_NRZ and receives indicator signal DATRDY, this circuit comprises band reseting module RSTX, the frequency divider DIVX that band resets and controls, counter CT1, the counter CT2 of mould X, decoded state module DECODE_STATE, decoding module ETUX, and decoded signal sampling module DECODE_STATE.

The reset frequency divider DIVX of control of band is configured to radio frequency clock signal RF_CLK is carried out frequency division, output frequency division signal DIV_CLK and two divided-frequency signal RF_CLK/2, and reset according to the position that the groove of radio frequency input restituted signal RF_IN occurs.The fractional frequency signal of output can be the output signal of the integral frequency divisioils such as 2 frequency divisions, 4 frequency divisions.In one embodiment, this band reset control frequency divider DIVX also according to external input signal SEL, the signal DIV_CLK of bit rate output 4 frequencys multiplication.Be with the course of work of the frequency divider DIVX of the control that resets to be:

A) groove occurs in response to radio frequency input restituted signal RF_IN, fractional frequency signal DIV_CLK exports " low ", and two divided-frequency signal RF_CLK/2 exports " low ";

B) there is not groove corresponding to radio frequency input restituted signal RF_IN, the frequency divider counting, RF_CLK counts frequency division to the radio frequency clock signal;

C) frequency divider according to the fractional frequency signal DIV_CLK signal of code rate selection signal output unit code rate 4 frequencys multiplication, is exported two divided-frequency signal RF_CLK/2 signal during counting;

Reseting module RSTX is configured to produce reset signal RSTN according to systematic reset signal SYS_RST and radio frequency input restituted signal RF_IN.In one embodiment, can use an end band reverse two the input or (OR) logic realize reseting module RSTX.Certainly, one skilled in the art will appreciate that and can also adopt other, such as the logic of tabling look-up, line or, perhaps the mode such as state machine realizes reseting module RSTX, repeats no more here.

Counter CT1 is configured to fractional frequency signal DIV_CLK is counted, and is triggered by fractional frequency signal DIV_CLK rising edge, exports count signal CNT1, and is resetted by reset signal RSTN.Described counter CT1 further is configured to comprise 2 for a unit encoding clock signal ETUCLK ⁿIndividual fractional frequency signal DIV_CLK, the counter number of bits of counter cnt 1 is n+2; Count signal CNT1 count results equals 2 ^N+1In time, stop to count.In the embodiment of an optimization, the course of work of counter CT1 is:

A) groove appears in or radio frequency input restituted signal RF_IN effective in response to systematic reset signal SYS_RST signal, and counter CT1 output CNT1 equals 0;

B) in response to the rising edge of systematic reset signal SYS_RST invalidating signal and fractional frequency signal DIV_CLK, counter CT1 cumulative 1 also exports count results CNT1;

C) reach 8 in response to CNT1, counter stops counting;

Mould X counter CT2 is configured to fractional frequency signal DIV_CLK is carried out mould X counting, is triggered by fractional frequency signal DIV_CLK rising edge, exports count signal CNT2, and is resetted by reset signal RSTN.Mould X counter CT2 further is configured to comprise 2 for a unit encoding clock signal ETUCLK ⁿIndividual fractional frequency signal DIV_CLK, 1 output count signal CNT1 equals 2 when counter cnt ⁿIn the time of-1, output count signal CNT2 resets.In the embodiment of an optimization, the modulo-three counter CT2 course of work is:

A) groove appears in or radio frequency input restituted signal RF_IN effective in response to systematic reset signal SYS_RST signal, and counter CT2 output CNT2 equals 0;

B) in response to the rising edge of systematic reset signal SYS_RST invalidating signal and fractional frequency signal DIV_CLK, counter CT2 cumulative 1 also exports count results CNT2;

C) count results in response to counter CT2 reaches 3, and counter O reset realizes " mould 3 " output.

Decoded state module DECODE_STATE is configured to trigger according to the negative edge that is configured according to two divided-frequency signal RF_CLK/2, produces and receives indicator signal DATRDY.Decoded state module DECODE_STATE, further be configured to when radio frequency input restituted signal RF_IN when being low set receive indicator signal DATRDY, equal 2 according to systematic reset signal SYS_RST or as counter output signal CNT1 ^N+1In time, reset.In the embodiment of an optimization, the course of work of decoded state module DECODE_STATE is:

A) effective in response to systematic reset signal SYS_RST, demoder accepting state signal DATRDY exports " low ";

B) first negative edge of groove in response to radio frequency input restituted signal RF_IN arrives, and receives indicator signal DATRDY and is output as " height ";

C) the output CNT1 in response to 4Bit counter CT1 reaches 8, receives indicator signal DATRDY zero clearing.

Decoding module ETUX is configured to according to systematic reset signal SYS_RST, receives indicator signal DATRDY, fractional frequency signal DIV_CLK, count signal CNT1 and count signal CNT2 output unit encoded clock ETUCLK signal.Decoding module ETUX further is configured by when systematic reset signal SYS_RST is effective, zero clearing unit encoding clock ETUCLK; Rising edge at fractional frequency signal DIV_CLK triggers, detection counter output signal CNT1 and CNT2 when reception indicator signal DATRDY is effective, and according to the numerical value negate of CNT1 and CNT2 or keep unit encoding clock ETUCLK signal, and the edge zero lap of the edge of unit encoding clock ETUCLK signal and input restituted signal RF_IN groove.In the embodiment of an optimization, the unit encoding clock ETUCLK course of work that the output signal of wherein said decoding module ETUX is recovered is:

A) effective in response to the restoring signal SYS_RST of system, the unit encoding clock signal ETUCLK zero clearing of recovery;

B) response reception indicator signal DATRDY is " height ", and the unit encoding clock signal ETUCLK of recovery allows upset;

C) be " 00 ", " 22 ", " 41 " and " 60 " in response to the output CNT1 of counter CT1 and the output CNT2 of modulo-three counter CT2, and the rising edge of fractional frequency signal DIV_CLK, the designature that the unit encoding clock signal ETUCLK that then recovers gets laststate.

Decoded signal sampling module DECODE_SAMPLE, this module is configured to according to systematic reset signal SYS_RST, reset signal RSTN and unit encoding clock ETUCLK signal, output non return-to-zero code RX_NRZ signal.

Wherein said decoded signal sampling module DECODE_SAMPLE comprises intermediate variable, and this decoded signal sampling module DECODE_SAMPLE further is configured to when systematic reset signal SYS_RST is effective, the set intermediate variable; Rising edge in response to radio frequency input restituted signal RF_IN arrives, and middle variable is carried out set; Arrive in response to unit encoding clock ETUCLK rising edge, to middle variable inversion operation, arrive in response to unit encoding clock ETUCLK negative edge, middle variable is sampled and as the non return-to-zero code RX_NRZ output signal of module.

In the embodiment of an optimization, the course of work of the non return-to-zero code output RX_NRZ of the output encoder demoder of decoding sampling module DECODE_SAMPLE is:

A) arrive in response to reset signal RSTN rising edge, the bosom variable register sets high;

B) first rising edge of groove in response to radio frequency input restituted signal RF_IN arrives, and the bosom variable register sets high;

C) rising edge in response to the unit encoding clock ETUCLK that recovers arrives, and inner sample register intermediate variable is got the designature of current state;

D) negative edge of the unit encoding clock ETUCLK of fractional frequency signal DIV_CLK recovery arrives, and the result of demoder sampling bosom variable register is as the output of RX_NRZ.

The present invention can be by band reseting module RSTX, the frequency divider DIVX that resets, counter CT1, mould X counter CT2, decoded state module DECODE_STATE, the composite design of decoding module ETUX and decoded signal sampling module DECODE_SAMPLE, can be by selecting the different fractional frequency signal DIV_CLK output of frequency counter, the counting step of counter CT1 and mould X counter CT2 is set, for the communication code check and different groove specifications of different ETU width, the unit encoding clock ETUCLK of the code bit ETU of the unit of decoding width, the coding RX_NRZ of non return-to-zero code and reception indicator signal DATRDY.Whole demoder uses the forward direction design without feedback, supports the non return-to-zero code decoding output of accurate unit encoding clock recovery and 7/8 unit encoding clock delay; Can support the data decode of different communication speed, unit encoding clock edge and input signal groove edge are not overlapping, differ 1/8 unit encoding clock, and the power supply burr antijamming capability that the signal groove is caused is strong.

Below with the example that is designed to of 4 frequency division output frequency division signals, then counter CT1 adopts the counter of 4Bit, it is example that mould X counter CT2 adopts the modulo-three counter of 2Bit, describes the decoding circuit course of work in detail.

The inventor by enumerate fully analyze the possible flanking sequence X of Miller coding Y the pattern of Z, find, if use the groove zero clearing of radio frequency input restituted signal RF_IN to process to frequency-dividing clock DIV_CLK, after then each radio frequency clock signal RF_CLK recovers, DIV_CLK all from rising edge, the frequency-dividing clock DIV_CLK rising edge quantity between the adjacent grooves and corresponding coding such as table 1.

The width of a frequency-dividing clock DIV_CLK is 1/4th of 1 code bit width ETUCLK, therefore, uses frequency-dividing clock DIVC_CLK rising edge that ETUCLK is triggered, and effectively makes the Pause edge that staggers, ETUCLK edge, has avoided conflict.

DIV_CLK rising edge quantity between the table 1 flanking sequence groove and corresponding coding

Can calculate with the counter cnt 1 of a radio frequency input restituted signal RF_IN zero clearing quantity of DIV_CLK rising edge between the adjacent radio frequency input restituted signal RF_IN groove; Numerical value in response to counter CT1 reaches 7, the expression sign off.If on this basis, but increase a counter CT2 who fixes with the counting step of above-mentioned counter synchronisation zero clearing, then CT2 combines two counters as the short scale of " slip " on CT1, the edge that identifies unit encoding clock ETUCLK that just can be correct.Use the DIV_CLK rising edge to trigger the output signal ETUCLK of decoding module ETUX, then the groove negative edge of the negative edge of ETUCLK and radio frequency input restituted signal RF_IN represents that the reference position of inputting code bit just in time differs 1/8 unit encoding cycle ETU.The maximum count value of getting CT2 here is 2, therefore become " modulo-three counter ", corresponding table 1 be the minimum length of adjacent grooves DIV_CLK rising edge number.

Arrangement is called ETUCLK with the unit encoding clock that recovers.On the basis that recovers unit encoding clock ETUCLK, just can be by set and the specific register intermediate variable of upset, and use the negative edge of the unit encoding clock ETUCLK that recovers that the content of register intermediate variable is carried out digital sample, just can recover serial non return-to-zero code data corresponding to improved Miller coding.Because ETUCLK and original radio frequency are inputted the groove negative edge of restituted signal RF_IN and are differed 1/8 unit encoding clock, the non return-to-zero code data RX_NRZ of demodulation output and the data of original input also differ 7/8 unit encoding clock, therefore, the edge of the non-return-to-zero coding data of output and the power supply burr that groove causes can be not overlapping, thereby anti-power supply burr characteristic is good.

Be with the frequency counter of the frequency divider DIVX of the control that resets to input restituted signal RF_IN zero clearing by radio frequency, select suitable output frequency division DIV_CLK by the SEL signal.In a kind of embodiment, the DIV_CLK frequency is four times of unit encoding clock ETU_CLK.Such as, the code check of corresponding 106Kbps, the signal frequency of DIV_CLK output is 424KHz; Analogize, the frequency of the corresponding DIV_CLK of the code check of 212Kbps is 847Khz; The frequency of the corresponding DIV_CLK of the code check of 424Kbps is 1.69MHz; The frequency of the DIV_CLK that the 847Kbps code check is corresponding is 3.39MHz.When the code check of selecting two-forty is, the frequency-dividing clock output that is lower than corresponding DIV_CLK is under an embargo, thereby reduces the power consumption of circuit.When reset signal RSTN was invalid, two divided-frequency signal RF_CLK/2 exported 1/2 signal of radio frequency clock signal RF_CLK frequency all the time, was used for triggering decoded state module DECODE_STATE.

The counter CT1 of 4Bit is resetted by system reset SYS_RST signal or radio frequency input restituted signal RF_IN, reset signal in response to counter CT1 is invalid, then counter CT1 to DIV_CLK pulse count, count results circulates between 0,1,2,3,4,5,6,7, and the output count results is to CNT1; When the CNT1 count value reached 8, CNT1 stopped counting.

2Bit modulo-three counter CT2 is resetted by the SYS_RST of system signal or radio frequency input restituted signal RF_IN, reset signal in response to counter CT2 is invalid, then counter CT2 to DIV_CLK pulse count, counting step mould 3, that is to say, count results circulates between 0,1,2, and the output count results is to CT2.

Decoded state module DECODE_STATE exports DATRDY, by the negative edge set of radio frequency input restituted signal RF_IN, removes until the CT1 counting is exported when reaching 8.Therefore DATRDY is in the negative edge action of " communication begins " signal SOC, until sign off.DATRDY is used to indicate " decoding module ETUX " beginning and power cut-off.

Table 2 shows the ETUCLK upset input state table of decoding module ETUX.Decoding module ETUX removes output ETUCLK by system reset SYS_RST; When DATRDY effectively after, triggered by the DIV_CLK rising edge, whenever counter CT1 and CT2 output CNT1 and CNT2 data in the table 2 occur right the time, the ETUCLK upset.Because the particular design of CNT1 and CNT2, ETUCLK can recover desirable unit encoding clock.Fig. 8 shows decoding module output ETUCLK of the present invention upset corresponding CNT1 and CNT2 coding.Among the figure, " SEQ " sequence comprised " communication beginning " (SOC), (EOC) corresponding improvement Miller coding of B1-B7 data, " sign off "; Each binary digit is used 4 binary number representations, corresponding 4 DIV_CLK cycles; Use the groove in the improved Miller coding of " 0 " expression.The particular design of CNT1 and CNT2 is to encode except 0-0 combination set for the CNT1 of ETUCLK upset and CNT2, is unique; Two for the 0-0 combination, does not have the DIV_CLK rising edge to trigger, and therefore, can not upset occur in the position at non-ETUCLK edge.

The ETU_cLKX upset input state table of table 2 decoding module ETUX

CNT1	CNT2
			0	0
2	2
		4	1
6	0

Decoding sampling module DECODE_SAMPLE is resetted by systematic reset signal SYS_RST.After resetting, decoding output data RX_NRZ is output as " height ".The decoding sampling module is according to radio frequency input restituted signal RF_IN, by the rising edge set internal register intermediate variable sampled data of groove signal; Rising edge by ETUCLK carries out " negate " operation to internal register intermediate variable sampled data; By the negative edge of ETUCLK the internal register intermediate variable is sampled and to obtain decoding output RX_NRZ.Because ETUCLK adopts the rising edge of DIV_CLK to trigger, so the edge of ETUCLK differs 1/8 ETUCLK at least in the Pause edge, the edge of ETUCLK meets with the groove edge of radio frequency input restituted signal RF_IN never.Therefore, sampled measurements is reliable.

The frequency-dividing clock DIV_CLK that obtains 4 times of unit encoding clock ETUCLK with the frequency counter of clear terminal has been used in the said improved Miller coding decoder design of whole invention, and adopt the DIV_CLK rising edge to trigger ETUX, so that ETUCLK has effectively avoided the edge of groove, therefore, decoded result had both guaranteed precision, can bear again the fluctuation at " groove " edge of raw data coding; Demoder does not use feedback element, so speed is fast, and it is little to lag behind, use the negative edge sampling of ETUCLK, the data of decoding and the data of transmission 7/8 the fixing unitary code bit width that only lags behind is beneficial to alignment of data, for the code bit alignment of anti-collision answering provides good basis.

Comprehensive above-mentioned invention is described, and each signal of a REQA order use coding decoder design of the present invention as shown in Figure 9.The output unit encoded clock ETUCLK signal that comprises decoding module ETUX among Fig. 9, the intermediate variable waveform of decoding sampling module DECODE_SAMPLE, the non return-to-zero code RX_NRZ waveform of output.

Above-described specific embodiment has carried out further detailed description to purpose of the present invention, technical scheme and beneficial effect.Institute it should be understood that the above only for specific embodiments of the invention, is not limited to the present invention, such as, system reset SYS_RST of the present invention has adopted high level to reset; The groove that improves the Miller coding adopts low level to represent, therefore, the reverse "or" logic composite signal of an end band is adopted in the input that resets of CT1 and CT2, if adopt the low level reset mechanism, then the reseting logic of response also will be done targetedly and adjust.For another example, each module of demoder of the present invention has only been described and has been realized the necessary function of this demoder, in practice, can increase at the frequency division module DIVX that band resets the figure place of counter, for processing, " frame delay-FDT (Frame Delay Time) " provide indicator signal, etc.These extra circuit are placed on the utilization ratio that inside modules of the present invention can improve circuit (such as counter), but add function and the performance that does not affect invention, to itself not contribution of decoding.Within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. the decoding circuit of a non-contact IC card, the input signal of this decoding circuit comprises systematic reset signal SYS_RST, radio frequency input restituted signal RF_IN, radio frequency clock signal RF_CLK, code rate selection signal SEL, output signal comprises non return-to-zero code output signal RX_NRZ, unit encoding clock signal ETUCLK and receives indicator signal DATRDY that this circuit comprises:

2. decoding circuit according to claim 1, wherein said counter CT1 further is configured to comprise 2 for a unit encoding clock signal ETUCLK ⁿIndividual fractional frequency signal DIV_CLK, the counter number of bits of counter CT1 is n+2; Count signal CNT1 count results equals 2 ^N+1In time, stop to count.

3. decoding circuit according to claim 1, wherein said mould X counter CT2 further is configured to comprise 2 for a unit encoding clock signal ETUCLK ⁿIndividual fractional frequency signal DIV_CLK, CNT1 equals 2 when counter CT1 output count signal ⁿIn the time of-1, output count signal CNT2 resets.

4. decoding circuit according to claim 1, wherein said decoded state module DECODE_STATE, further be configured to when radio frequency input restituted signal RF_IN when being low set receive indicator signal DATRDY, equal 2 according to systematic reset signal SYS_RST or as counter output signal CNT1 ^N+1In time, reset.

5. decoding circuit according to claim 1, wherein said decoding module ETUX further is configured by when systematic reset signal SYS_RST is effective zero clearing unit encoding clock ETUCLK; Rising edge at fractional frequency signal DIV_CLK triggers, detection counter output signal CNT1 and CNT2 when reception indicator signal DATRDY is effective, and according to the numerical value negate of CNT1 and CNT2 or keep unit encoding clock ETUCLK signal, and unit encoding clock ETUCLK signal edge and input restituted signal RF_IN groove edge zero lap.

6. described decoding circuit one of according to claim 1, wherein said decoded signal sampling module DECODE_SAMPLE comprises intermediate variable, this decoded signal sampling module DECODE_SAMPLE further is configured to when systematic reset signal SYS_RST is effective, the set intermediate variable; Rising edge in response to radio frequency input restituted signal RF_IN arrives, and middle variable is carried out set; Arrive in response to unit encoding clock ETUCLK rising edge, to middle variable inversion operation, arrive in response to unit encoding clock ETUCLK negative edge, middle variable is sampled and as the non return-to-zero code RX_NRZ output signal of module.

7. according to claim 1-3 and one of 6 described decoding circuits, wherein said band resets the frequency divider DIVX of control also according to external input signal SEL, the fractional frequency signal DIV_CLK of bit rate output 4 frequencys multiplication; Wherein said counter CT1 is the counter of 4Bit; The counter CT2 of wherein said mould X is modulo-three counter; Wherein said reseting module RSTX is two reverse input or (OR) logics of an end; Wherein said intermediate variable is produced by register.

8. the reset course of work of frequency divider DIVX of control of decoding circuit according to claim 7, wherein said band is:

B) there is not groove in response to radio frequency input restituted signal RF_IN, the frequency divider counting, RF_CLK counts frequency division to the radio frequency clock signal;

The course of work of wherein said counter CT1 is:

C) reach 8 in response to CNT1, counter stops counting;

The wherein said modulo-three counter CT2 course of work is:

According to claim 1 with 4 described decoding circuits, the course of work of wherein said decoded state module DECODE_STATE is:

A) effective in response to systematic reset signal SYS_RST, the accepting state signal DATRDY output " low " of demoder;

10. decoding circuit according to claim 5, the course of work of wherein said decoding module ETUX is:

C) be that decimal number is to " 00 ", " 22 ", " 41 " and " 60 " in response to the output CNT1 of counter CT1 and the output CNT2 of modulo-three counter CT2, and the rising edge of fractional frequency signal DIV_CLK, the designature that the unit encoding clock signal ETUCLK that then recovers gets laststate.

11. decoding circuit according to claim 6, the course of work of wherein said decoding sampling module DECODE_SAMPLE is: