CN102810148A - Decoding circuit of non-contact communication integrated circuit - Google Patents
Decoding circuit of non-contact communication integrated circuit Download PDFInfo
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- CN102810148A CN102810148A CN2012102875600A CN201210287560A CN102810148A CN 102810148 A CN102810148 A CN 102810148A CN 2012102875600 A CN2012102875600 A CN 2012102875600A CN 201210287560 A CN201210287560 A CN 201210287560A CN 102810148 A CN102810148 A CN 102810148A
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Abstract
The invention discloses a decoding circuit of a non-contact communication integrated circuit. The decoding circuit comprises a frequency divider DIVX with a reset control function, a reset module, a counter CT 1 of a mold X, a counter CT2, a decoding state module DECODE_STATE, a decoding module ETUX and a decoding signal sampling module DECODE_SAMPLE. The decoding circuit adopts a no-feedback forward design, supports accurate unit coding clock recovery and lagged non return-to-zero code decoding output of a set unit coding clock, and can support data decoding at different communication speeds and provide accurate time bases for collision-resistant response.
Description
Technical field
The present invention relates to the contactless communication integrated circuit, be specifically related to a kind of decoding circuit of contactless communication integrated circuit.
Background technology
The high frequency non-contact card that meets the ISO/IEC14443 standard has penetrated into the every field of daily life since coming out, be widely used in every field such as the identification of people's identity, ticket, gate inhibition, article identification.Wherein from the Mifare system of Philips/NXP company develop and the ISO/IEC14443A type non-contact card that comes because coded system is unique; Demodulator circuit is simple; Obtained comprising the support of a lot of integrated circuit manufacturer of Philips/NXP; Product type is numerous, and multi-size well satisfies various demands.For needs and the realization technology upgrading that better adapts to emerging service; The second portion of describing ISO/IEC14443 standard radio frequency interface is also on the basis of the standard of promulgation in June calendar year 2001; Revise; One of content of revision is brought up to 212Kbps, 424Kbps and 847Kbps with data communication rates from single 106Kbps exactly, and with 106Kbps as default traffic rate.
For the A system of ISO/IEC14443 standard, its coded system has adopted improved Miller coding, uses the 100%ASK modulated transmit signal.Like Fig. 1,102 sequence X of 101 " grooves "/" time-out-Pause " (the different appellations of different documents, the hereinafter unification is called " groove ") of RF energy interruption appear in the centre of a sign indicating number position (ETU); The 103 sequence Y that during a sign indicating number position (ETU), do not have " groove " of RF energy interruption; Begin to occur the 104 sequence Z of " groove " that RF energy interrupts in a sign indicating number position (ETU); Use the combination of sequence X, Y and Z represent to communicate by letter beginning (SOC), logical zero, logical one and sign off (EOC).
Coding rule according to ISO/IEC14443; The reader acknowledges requests instruction REQA of A type is sexadecimal number 0x26; The mode that adopts low level to send out earlier, Fig. 2 shows radio frequency clock signal RF_CLK, radio frequency input restituted signal RF_IN and a corresponding unit encoding clock ETU_CLK waveform that complete REQA instruction is corresponding.Clock after corresponding non-contact card of RF_CLK or the shaping of RFID tag receiving end radiofrequency signal is the output of Fig. 1 corresponding simulating after signal digitalized; Radio frequency input restituted signal RF_IN be the corresponding simulating signal demodulation of Fig. 1 come out and digitizing after envelope, be the digital signal output that the local demodulation of noncontact card or RFID tag receiving end is come out; These two signals are noncontact card or RFID tag integrated circuit main input signals to improved Miller coding decoder.The ETU_CLK signal is used to identify single sign indicating number position, in wireless signals, does not exist, and need wherein recover out at demoder.
Fig. 3 shows the specification of 106Kbps range signal modulation groove.The width of groove is not fixed, and certain scope is arranged.
Though the demodulator circuit of ISO/IEC14443A signal is simple; But during the signal of identification information " groove ", the receiving integrate circuit of contactless communication can not be coupled to energy and clock from antenna, therefore; The decoding circuit of ISO/IEC14443 standard A type product is complicated, and design difficulty is big.After particularly the speed of data communication improves, use same set of decoding circuit to be applicable to that various code checks are difficult points of integrated circuit related with same decoder design.
In people's such as Qiu Zujiang " a kind of implementation method of improved Miller encoding and decoding (microelectronics, the 30th volume, the 3rd phase, in June, 2000,176-178 page or leaf) ", the author provides a kind of simple, effective decoding circuit to the 106Kbps code check, like Fig. 4.Its signal signal and internal_clk are corresponding respectively radio frequency input restituted signal RF_IN and the radio frequency clock signal RF_CLK among Fig. 2.The document has used " clock circuit " to obtain clk_128, and clk_128 is equivalent to the ETU_CLK among Fig. 2.Different with general counter frequency division, during " groove ", the RF_CLK/Internal_clk signal stops; Therefore; The way of this design is as " groove ", low four of the counter of " clock circuit " resetted, and with low 2 bit in remaining three; Most significant digit remains unchanged, and " groove " just can not appear on the variation edge of clk_128/ETU_CLK like this.This design uses " pulsing circuit " to produce " groove " the identification signal signal that width is 8 carrier frequency clocks.This design is at " groove " when signal occurs; By force frequency counter is carried out set/reset and recover signal to fixed numeric values; Different code rate need be provided with different counter reset/set numerical value, and using for high-speed data communication has two defectives: one, the width of " groove " is not constant, like Fig. 3; " groove " width of different size will recover the different clk_128 of dutycycle (corresponding 212/424/847Kbps should be called clk_64/clk_32/clk_16 respectively); Two, for " groove " and the signal edges of signals of staggering; " groove " identification signal signal occupies 8 carrier frequency clocks; The clk_128 that recovers will have skew with original ideal signal ETU_CLK, and it is inapplicable that this design only has the 847Kbps high speed situations of 16 carrier frequency clocks for an ETU_CLK.
In U.S. Pat 6962293, the inventor has proposed a kind of decoder design that is applicable to various code checks.Like Fig. 5, in this patent, used a preparatory frequency counter Divider that nothing resets, with radio frequency clock signal RF_CLK signal frequency split, according to rate selection signal SEL, the DIV_CLK of output ETU_CLK quadruple rate; Use one three count pick up device RX_IN_CNT, this counter can be resetted by " groove " signal of systematic reset signal SYS_RST or radio frequency input restituted signal RF_IN; One two counter STATE_CNT, the generation state; A clock generates and decoder module, and output improves the decoded non-return-to-zero output of Miller RX_I N, sign indicating number bit clock ETU_RX_CLK, decoded state indication END_OF_RX; " Reset Controller " module of using ETU_RX_CLK to generate the STATE_CNT counter reset.
This patent can be according to the combination of the output data of RX_IN_CNT and two counters of STATE_CNT, obtains logical zero and the logical one of rising edge and negative edge, the RX_IN of ETU_RX_CLK, the state of END_OF_RX respectively.
Compare with previous document; This patent can obtain the recruiting unit encoded clock ETU_RX_CLK consistent with desirable ETU_CLK; And can use the DIV_CLK of code check quadruple; In conjunction with count pick up device RX_IN_CNT and state counter STATE_CNT, provide the output data RX_IN and the sign off indicator signal END_OF_RX of demoder NRZ.Detailed RX_IN_CNT and STATE_CNT timer numerical value and RX_IN, ETU_RX_CLK and END_OF_RX output signal relationship table have also been provided in this patent.
Corresponding states more complicated between decoding output RX_IN, unit encoding clock ETU_RX_CLK and the end communication END_OF_RX and the counter of this patent design is such as corresponding respectively 7 RX_IN_CNT of rising and falling edges and the STATE_CNT combination of ETU_RX_CLK; 3 and the one of four states combination of the logical zero of RX_IN and logical one corresponding RX_IN_CNT of difference and STATE_CNT.In addition, the zero clearing of state counter STATE_CNT depends on the feedback signal RST that obtains through " Reset Controller " module from unit encoding clock ETU_RX_CLK, exists to lag behind.
Summary of the invention
The present invention proposes a kind of decoding circuit of contactless communication integrated circuit; The forward direction design of not having feedback is used in this decoding circuit design; Support the decoding output of the NRZ that accurate unit encoding clock recovery and fixing 1 unit encoding clock lag behind, can support the data decode of different communication speed and reply when providing accurate basic for anti-collision.
According to an aspect of the present invention; A kind of decoding circuit of contactless communication integrated circuit is disclosed; The input signal of this decoding circuit comprises systematic reset signal SYS_RST, radio frequency input restituted signal RF_IN, radio frequency clock signal RF_CLK; The output signal comprises NRZ output signal RX_NRZ and receives indicator signal RX_MOD that this circuit comprises:
The reset frequency divider DIVX of control of band is configured to radio frequency clock signal RF_CLK is carried out frequency division, output frequency division signal DIV_CLKX, and reset according to the position that the groove of radio frequency input restituted signal RF_IN occurs;
Reseting module is configured to produce reset signal RSTN according to systematic reset signal SYS_RST and radio frequency input restituted signal RF_IN;
The counter CT1 of mould X is configured to the reset fractional frequency signal DIV_CLKX of frequency divider DIVX output of control of band is carried out mould X counting, output count signal CNT1, and reset by reseting module output signal RSTN;
Counter CT2, the fractional frequency signal DIV_CLKX that the frequency divider DIVX that is configured to control band is resetted exports counts, and exports count signal CNT2, and is resetted by reseting module output signal RSTN;
Decoded state module DECODE_STATE; Be configured to produce output signal RX_MOD according to radio frequency input restituted signal RF_IN; RF_IN produces output signal SOC_IND according to radio frequency input restituted signal, and CNT2 resets according to systematic reset signal SYS_RST sum counter output signal;
Decoding module ETUX is configured to according to systematic reset signal SYS_RST and decoding block of state output signal SOC_IND, output unit encoded clock ETU_CLKX signal;
Decoded signal sampling module DECODE_SAMPLE, this module is configured to according to systematic reset signal SYS_RST, exports the NRZ RX_NRZ output signal of said decoded signal sampling module DECODE_SAMPLE.
Description of drawings
Through the more detailed description to embodiment of the invention mode in the accompanying drawing, above-mentioned and other purpose, characteristic and advantage of the present invention will become more obvious, and wherein, identical reference number is represented the same parts in the illustrated embodiments of the invention mode usually.
Fig. 1 shows the improvement Miller modulation signals waveform that typical contactless communication integrated circuit receives in the prior art;
Fig. 2 shows REQA instruction radio frequency clock signal RF_CLK, radio frequency input restituted signal RF_IN and corresponding unit encoding clock ETU_CLK waveform complete in the prior art;
Fig. 3 shows the specification of ISO14443 standard 106Kbps range signal modulation groove in the prior art;
Fig. 4 shows a kind of decoding circuit design that simply is applicable to the low speed code check in the prior art;
Fig. 5 shows a kind of decoding circuit design that is applicable to a plurality of speed in the prior art;
Fig. 6 shows the improved Miller coding and decoding of many speed of the present invention circuit;
Fig. 7 shows CNT1 and the CNT2 coding of decoding module output ETU_CLKX of the present invention; And
Fig. 8 shows and uses pairing each signal of the short frame of a reader acknowledges requests of decoder decode of the present invention REQA instruction.
Embodiment
To describe preferred implementation of the present invention in further detail with reference to accompanying drawing, show the preferred embodiments of the present invention in the accompanying drawings.Yet the present invention can should not be construed by the embodiment that sets forth here with the various forms realization and limit.On the contrary, it is in order to make the present invention thorough more and complete that these embodiment are provided, and, fully scope of the present invention is conveyed to those skilled in the art.
Below further combine chart that the present invention is described.
Fig. 6 shows the decoding circuit according to a kind of contactless communication integrated circuit of one embodiment of the present invention, and this circuit is a kind of Miller coding and decoding circuit.The input signal of this decoding circuit comprises systematic reset signal SYS_RST, radio frequency input restituted signal RF_IN, radio frequency clock signal RF_CLK, exports signal and comprises NRZ output signal RX_NRZ and receive indicator signal RX_MOD that this circuit comprises the frequency divider DIVX that band resets and controls; Reseting module; The counter CT1 of mould X, counter CT2, decoded state module DECODE_STATE; Decoding module ETUX, and decoded signal sampling module DECODE_SAMPLE.Specifically:
The reset frequency divider DIVX of control of band is configured to radio frequency clock signal RF_CLK is carried out frequency division, output frequency division signal DIV_CLKX, and reset according to the position that the groove of radio frequency input restituted signal RF_IN occurs.The fractional frequency signal of output can be the output signal of integral frequency divisioils such as 2 frequency divisions, 4 frequency divisions.In one embodiment, this band reset control frequency divider DIVX also according to external input signal SEL, the signal DIV_CLKX of bit rate output 4 frequencys multiplication.The frequency divider DIVX course of work is:
A) the output DIV_CLKX output " low " of frequency divider DIVX groove appears, in response to radio frequency input restituted signal RF_IN;
B) do not have groove in response to radio frequency input restituted signal RF_IN, frequency divider is normally counted, and RF_CLK counts frequency division to the radio frequency clock signal;
C) frequency divider is during counting, according to the DIV_CLKX signal of code rate selection signal output unit code rate 4 frequencys multiplication.
Reseting module is configured to produce reset signal RSTN according to systematic reset signal SYS_RST and radio frequency input restituted signal RF_IN.In one embodiment, can use an end band reverse or (OR) logic realize reseting module.Certainly, one skilled in the art will appreciate that and can also adopt other, such as the logic of tabling look-up, line or, perhaps mode such as state machine realizes reseting module, repeats no more here.
The counter CT1 of mould X is configured to the reset fractional frequency signal DIV_CLKX of frequency divider DIVX output of control of band is carried out mould X counting, output count signal CNT1, and reset by reseting module output signal RSTN.In one embodiment, be the quadruple frequency-dividing clock of code check in response to DIV_CLKX, CT1 is a modulo-three counter.The 2Bit modulo-three counter CT1 course of work is:
A) groove occurs in response to the effective perhaps radio frequency of systematic reset signal SYS_RST signal input restituted signal RF_IN, counter CT1 output CTN1 equals 0;
B) in response to systematic reset signal SYS_RST invalidating signal and frequency-dividing clock output negative edge, counter CT1 adds up 1 and export count results CNT1;
C) count results in response to counter CT1 reaches 3, and counter O reset realizes " mould 3 " output.
Counter CT2, the fractional frequency signal DIV_CLKX that the frequency divider DIVX that is configured to control band is resetted exports counts, and exports count signal CNT2, and is resetted by reseting module output signal RSTN.In one embodiment, be the quadruple frequency-dividing clock of code check in response to DIV_CLKX, can use the counter of 3Bit.The course of work of 3Bit counter CT2 is:
A) groove occurs in response to the effective perhaps radio frequency of systematic reset signal SYS_RST signal input restituted signal RF_IN, counter CT2 output CTN2 equals 0;
B) in response to systematic reset signal SYS_RST invalidating signal and frequency-dividing clock output negative edge, counter CT2 adds up 1 and export count results CNT2;
Reach 7 in response to CNT2, counter stops counting.
Decoded state module DECODE_STATE; Be configured to produce output signal RX_MOD according to radio frequency input restituted signal RF_IN; RF_IN produces output signal SOC_IND according to radio frequency input restituted signal; CNT2 resets according to systematic reset signal SYS_RST sum counter output signal. and in one embodiment, said decoded state module DECODE_STATE further is configured to the negative edge generation output signal RX_MOD according to the groove of radio frequency input restituted signal RF_IN; The rising edge of importing the groove of restituted signal RF_IN according to radio frequency produces output signal SOC_IND, and CNT2 resets according to systematic reset signal SYS_RST sum counter output signal.
In another embodiment, keep low after RX_MOD and SOC_MOD signal reset, next interim when the negative edge of radio frequency input restituted signal RF_IN, RX_MOD puts height; Next interim when the rising edge of radio frequency input restituted signal RF_IN, SOC_IND puts height.The course of work of decoded state module DECODE_STATE is:
A) effective in response to systematic reset signal SYS_RST signal, the rising edge indicator signal SOC_IND output of output SOC " groove " is low;
B) systematic reset signal SYS_RST signal is effective, and demoder accepting state signal RX_MOD output is low;
C) first negative edge of groove in response to radio frequency input restituted signal RF_IN arrives, and height is put in demoder accepting state signal RX_MOD output;
D) first rising edge of groove in response to radio frequency input restituted signal RX_IN arrives, and height is put in output SOC " groove " rising edge indicator signal SOC_IND output;
E) the output CNT2 in response to 3Bit counter CT2 reaches 7, the whole zero clearings of groove rising edge indicator signal SOC_IND of demoder accepting state signal RX_MOD and radio frequency input restituted signal RF_IN.
Decoding module ETUX is configured to according to systematic reset signal SYS_RST and decoding block of state output signal SOC_IND, output unit encoded clock ETU_CLKX signal.In one embodiment; Said decoding module ETUX; Further be configured in response to sub-frequency clock signal DIV_CLKX and change, detection counter output signal CNT2 and CNT2 are according to the numerical value set of CNT1 and the CNT2 unit encoding clock ETU_CLKX signal that perhaps resets.In one embodiment, the unit encoding clock ETU_CLKX course of work of the output signal of decoding module ETUX recovery is:
A) effective in response to systematic reset signal SYS_RST signal, the unit encoding clock signal ETU_CLKX zero clearing of recovery;
B) the groove rising edge indicator signal SOC_IND in response to radio frequency input restituted signal RF_IN is high, and the unit encoding clock signal ETU_CLKX of recovery allows upset;
C) be " 00 ", " 22 ", " 41 " and " 60 " in response to the output CNT1 of 2Bit modulo-three counter CT1 and the output CNT2 of 3Bit counter CT2; The designature that the unit encoding clock signal ETU_CLKX that recovers gets laststate; Be " 0 " just in response to laststate; Then CNT1 and CNT2 are that above-mentioned data are right, and ETU_CLKX exports " 1 "; Otherwise perhaps.
Decoded signal sampling module DECODE_SAMPLE, this module is configured to according to systematic reset signal SYS_RST, exports the NRZ RX_NRZ output signal of said decoded signal sampling module DECODE_SAMPLE.In one embodiment; Decoded signal sampling module DECODE_SAMPLE comprises intermediate variable, and this decoded signal sampling module DECODE_SAMPLE further is configured to according to systematic reset signal SYS_RST, removes intermediate variable; Wherein response arrives with the rising edge of radio frequency input restituted signal RF_IN; To middle variable set,, middle variable is carried out inversion operation in response to the rising edge arriving of unit encoding clock ETU_CLKX; Arrive in response to unit encoding clock ETU_CLKX negative edge, middle variable is sampled and as the NRZ RX_NRZ output signal of module.
In one embodiment, can use register, be used in the middle of two state transformations, keeping original value as intermediate variable.Those skilled in the art can also adopt other, such as random access memory, and FeRAM, the storage unit of RRRAM etc. repeats no more as intermediate variable here.
In one embodiment, the course of work of the NRZ of the output encoder demoder of decoding and sampling module DECODE_SAMPLE output RX_NRZ is:
Effective in response to systematic reset signal SYS_RST signal, inner sample register is put height;
B) first rising edge of groove in response to radio frequency input restituted signal RF_IN arrives, and inner sample register intermediate variable is put height;
C) rising edge in response to the unit encoding clock ETU_CLKX that recovers arrives, and inner sample register intermediate variable is got the designature of current state;
D) negative edge of the unit encoding clock ETU_CLKX that recovers arrives, the take a sample signal of inner sample register and as the output of RX_NRZ of the NRZ output RX_NRZ of demoder.
The present invention can pass through the composite design of decoded state module, decoding module and the decoded signal sampling module of frequency counter, reseting module, mould X counter 1, counter 2, the detection of groove edge; Can export, be provided with the counting step of the mould X sum counter CT2 of mould X counter CT1 through selecting the different fractional frequency signal of frequency counter; To the communication code check and different groove specifications of different ETU width, decode the unit encoding clock ETU_CLKX of unitary code position ETU width, non return to zero coding RX_NRZ and decoding output indicator signal RX_MOD; Entire decoder adopts the forward direction design of not having feedback; Support accurate unit encoding clock ETU_CLKX to recover and the decoding output of the NRZ that fixing 1 unit encoding clock ETU lags behind, can support the data decode of different communication speed and reply when providing accurate basic for anti-collision.
Below with the example that is designed to of 4 frequency division output frequency division signals, then mould X counter CT1 adopts the modulo-three counter of 2Bit, it is example that counter CT2 adopts the counter of 3Bit, describes the decoding circuit course of work in detail.
The inventor through enumerate fully analyze possible flanking sequence Y pattern; Find; If use the groove zero clearing of radio frequency input restituted signal RF_IN to handle to frequency-dividing clock DIV_CLKX, after then each radio frequency clock signal RF_CLK recovered, DIV_CLKX began from rising edge; Disregard that DIV_CLKX negative edge overlapping, DIV_CLKX negative edge quantity and corresponding codes such as table 1 between the adjacent grooves with the ETU_CLK edge.
The width of a DIV_CLKX is 1/4th of 1 sign indicating number bit width ETU_CLK, and therefore, the method for the negative edge that removal and ETU_CLK edge are overlapping will cause method that the precision of groove is had very high adaptive faculty.
DIV_CLKX negative edge quantity and corresponding codes between the table 1 flanking sequence groove
Can use the counter cnt 2 of radio frequency input restituted signal RF_IN zero clearing to calculate DIV_CLKX negative edge quantity between the adjacent radio frequency input restituted signal RF_IN groove; Count value in response to counter reaches 7, the expression sign off.If on this basis, but increase a counter CT1 who fixes with the counting step of above-mentioned counter synchronisation zero clearing.CT1 combines two counters as the short scale of " slip " on CT2, the edge that identifies unit encoding clock ETU_CLK that just can be correct.The maximum count value of getting CT1 here is 2, therefore be called " modulo-three counter ", correspondence table 1 be the minimum length of adjacent grooves DIV_CLKX negative edge number.
Here the unit encoding clock ETU_CLK that recovers to come out is called ETU_CLKX.On the basis that recovers unit encoding clock ETU_CLKX; Just can be through the set register intermediate variable specific with upset; And use the negative edge of the unit encoding clock ETU_CLKX that recovers that the content of register intermediate variable is carried out digital sample, just can recover and improve the corresponding serial non-return-to-zero data of Miller coding.
Be with the frequency counter of the frequency divider DIVX of the control that resets to import restituted signal RF_IN zero clearing, select suitable output frequency division DIV_CLKX by the SEL signal by radio frequency.In a kind of embodiment, the DIV_CLKX frequency is four times of unit encoding clock ETU_CLK.Such as, the code check of corresponding 106Kbps, the signal frequency of DIV_CLKX output is 424KHz; Analogize, the frequency of the corresponding DIV_CLKX of the code check of 212Kbps is 847KHz; The frequency of the corresponding DIV_CLKX of the code check of 424Kbps is 1.69MHz; The frequency of the DIV_CLKX that the 847Kbps code check is corresponding is 3.39MHz.When selecting the code check of two-forty, the frequency-dividing clock output that is lower than corresponding DIV_CLKX is not forbidden, thus the power consumption of reduction circuit.
The counter CT1 of 2Bit mould 3 is resetted by system reset SYS_RST signal or radio frequency input restituted signal RF_IN.Reset signal in response to counter CT1 is invalid, counter CT1 to DIV_CLKX pulse count, counting step mould 3 that is to say, count results is circulation 0,1, between 2, and the output count results is to CT1.
The counter CT2 of 3Bit is resetted by system reset SYS_RST signal or radio frequency input restituted signal RF_IN; Reset signal in response to counter CT2 is invalid; Counter CT2 to DIV_CLKX pulse count; Count results is circulation 0,1,2,3,4,5,6, between 7, and the output count results is to CNT2.
Decoded state module DECODE_STATE has two outputs SOC_IND and RX_MOD, respectively by rising edge and the negative edge set of radio frequency input restituted signal RF_IN, and removing when the output of CT2 counting reaches maximum count numerical value 7.Therefore SOC_IND is in the rising edge action of " communication begins " signal SOC, until sign off; RX_MOD is in the negative edge action of " communication begins " signal SOC, until sign off.SOC_IND is used for indication " decoding module ETUX " and starts working.
Table 2 shows the ETU_CLKX upset input state table of decoding module ETUX.Decoding module ETUX removes output ETU_CLKX by system reset SYS_RST; When SOC_IND effectively after, trigger by the negative edge of DIV_CLKX, whenever counter CT1 and CT2 output CNT1 and CNT2 data in the table 2 occur right the time, ETU_CLKX reverses.Because the particular design of CNT1 and CNT2, ETU_CLKX can recover desirable unit encoding clock.Fig. 7 shows decoding module output ETU_CLKX of the present invention upset corresponding CNT1 and CNT2 coding.Among the figure, " SEQ " sequence comprised " communication beginning " (SOC), (EOC) corresponding improvement Miller coding of B1-B7 data, " sign off "; Each binary digit is used 4 binary number representations, corresponding 4 DIV_CLKX cycles; Use the groove in the improved Miller coding of " 0 " expression.The particular design of CNT1 and CNT2 is that coding for the CNT1 of ETU_CLKX upset and CNT2 except 0-0 makes up, is unique; And, do not have the DIV_CLKX negative edge to trigger for the 0-0 combination, therefore, can not upset appear in the position at non-ETU_CLK edge.
The ETU_CLKX upset input state table of table 2 decoding module ETUX
| | CNT2 | |
| 0 | 0 | |
| 2 | 2 | |
| 4 | 1 | |
| 6 | 0 |
Decoding and sampling module DECODE_SAMPLE is resetted by systematic reset signal SYS_RST.After resetting, decoding output data RX_NRZ is output as " height ".The decoding and sampling module is according to radio frequency input restituted signal RF_IN, by the rising edge set internal register intermediate variable sampled data of groove signal; Rising edge by ETU_CLKX carries out " negate " operation to internal register intermediate variable sampled data; By the negative edge of ETU_CLKX the internal register intermediate variable is sampled and to obtain decoding output RX_NRZ.(for sequence X, it is overlapping that radio frequency is imported the rising edge of negative edge and ETU_CLKX of groove of restituted signal RF_IN because the rising edge of ETU_CLKX and negative edge meet with the groove rising edge of radio frequency input restituted signal RF_IN never; For sequence Z, the negative edge of the groove of radio frequency input restituted signal RF_IN and the negative edge of ETU_CLKX are overlapping.For the 847KHz top speed coding of ISO14443A, the groove rising edge of radio frequency input restituted signal RF_IN and the shortest 4 oscillation period at interval of rising edge of ETU_CLKX), therefore, sampled measurements is reliable.
The said improved Miller coding decoder design of whole invention has used the frequency counter of band clear terminal to obtain the frequency-dividing clock DIV_CLKX of 4 times of unit encoding clock ETU_CLK; Therefore, decoded result had both guaranteed that precision had the fluctuation at " groove " edge that can bear the raw data coding; Demoder does not use feedback element, so speed is fast, and it is little to lag behind; Use the negative edge sampling of ETU_CLKX; The data of data and the transmission of the decoding fixing ETU that only lags behind is beneficial to alignment of data, and aliging for the sign indicating number position of anti-collision answering provides good basis.
Describe in conjunction with above-mentioned invention, a REQA orders each signal that uses coding decoder of the present invention to relate to as shown in Figure 8.The output unit encoded clock ETU_CLKX signal that comprises decoding module ETUX among Fig. 8; The NRZ RXNRZ waveform of the intermediate variable waveform of decoding and sampling module DECODE_SAMPLE, output; The positive and negative periodic waveform symmetry of ETU_CLKX is good; Each yard bit period and radio frequency input restituted signal RF_IN groove data edge consistance are high; NRZ RXNRZ output is compared with input signal and is postponed a fixing unitary code bit period, is convenient to control accurately response time, base when providing accurate for sign indicating number position anti-collision.
Above-described specific embodiment has carried out further explain to the object of the invention, technical scheme and beneficial effect.Institute it should be understood that the above is merely specific embodiment of the present invention, is not limited to the present invention, such as, system reset SYS_RST of the present invention has adopted high level to reset; The groove that improves the Miller coding adopts low level to represent, therefore, the input that resets of CT1 and CT2 adopt an end band reverse " or " the logic composite signal, if adopt the low level reset mechanism, then corresponding reseting logic also will be done targetedly and adjust.All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the decoding circuit of a contactless communication integrated circuit; The input signal of this decoding circuit comprises systematic reset signal SYS_RST, radio frequency input restituted signal RF_IN, radio frequency clock signal RF_CLK; The output signal comprises NRZ output signal RX_NRZ and receives indicator signal RX_MOD that this circuit comprises:
The reset frequency divider DIVX of control of band is configured to radio frequency clock signal RF_CLK is carried out frequency division, output frequency division signal DIV_CLKX, and reset according to the position that the groove of radio frequency input restituted signal RF_IN occurs;
Reseting module is configured to produce reset signal RSTN according to systematic reset signal SYS_RST and radio frequency input restituted signal RF_IN;
The counter CT1 of mould X is configured to the reset fractional frequency signal DIV_CLKX of frequency divider DIVX output of control of band is carried out mould X counting, output count signal CNT1, and reset by reseting module output signal RSTN;
Counter CT2 is configured to the reset fractional frequency signal DIV_CLKX of frequency divider DIVX output of control of band is counted, output count signal CNT2, and reset by reseting module output signal RSTN;
Decoded state module DECODE_STATE; Be configured to produce output signal RX_MOD according to radio frequency input restituted signal RF_IN; RF_IN produces output signal SOC_IND according to radio frequency input restituted signal, and CNT2 resets according to systematic reset signal SYS_RST sum counter output signal;
Decoding module ETUX is configured to according to systematic reset signal SYS_RST and decoding block of state output signal SOC_IND, output unit encoded clock ETU_CLKX signal;
Decoded signal sampling module DECODE_SAMPLE, this module is configured to according to systematic reset signal SYS_RST, exports the NRZ RX_NRZ output signal of said decoded signal sampling module DECODE_SAMPLE.
2. decoding circuit according to claim 1; Wherein said decoded state module DECODE_STATE; Further be configured to negative edge generation output signal RX_MOD according to the groove of radio frequency input restituted signal RF_IN; The rising edge of importing the groove of restituted signal RF_IN according to radio frequency produces output signal SOC_IND, and CNT2 resets according to systematic reset signal SYS_RST sum counter output signal.
3. decoding circuit according to claim 1 and 2; Wherein said decoding module ETUX; Further be configured in response to sub-frequency clock signal DIV_CLKX and change; Detection counter output signal CNT2 and CNT2 are according to the numerical value set of CNT1 and CNT2 or the unit encoding clock ETU_CLKX signal that resets.
4. according to the described decoding circuit of one of claim 1-3; Wherein said decoded signal sampling module DECODE_SAMPLE comprises intermediate variable, and this decoded signal sampling module DECODE_SAMPLE further is configured to according to systematic reset signal SYS_RST, removes intermediate variable; Wherein the rising edge in response to radio frequency input restituted signal RF_IN arrives; To middle variable set,, middle variable is carried out inversion operation in response to the rising edge arriving of unit encoding clock ETU_CLKX; Arrive in response to unit encoding clock ETU_CLKX negative edge, middle variable is sampled and as the NRZ RX_NRZ output signal of module.
5. according to the described decoding circuit of one of claim 1-4; Wherein said band reset control frequency divider DIVX also according to external input signal SEL; The signal DIV_CLKX of bit rate output 4 frequencys multiplication, the counter CT1 of wherein said mould X is a modulo-three counter, wherein said counter CT2 is the counter of 3Bit; Wherein said reseting module be an end band reverse or (OR) logic, wherein said intermediate variable is a register.
6. decoding circuit according to claim 5, the wherein said frequency divider DIVX course of work is:
A) the output DIV_CLKX output " low " of frequency divider DIVX groove appears, in response to radio frequency input restituted signal RF_IN;
B) there is not groove in response to radio frequency input restituted signal RF_IN, the frequency divider counting, RF_CLK counts frequency division to the radio frequency clock signal;
C) frequency divider is during counting, according to the DIV_CLKX signal of code rate selection signal output unit code rate 4 frequencys multiplication;
The wherein said modulo-three counter CT1 course of work is:
A) groove occurs in response to the effective perhaps radio frequency of systematic reset signal SYS_RST signal input restituted signal RF_I N, counter CT1 output CTN1 equals 0;
B) in response to systematic reset signal SYS_RST invalidating signal and frequency-dividing clock output negative edge, counter CT1 adds up 1 and export count results CNT1;
C) count results in response to counter CT1 reaches 3, and counter O reset realizes " mould 3 " output;
The course of work of wherein said counter CT2 is:
A) groove occurs in response to the effective perhaps radio frequency of systematic reset signal SYS_RST signal input restituted signal RF_IN, counter CT2 output CTN2 equals 0;
B) in response to systematic reset signal SYS_RST invalidating signal and frequency-dividing clock output negative edge, counter CT2 adds up 1 and export count results CNT2;
Reach 7 in response to CNT2, counter stops counting.
7. decoding circuit according to claim 6, the course of work of wherein said decoded state module DECODE_STATE is:
A) effective in response to systematic reset signal SYS_RST signal, the rising edge indicator signal SOC_IND output of output SOC " groove " is low;
B) systematic reset signal SYS_RST signal is effective, and demoder accepting state signal RX_MOD output is low;
C) first negative edge of groove in response to radio frequency input restituted signal RF_IN arrives, and height is put in demoder accepting state signal RX_MOD output;
D) first rising edge of groove in response to radio frequency input restituted signal RX_IN arrives, and height is put in output SOC " groove " rising edge indicator signal SOC_IND output;
E) the output CNT2 in response to 3Bit counter CT2 reaches 7, the groove rising edge indicator signal SOC_IND zero clearing of demoder accepting state signal RX_MOD and radio frequency input restituted signal RF_IN.
8. decoding circuit according to claim 7, the unit encoding clock ETU_CLKX course of work that the output signal of wherein said decoding module ETUX recovers is:
A) effective in response to systematic reset signal SYS_RST signal, the unit encoding clock signal ETU_CLKX zero clearing of recovery;
B) the groove rising edge indicator signal SOC_IND in response to radio frequency input restituted signal RF_IN is high, and the unit encoding clock signal ETU_CLKX of recovery allows upset;
C) be " 0 " in response to laststate, then CNT1 and CNT2 are that above-mentioned data are right, and ETU_CLKX exports " 1 "; Otherwise perhaps, wherein, be " 00 ", " 22 ", " 41 " and " 60 " in response to the output CNT2 of the output CNT1 sum counter CT2 of modulo-three counter CT1, the designature that the unit encoding clock signal ETU_CLKX of recovery gets laststate.
9. decoding circuit according to claim 8, the course of work of the NRZ output RX_NRZ of the output encoder demoder of wherein said decoding and sampling module DECODE_SAMPLE is:
A) effective in response to systematic reset signal SYS_RST signal, inner sample register is put height;
B) first rising edge of groove in response to radio frequency input restituted signal RF_IN arrives, and inner sample register intermediate variable is put height;
C) rising edge in response to the unit encoding clock ETU_CLKX that recovers arrives, and inner sample register intermediate variable is got the designature of current state;
D) negative edge of the unit encoding clock ETU_CLKX that recovers arrives, the take a sample signal of inner sample register and as the output of RX_NRZ of the NRZ output RX_NRZ of demoder.
10. keep low after decoding circuit according to claim 5, wherein said RX_MOD and SOC_MOD signal reset, next interim when the negative edge of radio frequency input restituted signal RF_IN, RX_MOD puts height; Next interim when the rising edge of radio frequency input restituted signal RF_IN, SOC_IND puts height.
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