CN102594371B - The method of a kind of Turbo code interleaving process and device - Google Patents
The method of a kind of Turbo code interleaving process and device Download PDFInfo
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- CN102594371B CN102594371B CN201110020455.6A CN201110020455A CN102594371B CN 102594371 B CN102594371 B CN 102594371B CN 201110020455 A CN201110020455 A CN 201110020455A CN 102594371 B CN102594371 B CN 102594371B
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Abstract
The present invention relates to communication technical field, in order to solve in prior art in Turbo code rate matching process, the problem of logic control complexity during interleaving treatment, a kind of method providing Turbo code rate to mate and device, the method comprises: collect the 3rd road output stream that Turbo encoder exports, the second matrix is obtained after directly carrying out interleaving treatment by the 3rd road output stream, due to the 3rd road output stream is directly carried out interleaving treatment, do not need in interleaving procedure to read RAM, logic control is realized simple.
Description
Technical field
The present invention relates to communication technical field, particularly relate to method and the device of a kind of Turbo code rate coupling.
Background technology
Rate-matched technology has been used, in order to balance the data volume of input and output when balancing input and output data in LTE system.For different channel coding methods, in LTE, employ Turbo code rate matching technique and convolutional code rate matching technique respectively.
Compared with mating with convolutional code rate, turbo code rate coupling is more complex.Turbo code rate coupling not only can operate as required from the diverse location of data flow, and needs to export three tunnels of turbo encoder before treatment carry out different intertextures and just can start bit selection operation after being spliced into two matrixes.
In prior art, existing problems are as follows, in Turbo code rate matching process, time interleaving treatment is carried out to the 3rd road output stream of turbo encoder, need to read from random access memory ram and fill the 3rd road output stream after process through inactive bit, carry out interleaving treatment, such meeting, can the continuous saltus step in address of RAM instead of continuous print change because need in interleaving procedure to read RAM, makes the control logic producing address can become very complicated.
Summary of the invention
In order to solve in prior art in Turbo code rate matching process, the problem of logic control complexity during interleaving treatment, the invention provides method and the device of the process of a kind of Turbo code interleaving.
The method of a kind of Turbo code interleaving process that the embodiment of the present invention provides, comprising:
Collect the 3rd road output stream that Turbo encoder exports;
The second matrix is obtained after directly carrying out interleaving treatment by the 3rd road output stream;
Wherein, obtain the second matrix after directly carrying out interleaving treatment by the 3rd road output stream to comprise:
Carry out inactive bit filling process by the 3rd road output stream and obtain the first matrix, first matrix column number is 32, line number is the long-pending smallest positive integral being more than or equal to the bit number of the 3rd road output stream be multiplied with 32, from first row, inactive bit is filled with in the first row of the first matrix, the quantity of inactive bit is the long-pending of the first matrix column number and line number, deduct the bit number difference of the 3rd road output stream, the data that other position that first matrix does not fill inactive bit is deposited are from the first row to last column, often row arranges from first row to last, be followed successively by the data by exporting in tactic 3rd road output stream,
According to
directly carrying out interleaving treatment to the first matrix obtains the second matrix, and wherein, π (k) represents the sequence number of data in the first matrix, and k represents the sequence number of data in the second matrix, and P represents permutation function,
represent the line number at the first matrix,
represent at the first matrix column number,
permutation function P represents as table
<0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23, in 15,31> 0 represents that the first matrix the 1st arranges, and 16 represent that the first matrix the 17th arranges, 31 represent that the first matrix the 32nd arranges
in P (0) represent the second matrix first row, P (1) represents the second matrix secondary series,
represent last row of the second matrix.
Further comprise, the second matrix is directly existed in random access memory ram.
Further comprise, shifting function is carried out to the second matrix and obtains the 3rd matrix, and the 3rd matrix is existed in random access memory ram, second matrix column number is 32, the data of last column of the 3rd matrix are by after rear 31 bit data in second matrix last column, the data of splicing the second matrix the first row first row are formed, the data of other row of the 3rd matrix are by after rear 31 bit data in the row that the second matrix line number is identical, and the data of splicing the second matrix next line first row are formed.
The embodiment of the present invention additionally provides the device of a kind of Turbo code interleaving process, comprising:
Data collection module, for collecting the 3rd road output stream that Turbo encoder exports;
Sub-block interleaving block, obtains the second matrix after directly carrying out interleaving treatment by the 3rd road output stream;
Wherein, described sub-block interleaving block is used for carrying out inactive bit filling process by the 3rd road output stream and obtains the first matrix, first matrix column number is 32, line number is the long-pending smallest positive integral being more than or equal to the bit number of the 3rd road output stream be multiplied with 32, from first row, inactive bit is filled with in the first row of the first matrix, the quantity of inactive bit is the long-pending of the first matrix column number and line number, deduct the bit number difference of the 3rd road output stream, the data that other position that first matrix does not fill inactive bit is deposited are from the first row to last column, often row arranges from first row to last, be followed successively by the data by exporting in tactic 3rd road output stream,
According to
directly carrying out interleaving treatment to the first matrix obtains the second matrix, and wherein, π (k) represents the sequence number of data in the first matrix, and k represents the sequence number of data in the second matrix, and P represents permutation function,
represent the line number at the first matrix,
represent at the first matrix column number,
permutation function P represents as table
<0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23, in 15,31> 0 represents that the first matrix the 1st arranges, and 16 represent that the first matrix the 17th arranges, 31 represent that the first matrix the 32nd arranges
in P (0) represent the second matrix first row, P (1) represents the second matrix secondary series,
represent last row of the second matrix.
Further, sub-block interleaving block, also for directly being existed in random access memory ram by the second matrix.
Further, sub-block interleaving block, also obtain the 3rd matrix for carrying out shifting function to the second matrix, and the 3rd matrix is existed in random access memory ram, second matrix column number is 32, the data of last column of the 3rd matrix are by after rear 31 bit data in second matrix last column, the data of splicing the second matrix the first row first row are formed, the data of other row of the 3rd matrix are by after rear 31 bit data in the row that the second matrix line number is identical, and the data of splicing the second matrix next line first row are formed.
The scheme that the embodiment of the present invention provides, due to the 3rd road output stream is directly carried out interleaving treatment, does not need in interleaving procedure to read RAM, logic control is realized simple.Technique effect about the present embodiment scheme is described as follows: null bit only exists in the first row with original matrix, but the intertexture result due to the 3rd road output stream is not only the rank transformation of data, when 31 in the result of P function, due to below add one effect, cause these data needs from interweave after matrix next line first row obtain.From RAM, the scheme that the 3rd road output stream after carrying out inactive bit filling process carries out interleaving treatment is read if also adopted, when read data, saltus step and can not consecutive variations just constantly must be carried out in the address of RAM, makes the control logic producing address can become very complicated.
Original matrix the 0th row the 0th row are before interleaving bound to be filled to be null bit, and in rate adaptation operating process, to turbo encoder export the 3rd road output stream do interweave time, the bit that 3rd circuit-switched data exports will be placed to last row of the 3rd circuit-switched data through the bit of filling the 0th row of the matrix formed, a line and data all in these row have all moved up, and uppermost bit has been moved to last column. in whole interleaving process, also the bit having the 0th row of input only there occurs shifting function in the ranks in interleaving process, all there is not this change in all bits of other row.
Accordingly, in hardware implementing process, can when formation interleaver matrix, rear 31 data of the first row before intertexture are added that first data of the second row are stitched together, form the first row data of interleaver matrix, do like this and be also very easy to, do once to be shifted namely can realize more in the output of data collection phase to the 3rd circuit-switched data.Afterwards, when the data forming last column, first row data due to the first row are a null bit certainly, this bit has been moved to last row of last column of interleaver matrix in interleaving process, only need remember that last row of last column of this interleaver matrix must be null bits.Afterwards, only need by arranging sense data from matrix and identifying null bit.
Accompanying drawing explanation
The method flow diagram that Fig. 1 provides for the embodiment of the present invention;
The structure drawing of device that Fig. 2 provides for the embodiment of the present invention.
Embodiment
Be described in detail below in conjunction with the technical scheme of accompanying drawing to the embodiment of the present invention.
From the matrix to be read be stored in RAM, read data, carry out bit collection, selection and transmission process.
The present embodiment provides the method flow of a kind of Turbo code interleaving process to comprise as shown in Figure 1:
Step 101: collect the 3rd road output stream that Turbo encoder exports.
Step 102: carry out the process of invalid null bit padding by the 3rd road output stream of Turbo encoder and obtain original matrix.
In the present embodiment, the 3rd road output stream of Turbo encoder is that 157bits is expressed as D, D=<d
0, d
1... d
i... d
156>, the wherein integer of 0≤i≤156, d
0be the Bit data that the 3rd road output stream first exports, d
1be the Bit data that the 3rd road output stream second exports, d
ibe the Bit data that the 3rd road output stream i-th exports, d
156it is last Bit data exported of the 3rd road output stream.
Output stream D is carried out inactive bit filling process and obtain original matrix, the columns of original matrix is 32, line number is 5, namely following principle should be met, the long-pending smallest positive integral being more than or equal to the bit number 157 of the 3rd road output stream be multiplied with 32 is 5, line number is 5, from first row, inactive bit is filled with in the first row of original matrix, the quantity of inactive bit is 3, the i.e. columns 32 of original matrix and long-pending 160 of line number 5, deduct the difference of the data bit number 157 of the 3rd road output stream, the data that other position of original matrix is deposited are from the first row to last column, often row arranges from first row to last, be followed successively by the data by exporting in tactic 3rd road output stream, in the first row of the original matrix namely in the present embodiment, front 3 are classified as inactive bit, terminate to one's own profession 4th row from the first row, be followed successively by d
0, d
1... d
27, d
28., terminate to one's own profession first row from the second row, be followed successively by d
29, d
30... d
59, d
60., terminate to one's own profession first row from the third line, be followed successively by d
61, d
62... d
91, d
92, terminate to one's own profession first row from fourth line, be followed successively by d
93, d
94... d
123, d
124, terminate to one's own profession first row from fifth line, be followed successively by d
125, d
126... d
155, d
156, be expressed as at original matrix:
, wherein,
line number the present embodiment of expression original matrix is 5,
columns the present embodiment of expression original matrix is 32.The present embodiment original matrix also can be expressed as
wherein original matrix data y
0, y
1... y
159subscript 0,1...159, represent y
0, y
1... y
159sequence number π (k).
Step 103: obtain the matrix after interweaving after directly carrying out interleaving treatment by original matrix, and the matrix after interweaving is existed in random access memory ram.
According to
directly right
carry out interleaving treatment and obtain the matrix after interweaving, wherein, π (k) represents the sequence number of data in original matrix, and k represents the sequence number of data in the matrix after intertexture,
p represents permutation function, and permutation function P is expressed as follows table 1.
Table 1
<0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23,15,31> represent the columns that original matrix respectively arranges,
in P (0) represent interweave after matrix first row, P (1) represent interweave after matrix secondary series,
represent last row of the matrix after interweaving.Data in matrix after intertexture
with original matrix y
π (k)between there is following corresponding relation,
such as k=0, π (k)=1,
similar k=1, π (k)=33; K=2, π (k)=65; K=3, π (k)=97; K=4, π (k)=129; K=5, π (k)=17; K=6, π (k)=49; K=155, π (k)=32; K=156, π (k)=64, k=157, π (k)=96; K=158, π (k)=128; K=159, π (k)=0; Matrix notation after intertexture is:
No longer original matrix is existed in RAM in this step, but directly carry out interleaving treatment by original matrix and obtain the matrix after interweaving.
Step 104: read data from the matrix after the intertexture be stored in RAM, carries out bit collection, selection and transmission process.
Matrix after the intertexture be stored in RAM
middle reading data, carry out bit collection, selection and transmission process, if the data read are non-inactive bit, select these data to transmit, otherwise do not select these data to carry out transmission process.
Certainly can also by the matrix after intertexture
carry out shifting function obtain shifting processing after matrix, the matrix notation after shifting processing is
matrix after shifting processing is existed in random access memory ram, below the formation of this matrix is described, matrix column number after intertexture is 32, the data of last column of the matrix after shifting processing are by after rear 31 bit data in matrix last column after interleaving, the data of the matrix the first row first row after splicing interweaves are formed, the data of other row of the matrix after shifting processing are by after rear 31 bit data in the identical row of matrix line number after interleaving, and the data of the matrix next line first row after splicing interweaves are formed.Be no matter using shifting processing after matrix exist in RAM as matrix to be read, or the matrix after interweaving directly is existed in RAM as matrix to be read, this matrix to be read that all will obtain according to the matrix after intertexture, difference is, matrix after shifting processing needs to utilize more resource when being formed, and logic control is comparatively simple when reading, matrix after intertexture utilizes resource less when being formed, and matrix solution when reading after relative shifting processing, logic control is comparatively complicated, but with the 3rd road output stream carry out inactive bit fill process after the scheme logic control of directly reading simple.
Below the technique effect of the present embodiment scheme is described, null bit only exists in the first row with original matrix, but the intertexture result due to the 3rd road output stream is not only the rank transformation of data, when 31 in the result of P function, due to below add one effect, cause these data needs from interweave after matrix next line first row obtain.From RAM, the scheme that the 3rd road output stream after carrying out inactive bit filling process carries out interleaving treatment is read if also adopted, when read data, saltus step and can not consecutive variations just constantly must be carried out in the address of RAM, makes the control logic producing address can become very complicated.
Original matrix the 0th row the 0th row are before interleaving bound to be filled to be null bit, and in rate adaptation operating process, to turbo encoder export the 3rd road output stream do interweave time, the bit that 3rd circuit-switched data exports will be placed to last row of the 3rd circuit-switched data through the bit of filling the 0th row of the matrix formed, a line and data all in these row have all moved up, and uppermost bit has been moved to last column. in whole interleaving process, also the bit having the 0th row of input only there occurs shifting function in the ranks in interleaving process, all there is not this change in all bits of other row.
Accordingly, in hardware implementing process, can when formation interleaver matrix, rear 31 data of the first row before intertexture are added that first data of the second row are stitched together, form the first row data of interleaver matrix, do like this and be also very easy to, do once to be shifted namely can realize more in the output of data collection phase to the 3rd circuit-switched data.Afterwards, when the data forming last column, first row data due to the first row are a null bit certainly, this bit has been moved to last row of last column of interleaver matrix in interleaving process, only need remember that last row of last column of this interleaver matrix must be null bits.Afterwards, only need by arranging sense data from matrix and identifying null bit.
The embodiment of the present invention additionally provides the device of a kind of Turbo code interleaving process, as shown in Figure 2, comprising:
Data collection module 201, for collecting the 3rd road output stream that Turbo encoder exports;
Sub-block interleaving block 202, obtains the second matrix after directly carrying out interleaving treatment by the 3rd road output stream.
Further, sub-block interleaving block 202, also for directly being existed in random access memory ram by the second matrix.
Further, sub-block interleaving block 202, also obtain the 3rd matrix for carrying out shifting function to the second matrix, and the 3rd matrix is existed in random access memory ram, second matrix column number is 32, the data of last column of the 3rd matrix are by after rear 31 bit data in second matrix last column, the data of splicing the second matrix the first row first row are formed, the data of other row of the 3rd matrix are by after rear 31 bit data in the row that the second matrix line number is identical, and the data of splicing the second matrix next line first row are formed.
Further, sub-block interleaving block 202, also obtain the first matrix for being carried out inactive bit filling process by the 3rd road output stream, first matrix column number is 32, line number is the long-pending smallest positive integral being more than or equal to the bit number of the 3rd road output stream be multiplied with 32, from first row, inactive bit is filled with in the first row of the first matrix, the quantity of inactive bit is the long-pending of the first matrix column number and line number, deduct the data bit number difference of the 3rd road output stream, the data that other position of first matrix is deposited are from the first row to last column, often row arranges from first row to last, be followed successively by the data by exporting in tactic 3rd road output stream, directly carry out interleaving treatment according to the first matrix and obtain the second matrix.
Further, sub-block interleaving block 202, also for basis
directly carrying out interleaving treatment to the first matrix obtains the second matrix, and wherein, π (k) represents the sequence number of data in the first matrix, and k represents the sequence number of data in the second matrix, and P represents permutation function,
represent the line number at the first matrix,
represent at the first matrix column number,
permutation function P represents as table
<0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23,15,31> represent the columns that the first matrix respectively arranges,
p (0) represents the second matrix first row, and P (1) represents the second matrix secondary series ...,
represent last row of the second matrix.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (6)
1. a method for Turbo code interleaving process, is characterized in that, comprising:
Collect the 3rd road output stream that Turbo encoder exports;
The second matrix is obtained after directly carrying out interleaving treatment by the 3rd road output stream;
Wherein, described directly carry out interleaving treatment by the 3rd road output stream after obtain the second matrix and be specially:
Carry out inactive bit filling process by the 3rd road output stream and obtain the first matrix, first matrix column number is 32, line number is the long-pending smallest positive integral being more than or equal to the bit number of the 3rd road output stream be multiplied with 32, from first row, inactive bit is filled with in the first row of the first matrix, the quantity of inactive bit is the long-pending of the first matrix column number and line number, deduct the bit number difference of the 3rd road output stream, the data that other position that first matrix does not fill inactive bit is deposited are from the first row to last column, often row arranges from first row to last, be followed successively by the data by exporting in tactic 3rd road output stream,
According to
directly carrying out interleaving treatment to the first matrix obtains the second matrix, and wherein, π (k) represents the sequence number of data in the first matrix, and k represents the sequence number of data in the second matrix, and P represents permutation function,
represent the line number at the first matrix,
represent at the first matrix column number,
permutation function P represents as table
<0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23, in 15,31> 0 represents that the first matrix the 1st arranges, and 16 represent that the first matrix the 17th arranges, 31 represent that the first matrix the 32nd arranges
in P (0) represent the second matrix first row, P (1) represents the second matrix secondary series,
represent last row of the second matrix.
2. the method for claim 1, is characterized in that, also comprises:
Second matrix is directly existed in random access memory ram.
3. the method for claim 1, is characterized in that, also comprises:
Shifting function is carried out to the second matrix and obtains the 3rd matrix, and the 3rd matrix is existed in random access memory ram, second matrix column number is 32, the data of last column of the 3rd matrix are by after rear 31 bit data in second matrix last column, the data of splicing the second matrix the first row first row are formed, the data of other row of the 3rd matrix are by after rear 31 bit data in the row that the second matrix line number is identical, and the data of splicing the second matrix next line first row are formed.
4. a device for Turbo code interleaving process, is characterized in that, comprising:
Data collection module, for collecting the 3rd road output stream that Turbo encoder exports;
Sub-block interleaving block, obtains the second matrix after directly carrying out interleaving treatment by the 3rd road output stream;
Wherein, described sub-block interleaving block is used for carrying out inactive bit filling process by the 3rd road output stream and obtains the first matrix, first matrix column number is 32, line number is the long-pending smallest positive integral being more than or equal to the bit number of the 3rd road output stream be multiplied with 32, from first row, inactive bit is filled with in the first row of the first matrix, the quantity of inactive bit is the long-pending of the first matrix column number and line number, deduct the bit number difference of the 3rd road output stream, the data that other position that first matrix does not fill inactive bit is deposited are from the first row to last column, often row arranges from first row to last, be followed successively by the data by exporting in tactic 3rd road output stream,
According to
directly carrying out interleaving treatment to the first matrix obtains the second matrix, and wherein, π (k) represents the sequence number of data in the first matrix, and k represents the sequence number of data in the second matrix, and P represents permutation function,
represent the line number at the first matrix,
represent at the first matrix column number,
permutation function P represents as table
<0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23, in 15,31> 0 represents that the first matrix the 1st arranges, and 16 represent that the first matrix the 17th arranges, 31 represent that the first matrix the 32nd arranges
in P (0) represent the second matrix first row, P (1) represents the second matrix secondary series,
represent last row of the second matrix.
5. device as claimed in claim 4, is characterized in that, sub-block interleaving block, also for directly being existed in random access memory ram by the second matrix.
6. device as claimed in claim 4, it is characterized in that, sub-block interleaving block, also obtain the 3rd matrix for carrying out shifting function to the second matrix, and the 3rd matrix is existed in random access memory ram, second matrix column number is 32, the data of last column of the 3rd matrix are by after rear 31 bit data in second matrix last column, the data of splicing the second matrix the first row first row are formed, the data of other row of the 3rd matrix are by after rear 31 bit data in the row that the second matrix line number is identical, the data of splicing the second matrix next line first row are formed.
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