CN101090305A - Radio physical layer channel code chain processing method - Google Patents
Radio physical layer channel code chain processing method Download PDFInfo
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- CN101090305A CN101090305A CN 200710141526 CN200710141526A CN101090305A CN 101090305 A CN101090305 A CN 101090305A CN 200710141526 CN200710141526 CN 200710141526 CN 200710141526 A CN200710141526 A CN 200710141526A CN 101090305 A CN101090305 A CN 101090305A
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Abstract
This invention relates to a channel coding link process method of wireless physical layer including: carrying out Turbo coding to information block bit data, carrying out rate match to the Turbo coded code bit based on circulation buffer storage, and bit priority mapping modulation to the system bit stream and verified bit stream.
Description
Technical field
The present invention relates to radio communication, be specifically related to a kind of radio physical layer channel code chain processing method.
Background technology
In wireless communication system, channel code chain is the bottom technology of physical layer, has determined wireless communication system bottom transmission performance and transmission reliability.In up-to-date 3GPP LTE research on standard, channel code chain has adopted a series of up-to-date technology, has improved the physical layer transmission performance when simplifying implementation complexity.Wherein: in up-to-date 3GPP standard agreement, adopted 1. and replaced the channel coding schemes of the Turbo code of Quadratic Polynomial Permutation (being called for short QPP) interleaver as data service based on quadratic polynomial; Adopt 2. based on the speed matching method of circular buffer (Circular Buffer) realize sending data length and distribute the size of physical channel resources to be complementary.Simultaneously, in order to obtain the higher availability of frequency spectrum and hardware circuit solution, adopted 3. high-order modulating such as 16QAM, 64QAM.
In addition; the bit priority mapping can be used as a kind of enhancement techniques that adopts under high-order modulating; by highly reliable constellation point bit in the back systematic bits employing high order modulation of encoding is modulated mapping; thereby make systematic bits obtain stronger protection; improve decoding performance; and then the throughput performance of raising Radio Link, reduce propagation delay time.And do not adopt the channel code chain processing method of above-mentioned four kinds of technology simultaneously or do not adopt the channel code chain processing method of above-mentioned four kinds of technology to be disclosed simultaneously at present.
Summary of the invention
The technical issues that need to address of the present invention provide a kind of radio physical layer channel code chain processing method, make systematic bits obtain stronger protection than prior art, improve decoding performance, and then improve the throughput performance of Radio Link, reduce propagation delay time.
Above-mentioned technical problem of the present invention solves like this, and a kind of radio physical layer channel code chain processing method is provided, and may further comprise the steps:
1.1) block of information Bit data I is carried out the Turbo coding;
1.2) the code word bits C behind the Turbo coding is carried out rate-matched based on circular buffer;
1.3) systematic bits stream S, the check bit stream P that exports after the rate-matched carried out bit priority mapping modulation.
According to processing method provided by the invention, described step 1.1) the Turbo coding in is based on the Turbo coding of QPP interleaver, described step 1.1) comprises necessary filling substep, that is: judge at first before coding whether described block of information Bit data size satisfies QPP interleaver Bit data size requirements, if do not satisfy, then before described block of information Bit data, filling " filling " bit of some, otherwise, need before described block of information Bit data, not fill.
According to processing method provided by the invention, described " filling " bit can be " 0 ".
According to processing method provided by the invention, described step 1.1) also comprise:
3.1) to the coding that the block of information Bit data X after necessity filling processing carries out Turbo code first constituent encoder, export first check bit stream Z;
3.2) block of information Bit data X after necessity fill handled carries out the interleaving treatment based on the QPP interleaver;
3.3) the block of information X ' Bit data of exporting after the interleaving treatment is carried out the coding of Turbo code second constituent encoder, export second check bit stream Z ';
3.4) the tail bit sequence that produces of output described Turbo code first constituent encoder and second constituent encoder;
3.5) the block of information Bit data X after the above-mentioned processing, first check bit stream Z, second check bit stream Z ' and tail bit sequence are carried out multiplexing, form the Turbo coding back code word bits stream that interweaves based on QPP.
According to processing method provided by the invention, described step 1.2) two kinds of processing methods (that is: two kinds of speed matching algorithms) can be arranged, wherein:
(1) processing method one comprises:
4.1) the code word bits stream C of Turbo coding output is carried out bit separation output system bit stream S, first check bit stream P
1With second check bit stream P
2
4.2) systematic bits stream S, first check bit that separates output flowed P
1With second check bit stream P
2Carrying out sub-block interleaving respectively handles;
4.3) systematic bits stream S after sub-block interleaving is handled
I, the sub-block interleaving check bit stream P1 after handling
I, the sub-block interleaving check bit stream P2 after handling
ICarry out bit collection and handle, form virtual circular buffer CB output.
4.4) according to redundancy versions value and transmission HARQ length of data package transmission packet bit definite and that starting position circulation reading rate coupling is exported from virtual circular buffer, judge according to specifically reading the position, if systematic bits, then order is write in the rate-matched output system bit stream, otherwise order is write in the rate-matched output verification bit stream.
(2) processing method two (that is: bit is selected speed matching algorithm) comprising:
5.1) the code word bits stream of Turbo coding output is carried out bit separation output system bit stream, first check bit stream and second check bit stream.
5.2) the transmission HARQ packet bit definite with transmission HARQ length of data package and selection reading rate coupling output from systematic bits stream, first check bit stream and second check bit that separates output flows according to the redundancy versions value, judge according to specifically reading the position, if systematic bits, then order is write in the rate-matched output system bit stream, otherwise order is write in the rate-matched output verification bit stream.
According to processing method provided by the invention, above-mentioned processing method two (that is: bit is selected speed matching algorithm) specifically comprises:
6.1) code word bits behind the Turbo coding is carried out systematic bits stream, first check bit stream and second check bit stream that bit separation output length is L;
6.2) the systematic bits stream, first check bit stream and second check bit stream that calculate to separate needs virtual interpolations D=32*ceil (L/32)-L individual " dummy bit " on every circuit-switched data bit stream; Described " dummy bit " is unactual to be added on every circuit-switched data bit stream, just because the circulating buffer memory rate matching algorithm needs the influence after " dummy bit " added in consideration in the rate-matched process.
6.3) systematic bits stream, first check bit stream and second check bit that adds " dummy bit " flow to scanning frequency rate matching treatment, from above-mentioned three bit streams, carry out bit and select, generate the systematic bits stream and the check bit stream of the corresponding HARQ of transmission packet.If filling bit is arranged, go filling bit to handle to the systematic bits stream and the first check bit stream that separates.
According to processing method provided by the invention, described step 6.3) comprising:
7.1) be provided with and read total bit counter n=0, read-out system bit counter n
Sys=0, reader check bit counter n
Par=0;
7.2) according to the circulating buffer memory rate matching algorithm, judge whether n+1 bit of current output is systematic bits, if the output bit is a systematic bits, then determine and read non-" filling " bit, again this bit is write output system bit stream n according to the address A of current selection bit in the systematic bits stream of input by corresponding formula
SysThe bit position is gone, and reads total bit counter n and systematic bits counter n simultaneously
SysAdd 1 respectively; Judge whether bit calculator n reaches and read the requirement of HARQ bag total number of bits, if speed matching algorithm finishes, otherwise, continue speed matching algorithm;
7.3) according to the circulating buffer memory rate matching algorithm, judge whether n+1 bit of current output is check bit, if the output bit is a check bit, alternately from flowing, first check bit stream of input and second check bit read, and by corresponding formula determine and according to current selection bit at " filling " bit that first check bit stream or the address B in second check bit stream of input read non-second check bit stream, again this bit is write output verification bit stream n
ParThe bit position is gone, and reads total bit counter n and check bit counter n simultaneously
ParAdd 1 respectively; Judge whether read total bit counter n reaches and read the requirement of HARQ bag total number of bits, if speed matching algorithm finishes, otherwise, continue speed matching algorithm.
According to processing method provided by the invention, select in the speed matching algorithm at bit, when " dummy bit " virtual systematic bits stream, first check bit stream and second check bit that is placed on separation flows the front described step 6.2), described step 7.2) the address A in the systematic bits stream of input is expressed as A=ColPerm (c)-D, described step 7.3) in address B in input first check bit stream or second check bit stream be expressed as B=ColPerm (c/2-16)-D; Wherein: ColPerm is the column permutation vector of the sub-block interleaving of rate-matched, and c is that D i.e. " dummy bit " number capable number.
According to processing method provided by the invention, select in the speed matching algorithm at bit, when " dummy bit " virtual systematic bits stream, first check bit stream and second check bit that is placed on separation flows the back described step 6.2), described step 7.2) the address A in the systematic bits stream of input is expressed as A=ColPerm (c), described step 7.3) in be expressed as B=ColPerm (c/2-16) at first check bit stream of input or the address B in second check bit stream; Wherein: ColPerm is the column permutation vector of the sub-block interleaving of rate-matched, and c is capable number.
According to processing method provided by the invention, described step 1.3) specifically: to systematic bits stream and the check bit stream of exporting after the rate-matched, under high-order modulating, utilize high reliability bit in the planisphere to come data in the transmitting system bit stream, realize the bit priority mapping.Can adopt 1. bit collection deinterleaving method or 2. Bit Interleave method realization during specific implementation, all should comprise as long as satisfy the implementation method that as far as possible systematic bits is sent on high reliability constellation point bit.
Particularly, 1. the bit collection deinterleaving method is as follows:
If rate-matched output system bit stream and check bit stream length are respectively Ls and Lp, the planisphere order of modulation of employing is M, and then the bit collection interleaver is the rectangular interweaving device of the capable K=of M (Ls+Lp)/M row.
The wiring method that the rectangular interweaving device adopts is as follows:
Method 1: systematic bits begins from the position, the upper left corner of rectangular interweaving device from left to right to write by row, write delegation after, if systematic bits has not been write, continue to begin from left to right to write by capable from descending leftmost position.Check bit begins from the position, the lower right corner of rectangular interweaving device to write from right to left by row, write delegation after, if check bit has not also been write, continue to begin to write from right to left by row from the lastrow farthest right position.
Method 2: systematic bits begins from the position, the upper left corner of rectangular interweaving device from left to right to write by row, write delegation after, if systematic bits has not also been write, continue to begin from left to right to write by capable from the next line leftmost position.After systematic bits had been write, check bit continued from left to right to write by row after the systematic bits that writes at last, write delegation after, if check bit do not write, continue to begin from left to right to write by capable from the next line leftmost position.
Method 3: adopt the system/check bit wiring method of bit collection (bit collection) in the HSDPA rate-matched, unique difference is owing to have only a check bit stream among the present invention, does not need interlocking between two check bit streams.
The employing of reading of bit collection interleaver is from left to right read by row, and the data in every row are read in accordance with the order from top to bottom.
Particularly, 2. the Bit Interleave method is finished and bit collection method identical functions, just realizes directly that by the different interleave methods of system, check bit stream above-mentioned three kinds of bit collection methods all can simply be derived interleave method.
For rectangular interweaving wiring method 1, its corresponding Bit Interleave method is as follows:
Systematic bits is according to OPADD index 0, M, 2M, 3M...... directly write the output buffering, corresponding to first row of rectangular interweaving device, if after writing out K systematic bits, systematic bits has not been write, then systematic bits is according to OPADD index 1, M+1,2M+1,3M+1, ... continue to write the output buffering, corresponding to second row of interleaver, and the like.For check bit according to OPADD index KM-1, (K-1) M-1, (K-2) M-1 ... directly write the output buffering, last column corresponding to interleaver, if after writing out K check bit, check bit has not been write, then check bit is according to OPADD index KM-2, (K-1) M-2, (K-2) M-2...... continues to write the output buffering, corresponding to the second last row of interleaver, and the like.
According to processing method provided by the invention, in the bit data flow that bit collection interweaves or Bit Interleave is exported, divide into groups with M successive bits, order is mapped in the planisphere, wherein the bit of front has high reliability with respect to the bit of back in M bit, sends on the high reliability bit in planisphere.
According to processing method provided by the invention, it is 8PSK, 16QAM, 64QAM or 256QAM that described high-order modulating includes, but are not limited to.
According to processing method provided by the invention, this method can be used in the digital radio communication system of various standards.
A kind of radio physical layer channel code chain processing method provided by the invention; employing meets the bit priority mapping techniques of technology trends; by highly reliable constellation point bit in the back systematic bits employing high order modulation of encoding is modulated mapping; thereby more can make systematic bits obtain stronger protection than prior art; improve decoding performance; and then the throughput performance of raising Radio Link, reduce propagation delay time.
Description of drawings
Further the present invention is described in detail below in conjunction with the drawings and specific embodiments.
Fig. 1 is channel code chain processing method one a flow process schematic diagram of the present invention;
Fig. 2 is method one a corresponding circulating buffer memory rate coupling schematic diagram shown in Figure 1;
Fig. 3 is channel code chain processing method two flow process schematic diagrames of the present invention;
Fig. 4 is the Turbo coding structure schematic diagram that method two correspondence shown in Figure 2 interweaves based on QPP;
Fig. 5 is the corresponding circulating buffer memory rate coupling of a method two shown in Figure 2 schematic diagram;
Fig. 6 is that " dummy bit " is added on the anterior system/check bit selection algorithm flow chart of son stream in the bit selection speed matching algorithm shown in Figure 5;
Fig. 7 is system/check bit selection algorithm flow chart that " dummy bit " is added on son stream rear portion in the bit selection speed matching algorithm shown in Figure 5.
Embodiment
At first, handle operation principle explanation the present invention of two kinds of specific embodiments in conjunction with radio physical layer channel code chain of the present invention:
(1) method one:
According to a kind of channel code chain processing method of the present invention, as shown in Figure 1, may further comprise the steps:
102) the block of information Bit data is carried out the Turbo coding;
104) code word bits behind the Turbo coding is carried out handling based on the rate-matched of circular buffer output system bit stream and check bit stream two parts; In the rate-matched processing procedure, the bit that reads is judged if reading bit is systematic bits, then order is write rate-matched output system bit stream part from circular buffer, otherwise order is write rate-matched output verification bit stream part;
106) systematic bits stream, the check bit stream of exporting based on the rate-matched of circular buffer is carried out bit priority mapping modulation.
Wherein, step 104) rate-matched based on circular buffer in is handled, and as shown in Figure 2, specifically comprises following five sub-steps:
(1) the code word bits stream to the output of Turbo coding carries out the bit separation operation, separates output system bit stream, first check bit stream and second check bit stream totally three circuit-switched data bit streams.
(2) systematic bits stream, first check bit stream and the second check bit flow point that separates output do not carry out sub-block interleaving processing.The sub-block interleaving of second check bit stream has a side-play amount with respect to the sub-block interleaving that first check bit flows, systematic bits flows.
(3) first check bit stream behind the systematic bits stream after sub-block interleaving is handled, the sub-block interleaving and the second check bit stream behind the sub-block interleaving carry out bit collection to be handled, and constitutes virtual circular buffer output.
(4) certain bit position from export virtual circular buffer begins to select reading rate to mate the transmission packet bit of output according to redundancy versions value and transmission length of data package.The data bit that rate-matched is read is judged simultaneously, if systematic bits, then order is write in the rate-matched output system bit stream, otherwise order is write in the rate-matched output verification bit stream.
(2) method two:
According to a kind of channel code chain processing method of the present invention, as shown in Figure 3, may further comprise the steps:
302) the block of information Bit data being carried out " filling " (padding) operates;
304) the block of information Bit data after " filling " operation is carried out encoding based on the Turbo of QPP interleaver;
306) to carry out handling systematic bits stream after the output speed matching treatment and check bit stream based on the code word bits behind the Turbo coding of QPP interleaver based on the rate-matched of circular buffer;
308) to carrying out bit priority mapping modulation based on systematic bits stream of exporting after the circulating buffer memory rate matching treatment and check bit stream.
Wherein,
Step 302) in, " filling " operation at first judges according to block of information Bit data size whether satisfy QPP interleaver requirement in the Turbo coding, if do not satisfy, before the block of information Bit data, fill " filling " bit of some, 0 bit for example, if satisfy, then 0 bit is filled in " filling " operation.
In the step 304, the Turbo coding based on the QPP interleaver as shown in Figure 4, comprises following substep:
(1) the block of information Bit data after " filling " operation is carried out the coding of Turbo code first constituent encoder, export first check bit stream;
(2) the block of information Bit data after " filling " operation is carried out interleaving treatment based on the QPP interleaver;
(3) interweave " fillings " block of information Bit data of back output of QPP is carried out the coding of Turbo code second constituent encoder, export second check bit and flow;
(4) the tail bit sequence of output Turbo code first constituent encoder and second constituent encoder generation.
(5) block of information Bit data, first check bit stream after " filling " operation, second check bit stream and tail bit sequence are carried out multiplexing, form the Turbo coding back code word bits stream that interweaves based on QPP.
Step 306), handle, as shown in Figure 5, comprise following substep based on the rate-matched of circular buffer:
(1) code word bits behind the Turbo coding is carried out the bit separation operation, separate output system bit stream, first check bit stream and second check bit stream totally three circuit-switched data bit streams, the length of three road bit data flows is L.
(2) calculate the systematic bits stream, first check bit stream and second check bit that separate and flow " dummy bit " number D=32*ceil (the L/32)-L that in the circulating buffer memory rate matching algorithm, need on every circuit-switched data bit stream, add.Particularly, " dummy bit " can be added on the front of every circuit-switched data bit stream in circulating buffer memory rate matched sub-block interleaving process, also can be added on the back of every circuit-switched data bit stream.Wherein, so-called interpolation dummy bit is not meant a real interpolation D data bit, is virtually in the follow-up step to have added D data bit here, and promptly this step is not the operation of necessary being.
(3) carry out rate-matched, go filling bit to handle, generate systematic bits stream and check bit stream two parts of certain HARQ bag, wherein, only go " filling bit " to operate to the systematic bits stream and the first check bit stream.Substep (3) is handled and is specifically comprised following three sub-steps again:
(3a) total bit counter n=0, read-out system bit counter n are read in setting
Sys=0, reader check bit counter n
Par=0.
(3b) according to given circulating buffer memory rate matching algorithm, judge whether n+1 bit of current output is systematic bits, if the output bit is a systematic bits, then determine the address A of current selection bit in the systematic bits stream of input according to specific computing formula, read this systematic bits according to address A, again this bit is write output system bit stream n
SysThe bit position is gone, and reads total bit counter n and systematic bits counter n simultaneously
SysAdd 1 respectively.Judge whether bit calculator n reaches and read the requirement of HARQ bag total number of bits, if speed matching algorithm finishes, otherwise, continue speed matching algorithm.Wherein, if current address A indication is " dummy bit " that adds in " filling bit " or the sub-block interleaving of rate-matched, then do not carry out described read-write operation, n and n
SysConstant.
(3c) according to given circulating buffer memory rate matching algorithm, judge whether n+1 bit of current output is check bit, if the output bit is a check bit, need alternately from first check bit stream of importing and second check bit stream of importing, to read a check bit, more specifically be, determine that according to the computing formula of rate-matched current selection bit is at first check bit stream of input or the address B in second check bit stream, read described check bit according to address B, again this bit is write output verification bit stream n
ParThe bit position is gone, and reads total bit counter n and check bit counter n simultaneously
ParAdd 1 respectively.Judge whether read total bit counter n reaches and read the requirement of HARQ bag total number of bits, if speed matching algorithm finishes, otherwise, continue speed matching algorithm.Wherein, if current address B indication is " dummy bit " that adds in " filling bit " or the sub-block interleaving of rate-matched in first check bit stream, then do not carry out described read-write operation, n and n
ParConstant.
Step 308), to step 306) the systematic bits stream and the check bit stream that generate, under 16QAM, 64QAM or 256QAM modulation system, utilize high reliability bit in the planisphere to come data in the transmitting system bit stream, realize that the bit priority mapping modulates.
Secondly, handle specific embodiment detailed description the present invention of two kinds of schemes in conjunction with radio physical layer channel code chain of the present invention:
(1) embodiment one
Suppose block of information Bit data sequence I (i
0, i
1..., i
K-1), wherein K is a block of information Bit data length, i
k(0≤k≤K-1) is the binary bits data.
Block of information Bit data I exports Turbo coding codeword bit stream sequence C (c through the Turbo coding
0, c
1... c
3 * S-1).
Turbo coding output code word bit stream sequence C is carried out the bit separation operation, isolate systematic bits stream sequence S (s
0, s
1... s
S-1), first check bit stream sequence P
1(p
0 1, p
1 1... p
S-1 1) and second check bit stream sequence P
2(p
0 2, p
1 2... p
S-1 2).
Isolated systematic bits stream sequence S, first check bit stream sequence P
1With second check bit stream sequence P
2Carry out sub-block interleaving respectively, the systematic bits stream sequence S behind the sub-block interleaving
I(s
0 I, s
1 I..., s
S-1 I), first check bit stream sequence P1 behind the sub-block interleaving
I(p1
0 I, p1
1 I..., p1
S-1 I), second check bit stream sequence P2 behind the sub-block interleaving
I(p2
0 I, p2
1 I..., p2
S-1 I).If π
Sys, π
P1And π
P2The sub-block interleaving processing function of representing isolated systematic bits stream, first check bit stream and second check bit stream respectively, δ is the sub-block interleaving skew of second check bit stream sequence with respect to first check bit stream sequence, and then systematic bits flows that sub-block interleaving flows sub-block interleaving with first check bit respectively, second check bit flows sub-block interleaving following relation:
π
p2(i)＝(π
sys(i)+δ)％S (0≤i≤S-1)
π
p1(i)＝π
sys(i) (0≤i≤S-1)
Systematic bits stream S after sub-block interleaving is handled
I, first check bit stream sequence P1 after sub-block interleaving is handled
IWith second check bit stream sequence P2
ICarry out bit collection and handle, form virtual circular buffer CB (cb
0, cb
1..., cb
3 * S-1), concrete bit collection is handled as follows:
cb
k＝s
k′ k＝0，1，…S-1
cb
S+2×k＝p1
k′ k＝0，1，…S-1
cb
S+2×k+1＝p2
k′ k＝0，1，…S-1
(0≤j≤3 * S-1), start position j begins circulation and reads size and be N from virtual circular buffer to determine to send the start position j that the HARQ packet reads according to redundancy versions value and virtual circular buffer size in virtual circular buffer
DataThe Bit data of transmission HARQ bag.Specifically in virtual circular buffer, read when sending packet data, judge reading the position k of Bit data in virtual circular buffer, when 0≤k≤S-1, the Bit data that reads is a systematic bits, and the Bit data that reads is write in the output system bit stream in proper order; When S≤k≤3 * S-1, the Bit data that reads is a check bit, and the Bit data of reading is write in the output verification bit stream in proper order.
The systematic bits stream of rate-matched output and check bit stream under 16QAM, 64QAM or 256QAM modulation system, utilize high reliability bit in the planisphere to come data in the transfer system bit stream, realize that the bit priority mapping modulates.
(2) embodiment two
If block of information Bit data vector I is (i
1, i
2..., i
K), wherein K is a block of information Bit data length, i
k(1≤k≤K) is the binary bits data.
Because the QPP in the Turbo encoder interweaves and does not support interweaving of continuous length block of information, therefore when block of information Bit data length does not satisfy the requirement of QPP weaving length, need before the block of information Bit data, carry out " filling " and (padding) operate, insert " 0 " bit.Block of information Bit data vector X (x after " filling "
1, x
2..., x
S), wherein S is " filling " back block of information Bit data length.Bit (x among the block of information Bit data vector X of " filling " back
1, x
2... x
S-K) be " 0 " Bit data of " filling ".
Block of information Bit data X input after " filling " is encoded based on the Turbo encoder that QPP interweaves, be divided into following five sub-steps: the block of information Bit data X after (1) " filling " imports first constituent encoder and encodes, and exports the first check bit flow vector Z (z
1, z
2... z
S); (2) input of the block of information Bit data X after " filling " QPP interleaver interweaves, " filling " block of information Bit data X ' (x after output QPP interweaves
1', x
2' ... x
S').(3) " filling " block of information Bit data X ' input second constituent encoder after QPP interweaves is encoded, and exports the second check bit flow vector Z ' (z
1', z
2' ... z
S').(4) the tail bit of output first constituent encoder and second constituent encoder generation, the tail bit sequence is: x
S+1, z
S+1, x
S+2, z
S+2, x
S+3, z
S+3, x
S+1', z
S+1', x
S+2', z
S+2', x
S+3', z
S+3'.(5) the block of information Bit data X after " filling ", first check bit stream sequence Z, second check bit stream sequence Z ' and tail bit sequence are carried out multiplexing, form the Turbo coding back code word bits stream sequence that interweaves based on QPP, concrete sequence is:
x
1, z
1, z
1', x
2, z
2, z
2' ..., x
S, z
S, z
S', x
S+1, z
S+1, x
S+2, z
S+2, x
S+3, z
S+3, x
S+1', z
S+1', x
S+2', z
S+2', x
S+3', z
S+3' code word bits stream sequence length is 3 * S+12.
The code word bits stream sequence input of the Turbo coding output that interweaves based on QPP is handled based on the rate-matched module of circular buffer, handles mainly to comprise following substep:
(1) code word bits to the input of rate-matched module flows sequence C (c
1, c
2... c
3 * S+12) carry out the bit separation operation, isolate systematic bits stream sequence S (s
1, s
2... s
S+4), first check bit stream sequence P
1(p
1 1, p
2 1... p
S+4 1) and second check bit stream sequence P
2(p
1 2, p
2 2... p
S+4 2), every road bitstream length is S+4.Enter code word bit stream sequence C and systematic bits stream sequence S, first check bit stream sequence P
1With second check bit stream sequence P
2Following relation is arranged:
s
k＝c
3×(k-1)+1 k＝1，2，…S+4
(2) to systematic bits stream sequence S, first check bit stream sequence P
1With second check bit stream sequence P
2Carry out rate-matched and handle, in rate-matched output, remove systematic bits stream S and first check bit stream P
1In " filling " bit and rate-matched in imagination " dummy bit " that add handle, systematic bits stream and the check bit of exporting certain HARQ bag flow two parts.Step (2) specifically comprises following two sub-steps (2a) (2b1) or (2a) (2b2) again
(1) flow sequence S, when first check bit flows sequence P1 and second check bit stream sequence P2 front, carry out substep (2a) (2b1) when designer's consideration is added on systematic bits with " dummy bit " in speed matching algorithm, algorithm flow as shown in Figure 6;
(2) when the designer considers in speed matching algorithm " dummy bit " to be added on systematic bits stream sequence S, first check bit flows sequence P1 and second check bit stream sequence P
2During the back, carry out substep (2a) (2b2), algorithm flow as shown in Figure 7.
(2a) total bit counter n=0, read-out system bit counter n are read in setting
Sys=0, reader check bit counter n
Par=0, be used for respectively rate-matched being exported total bit number, systematic bits number and check bit number and count.Imagination filling " dummy bit " number is D=32*ceil ((S+4)/32)-(S+4) in the sub-block interleaving process of rate-matched.Virtual circular buffer reads that initial row c=σ+RV * (96/nRV), wherein σ is the initial line displacement of reading, and RV is the redundancy versions value, and nRV is the redundancy versions number.Sending HARQ bag bit number is N
Data
(2b1) when reading total bit counter n value less than N
DataThe time, (II) rate adaptation operating of (III) of substep (I) is carried out in circulation.
(I) row c carries out modulo operation to the total columns 96 of virtual circular buffer.
(II) when satisfied row c less than 32 the time, according to the circulating buffer memory rate matching algorithm, current output bit is a systematic bits, 1. 2. 3. operation of substep is carried out in circulation.
1. calculate the bit position A of current selective system bit in input system bit stream sequence S, A=ColPerm (c)-D.Wherein ColPerm is the column permutation vector of the sub-block interleaving of rate-matched, ColPerm=[0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23,15,31].
2. ought satisfy address A less than S+4, circulation is carried out (i) and is (ii) operated: (i) as address A during more than or equal to S-K, and systematic bits S among the read-out system bit stream sequence S
A+1, again this bit is write output system bit stream n
SysThe bit position is gone, total bit counter n and systematic bits counter n
SysAdd 1 respectively.Judge whether n equals N
Data, if equate, then speed matching algorithm finishes, otherwise, continue to carry out speed matching algorithm.(ii) address A adds sub-block interleaving columns 32.
3. row c adds 1.
(III) when row c more than or equal to 32 the time, according to the circulating buffer memory rate matching algorithm, current output bit is a check bit, 1. 2. 3. operation of substep is carried out in circulation.
1. calculate current selection check bit at input first check bit stream sequence P
1In bit position B (with " B " replacement " A " be for the technical scheme self-consistentency, and avoid confusion, below the same), B=ColPerm (c/2-16)-D.
2. satisfy less than S+4 as address B, (i) (ii) (iii) (iv) (v) operation: (i) as address B during more than or equal to S-K, read first check bit stream sequence P is carried out in circulation
1Middle check bit p
B+1 1, again this bit is write output verification bit stream n
ParThe bit position is gone, and reads total bit counter n and reader check bit counter n
ParAdd 1 respectively.Judge whether n equals N
Data, if equate, then speed matching algorithm finishes, otherwise, continue to carry out speed matching algorithm.(ii) calculate current selection check bit at input second check bit stream sequence P
2In bit position B2, B2=B+ δ, wherein δ is the sub-block interleaving skew of second check bit stream sequence with respect to first check bit stream sequence.(iii) as B2 during more than or equal to S+4, B2 deducts S+4+D.(iv) when B2 more than or equal to 0 the time, read second check bit stream sequence P
2Middle check bit p
B2+1 2, again this bit is write output verification bit stream n
ParThe bit position is gone, and reads total bit counter n and reader check bit counter n
ParAdd 1 respectively.Judge whether n equals N
Data, if equate, then speed matching algorithm finishes, otherwise, continue to carry out speed matching algorithm.(v) address B adds sub-block interleaving columns 32.
3. row c adds 2.
(2 b2) is when reading total bit counter n value less than N
DataThe time, (II) rate adaptation operating of (III) of substep (I) is carried out in circulation.
(I) row c carries out modulo operation to the total columns 96 of virtual circular buffer.
(II) when row c less than 32 the time, according to the circulating buffer memory rate matching algorithm, current output bit is a systematic bits, 1. 2. 3. 4. operation of substep is carried out in circulation.
1. calculate the bit position A of current selective system bit in input system bit stream sequence S, A=ColPerm (c).Wherein ColPerm is the column permutation vector of the sub-block interleaving of rate-matched, ColPerm=[0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23,15,31].
2. when satisfying address A less than S-K, A circulation in address adds sub-block interleaving columns 32.
3. as address A during less than S+4, circulation is carried out (i) and is (ii) operated: (i) systematic bits S among the read-out system bit stream sequence S
A+1, again this bit is write output system bit stream n
SysThe bit position is gone, and reads total bit counter n and read-out system bit counter n
SysAdd 1 respectively.Judge whether n equals N
Data, if equate, then speed matching algorithm finishes, otherwise, continue to carry out speed matching algorithm.(ii) address A adds sub-block interleaving columns 32.
4. row c adds 1.
(III) when row c more than or equal to 32 the time, according to the circulating buffer memory rate matching algorithm, current output bit is a check bit, 1. 2. 3. 4. operation of substep is carried out in circulation.
1. calculate current selection check bit at input first check bit stream sequence P
1In bit position B, B=ColPerm (c/2-16).
2. as address B during less than S-K, circulation is carried out (i) and (ii) operate: read second check bit and flow sequence P
2Middle check bit p
B+ δ+1 2, again this bit is write output verification bit stream n
ParThe bit position is gone, and reads total bit counter n and reader check bit counter n
ParAdd 1 respectively.Judge whether n equals N
Data, if equate, then speed matching algorithm finishes, otherwise, continue to carry out speed matching algorithm.(ii) address B adds sub-block interleaving columns 32.
3. work as address B less than S+4, (i) (ii) (iii) operation is carried out in circulation: (i) read first check bit stream sequence P
1Middle check bit p
B+1 1, again this bit is write output verification bit stream n
ParThe bit position is gone, and reads total bit counter n and reader check bit counter n
ParAdd 1 respectively.Judge whether n equals N
Data, if equate, speed matching algorithm 2b then) finish, otherwise, continue to carry out speed matching algorithm 2b).(ii) read second check bit stream sequence P
2Middle check bit p
Mod (B+ δ, S+4)+1 2, again this bit is write output verification bit stream n
ParThe bit position is gone, and reads total bit counter n and reader check bit counter n
ParAdd 1 respectively.Judge whether n equals N
Data, if equate, then speed matching algorithm finishes, otherwise, continue to carry out speed matching algorithm.(iii) address B adds sub-block interleaving columns 32.
4. row c adds 2.
Based on the systematic bits stream and the check bit stream of the rate-matched of circular buffer output, under 16QAM, 64QAM or 256QAM modulation system, utilize high reliability bit in the planisphere to come data in the transfer system bit stream, realize that the bit priority mapping modulates.
Claims (11)
1, a kind of radio physical layer channel code chain processing method is characterized in that, may further comprise the steps:
1.1) the block of information Bit data is carried out the Turbo coding;
1.2) code word bits behind the Turbo coding is carried out rate-matched based on circular buffer;
1.3) systematic bits stream, the check bit stream of exporting after the rate-matched is carried out bit priority mapping modulation.
2, according to the described processing method of claim 1, it is characterized in that, described step 1.1) the Turbo coding in is based on the Turbo coding of QPP interleaver, described step 1.1) comprises necessary filling: judge at first before coding whether described block of information Bit data size satisfies QPP interleaver Bit data size requirements, if do not satisfy, then before described block of information Bit data, filling " filling " bit of some, otherwise, need before described block of information Bit data, not fill.
3, according to the described processing method of claim 2, it is characterized in that described step 1.1) also comprise:
3.1) described necessary block of information Bit data of filling after handling is carried out the coding of Turbo code first constituent encoder, export first check bit stream;
3.2) described necessary block of information Bit data of filling after handling is carried out interleaving treatment based on the QPP interleaver;
3.3) the block of information Bit data of exporting after the interleaving treatment is carried out the coding of Turbo code second constituent encoder, export second check bit stream;
3.4) the tail bit sequence that produces of output described Turbo code first constituent encoder and second constituent encoder;
3.5) carry out the described necessary block of information Bit data after handling, described first check bit stream, second check bit stream and the tail bit sequence of filling multiplexing, form the Turbo coding back code word bits stream that interweaves based on QPP.
4, according to the described processing method of claim 1, it is characterized in that described step 1.2) comprising:
4.1) to the code word bits stream of Turbo coding output carry out bit separation output system bit stream,
First check bit stream and second check bit stream;
4.2) systematic bits stream, first check bit stream and the second check bit flow point that separates output do not carried out sub-block interleaving processing;
4.3) systematic bits stream, first check bit stream and the second check bit stream after sub-block interleaving is handled carries out bit collection and handle, and forms virtual circular buffer output;
4.4) according to redundancy versions value and transmission HARQ length of data package transmission packet bit definite and that starting position circulation reading rate coupling is exported from virtual circular buffer, judge according to specifically reading the position, if systematic bits, then write rate-matched in proper order and go out in the systematic bits stream, otherwise order is write in the rate-matched output verification bit stream.
5, according to the described processing method of claim 1, it is characterized in that described step 1.2) comprising: 5.1) to the code word bits stream of Turbo coding output carry out bit separation output system bit stream,
First check bit stream and second check bit stream;
5.2) the transmission HARQ packet bit definite with transmission HARQ length of data package and selection reading rate coupling output from systematic bits stream, first check bit stream and second check bit that separates output flows according to the redundancy versions value, judge according to specifically reading the position, if systematic bits, then order is write in the rate-matched output system bit stream, otherwise order is write in the rate-matched output verification bit stream.
6, according to the described processing method of claim 5, it is characterized in that described step 1.2) comprising:
6.1) code word bits behind the Turbo coding is carried out bit separation, output length is systematic bits stream, first check bit stream and second check bit stream of L;
6.2) systematic bits stream, first check bit stream and second check bit stream virtual interpolations D=32*ceil (L/32)-L individual " dummy bit " on every circuit-switched data bit stream of calculate separating;
6.3) systematic bits stream, first check bit stream and second check bit that adds " dummy bit " flow to scanning frequency rate matching treatment and therefrom carry out the bit selection, generate the systematic bits stream and the check bit stream of the corresponding HARQ of transmission packet, if filling bit is arranged, go filling bit to handle to the systematic bits stream and the first check bit stream that separates.
7, according to the described processing method of claim 6, it is characterized in that described step 6.3) comprising:
7.1) be provided with and read total bit counter n=0, read-out system bit counter n
Sys=0, reader check bit counter n
Par=0;
7.2) according to the circulating buffer memory rate matching algorithm, judge whether n+1 bit of current output is systematic bits, if the output bit is a systematic bits, then determine and read non-" filling " bit, again this bit is write output system bit stream n according to the address A of current selection bit in the systematic bits stream of input by corresponding formula
SysThe bit position is gone, and reads total bit counter n and systematic bits counter n simultaneously
SysAdd 1 respectively; Judge whether bit counter n reaches the requirement of current generation HARQ packet total number of bits, if speed matching algorithm finishes, otherwise, continue speed matching algorithm;
7.3) according to the circulating buffer memory rate matching algorithm, judge whether n+1 bit of current output is check bit, if the output bit is a check bit, alternately from flowing, first check bit stream that separates and second check bit read, and determine and read filling bit in non-second check bit stream according to current selection bit at first check bit stream or the address B in second check bit stream of input by corresponding formula, again this bit is write output verification bit stream n
ParThe bit position is gone, and reads total bit counter n and check bit counter n simultaneously
ParAdd 1 respectively; Judge whether read total bit counter n reaches the requirement of current generation HARQ packet total number of bits, if speed matching algorithm finishes, otherwise, continue speed matching algorithm.
8, according to the described processing method of claim 6, it is characterized in that, when " dummy bit " virtual systematic bits stream, first check bit stream and second check bit that is placed on separation flows the front described step 6.2), described step 7.2) the address A in the systematic bits stream of input is expressed as A=ColPerm (c)-D, described step 7.3) in address B in input first check bit stream or second check bit stream be expressed as B=ColPerm (c/2-16)-D; Wherein: ColPerm is the column permutation vector of the sub-block interleaving of rate-matched, and c is capable number.
9, according to the described processing method of claim 6, it is characterized in that, when " dummy bit " virtual systematic bits stream, first check bit stream and second check bit that is placed on separation flows the back described step 6.2), described step 7.2) the address A in the systematic bits stream of input is expressed as A=ColPerm (c), described step 7.3) in be expressed as B=ColPerm (c/2-16) at first check bit stream of input or the address B in second check bit stream; Wherein: ColPerm is the column permutation vector of the sub-block interleaving of rate-matched, and c is capable number.
10, according to the described processing method of claim 1, it is characterized in that, described step 1.3) specifically: to systematic bits stream and the check bit stream of exporting after the rate-matched, under high-order modulating, utilize high reliability bit in the planisphere to come data in the transmitting system bit stream, realize the bit priority mapping.
According to the described processing method of claim 10, it is characterized in that 11, bit collection deinterleaving method or Bit Interleave method are adopted in described realization.
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