CN102843153A - Parallel encoder of RS (Reed-Solomon) codes with multiple code rates in CCSDS (Consultative Committee for Space Data System) and encoding method - Google Patents
Parallel encoder of RS (Reed-Solomon) codes with multiple code rates in CCSDS (Consultative Committee for Space Data System) and encoding method Download PDFInfo
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- CN102843153A CN102843153A CN2012103747811A CN201210374781A CN102843153A CN 102843153 A CN102843153 A CN 102843153A CN 2012103747811 A CN2012103747811 A CN 2012103747811A CN 201210374781 A CN201210374781 A CN 201210374781A CN 102843153 A CN102843153 A CN 102843153A
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Abstract
The invention relates to a scheme of parallel encoding of RS (Reed-Solomon) codes with two different code rates in a CCSDS (Consultative Committee for Space Data System). The scheme is characterized in that a parallel encoder of RS codes with multiple code rates of a system mainly consists of a shifting register, 8-bit two-input exclusive-OR gate, a summation array and product selectors. One hundred and twenty-seven multi-input exclusive-OR gates in the array are subjected to share summation by a finite field multiplying unit. A result of the finite field multiplying unit is formed by the output of eight multi-input exclusive-OR gates selected from each product selector, and the all product selectors simultaneously complete the parallel calculation of 32 finite field multiplications. The two code rates are compatible in the single encoder, the control logic is simple, and under the premise of keeping the invariability of the encoding speed, the resource demands are lowered greatly, and the parallel encoder has the characteristics of low cost, small power consumption and the like.
Description
Technical field
The present invention relates to the spatial data communications field, the efficient parallel coding method of multi code Rate of Chinese character RS sign indicating number in the particularly a kind of CCSDS system.
Background technology
In digital communication system, in order to improve the reliability of data in the Channel Transmission process, often adopt the influence of forward error correction technique opposing noise and interference, reduce the error rate, improve the quality of reception.Reed---Suo Luomen (Reed-Solomon, RS) sign indicating number have powerful correction at random with the ability of burst error, obtained in the modern communication system using widely.
CCSDS recommends to adopt finite field gf (2
8) on (255, the k) RS of system sign indicating number.The RS code length is the n=255 byte, and code check has 2 kinds.Fig. 1 has provided the information data byte length k and the checking data byte length r=n-k of RS sign indicating number under the different code checks.
The structure of the parallel RS encoder of tradition is as shown in Figure 2, and it mainly is made up of shift register, 8 two input XOR gates and Galois field multiplier, and its implementation complexity depends on Galois field multiplier to a great extent.Finite field gf (2
m) operation principle of multiplier is, the sum of products multiplicand is expressed as 1 * m rank binary vector form a and b, and multiplier table is shown as m * m rank binary matrix form A, satisfies a=bC between them.As everyone knows, finite field gf (2
m) parallel multiplication is parallel completion of inner product operation that bC is decomposed into m the column vector of b and C.When multiplier was constant, inner product can be reduced to the summation operation that owns element among " 1 " corresponding vectorial b in the Matrix C column vector, that is to say finite field gf (2
m) parallel multiplication can be reduced to m summation operation Parallel Implementation by element among the vectorial b.It is thus clear that, when multiplier is constant, a finite field gf (2
m) parallel multiplier is actually m different many inputs XOR gate.Here so-called many input XOR gates are meant that the number range of its input is 1 ~ m, comprise single input and two inputs.Notice that single input XOR gate is actually direct-connected line.
For CCSDS system, m=8.The existing solution of RS high spped coding is to adopt traditional parallel RS encoder to realize the RS coding of 2 kinds of code checks respectively.Can know that by Fig. 1 and 2 this processing method needs 8=384 register of (16+32) * altogether, relates to 16+32=48 finite field gf (2
8) parallel multiplier, be equivalent to (16+32) * 8=384 many input XOR gate.During practical application, select one according to the RS code check from 2 kinds of RS encoders and encode.To sum up visible, existing solution need expend more resource, the control logic more complicated.
Summary of the invention
High this technical disadvantages of the implementation complexity that exists in the existing solution to CCSDS multi code Rate of Chinese character RS coding; The invention provides the variable efficient parallel coding method of a kind of code check; Use unity coder to handle multi code Rate of Chinese character RS sign indicating number; Simplify control logic, adopt many input XOR gate multiplexing machines to be shaped on the demand that reduces register and logical resource of imitating.
As shown in Figure 4, mainly form based on the parallel encoder of multi code Rate of Chinese character RS sign indicating number in the CCSDS standard of the multiplexing mechanism of many inputs XOR gate: shift register, 8 two input XOR gate, sum array and product selectors by 4 parts.
Galois field multiplier is the technological difficulties of RS encoder, and has determined implementation complexity to a great extent.The present invention uses sum array and product selector to accomplish the efficient realization of finite field parallel multiplication.All Galois field multipliers are shared the XOR gate of input more than 127 in the sum array.Each product selector is therefrom chosen the result of a Galois field multiplier of output composition of the XOR gate of input more than 8, and all product selectors are accomplished the concurrent operation of 32 finite field multipliers simultaneously.The multiplexing mechanism of many input XOR gates can effectively reduce logical resource.
Single parallel encoder provided by the invention can be handled multi code Rate of Chinese character RS sign indicating number, thereby has simplified control logic, has reduced the demand to register.
Can further be understood through ensuing detailed Description Of The Invention and accompanying drawing about advantage of the present invention and spirit.
Description of drawings
Fig. 1 has provided information data byte length and the checking data byte length of RS sign indicating number under 2 kinds of code checks;
Fig. 2 is the structured flowchart of the parallel RS encoder of tradition;
Fig. 3 is the multiplier constant when adopting the parallel RS encoder of tradition to realize 2 kinds of code check RS codings respectively;
Fig. 4 has provided the structural representation of the variable parallel RS encoder of code check;
Fig. 5 is the formation sketch map of sum array;
Fig. 6 is the multiplier constant of multi code Rate of Chinese character RS sign indicating number efficient parallel encoder;
Fig. 7 is product selector S
lThe structured flowchart of (0≤l≤15);
Fig. 8 is product selector S
lThe structured flowchart of (16≤l≤31);
Fig. 9 has compared the resource requirement of two kinds of solutions of the parallel RS coding of CCSDS multi code Rate of Chinese character.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the present invention is described further, but not as to qualification of the present invention.
The Base-Band Processing of CCSDS transmitter relates to the coding of 2 kinds of code check RS sign indicating numbers, and is as shown in Figure 1.Realize the RS coding of 2 kinds of code checks, multiplier constant g so respectively if adopt the parallel RS encoder of tradition shown in Figure 2
K, d(k=223 or 239,0≤d<255-k) inferior as shown in Figure 3 about the power of primitive element α.
Fig. 4 has provided the structural representation of the variable parallel RS encoder of code check, and it mainly is made up of shift register, 8 two input XOR gates, sum array and product selector four functional modules.
Shift register is by 32 eight bit register R
0, R
1..., R
31Cascade forms, and has inserted 31 8 two input XOR gates between the adjunct register.
Sum array is sued for peace to 8 elements among the multiplicand vector b, particularly, is from b, to choose the individual different element of i (1≤i≤8) to carry out mould 2 and add.Can know by permutation and combination knowledge, exhaustively obtain 2
8-1=255 different summation expression formula.In fact, only can use 127 summation expression formulas wherein, they are α
j(j ∈ 0～12,24～37,43～57,59～73,76～88,97～104,126～136,170～180,213～220,230～242,249～254}) binary vector form and the inner product of vectorial b.127 summation expression formulas can use the XOR gate of input more than 127 to realize.The input number scope of many input XOR gates is 1 ~ 8, and when having only an input, single input XOR gate is actually direct-connected line.To sum up, sum array has 8 inputs and 127 outputs, and its inside is made up of the XOR gate of input more than 127, and is as shown in Figure 5.
Product selector can be accomplished 32 finite field gfs (2 simultaneously
8) parallel multiplication.Product selector S
l(0≤l≤31) link to each other with the part output of sum array, its input number and multiplier constant c
K, l(k=223 or 239,0≤l≤31) are closely related, and working method also is controlled by c
K, lFig. 6 has provided the multiplier constant c of the variable parallel RS encoder of code check
K, lAbout the power of primitive element α, wherein α
∞=0.Comparison diagram 3 and 6 can be known c
K, lWith g
K, dBetween have certain relation: when k=223, c
K, l=g
K, l(0≤l≤31); When k=239, c
K, l=g
K, l-16(16≤l≤31).
Product selector S
lThe input number of (0≤l≤31) depends on 2 multiplier constant c
K, lNon-zero number in (k=223 or 239).When 0≤l≤15, has only c
223, lNon-zero, S
l1*8=8 input arranged, as shown in Figure 7; When 16≤l≤31,2 c
K, lNon-zeros all, S
l2*8=16 input arranged, as shown in Figure 8.
Product selector S
lThe input of (0≤l≤31) links to each other with the part output of sum array.As previously mentioned, when multiplier is constant, finite field gf (2
8) parallel multiplication can be reduced to 8 summation operation Parallel Implementation by element among the multiplicand vector b, and these 8 summation operation depend on 8 column vectors of the binary matrix C that the multiplier constant is corresponding fully.This means, can be according to multiplier constant c
K, lFrom 127 outputs of sum array, select 8 and form a finite field gf (2
8) result of parallel multiplication.Suppose c
K, lAbout the power of primitive element α is j (j ≠ ∞), product selector S so
l8 corresponding α of outputs difference from the sum array selection
j, α
J+1..., α
J+7Binary vector form and the inner product of vectorial b.In Fig. 7 and 8, product selector S
lThe 1st group of 8 inputs of (0≤l≤31) depend on multiplier constant c
223, lProduct selector S
lThe 2nd group of 8 inputs of (16≤l≤31) depend on multiplier constant c
239, l
Product selector S
lThe working method of (0≤l≤31) is controlled by multiplier constant c
K, lIn Fig. 7, when control end is c
223, lThe time, product selector S
lThe output of (0≤l≤15) equals input; And work as control end is c
239, l=0 o'clock, output complete zero.In Fig. 8, when control end is c
223, lAnd c
192, lThe time, product selector S
l(16≤l≤31) are exported the 1st group and the 2nd group of input respectively.
The invention provides the variable efficient parallel coding method of a kind of code check, in conjunction with the efficient parallel encoder (as shown in Figure 4) of multi code Rate of Chinese character RS sign indicating number in the CCSDS standard, its coding step is described below:
(1) zero clearing shift register R
0, R
1..., R
31, be respectively product selector S according to the RS code check
0, S
1..., S
31The appropriate multiplier constant c of control end configuration
K, 0, c
K, 1..., c
K, 31
(2) close switch Z
1And Z
2, cut-off switch Z
3The k byte information data is sent into encoder successively encodes.
(3) close switch Z
3, cut-off switch Z
1And Z
2The numerical value of Output Shift Register obtains r byte check data one by one.
Find out that easily the efficient parallel encoder of multi code Rate of Chinese character RS sign indicating number is accomplished a RS coding needs k+r=n clock cycle, this scramble time with the parallel RS encoder of tradition is identical.
The existing solution of CCSDS multi code Rate of Chinese character RS coding is to use the parallel RS encoder of tradition to realize the coding of 2 kinds of code checks respectively, needs 8=384 register of (16+32) * and (16+32) * 8=384 XOR gates of importing altogether more.And the present invention uses unity coder, and control is got up fairly simple, adopts the multiplexing mechanism of many input XOR gates, needs 32*8=256 register altogether and the XOR gate of input more than 127.As shown in Figure 9, to compare with existing solution, the register that the present invention uses has reduced 33%, imports XOR gate more and has reduced 67%.
To sum up visible, to compare with existing solution, the efficient parallel coding method of multi code Rate of Chinese character RS sign indicating number provided by the invention can be simplified control logic keeping greatly reducing resource requirement under the constant prerequisite of coding rate, has characteristics such as cost is low, power consumption is little.
Below through the specific embodiment and the embodiment the present invention has been carried out detailed explanation, for a person skilled in the art, under the situation that does not break away from the principle of the invention, also can make some distortion and improvement, these also should be considered as protection scope of the present invention.
Claims (8)
1. parallel encoder that is suitable for 2 kinds of different code check RS sign indicating numbers that the CCSDS standard adopts; For 2 kinds of code checks, the RS code length is the n=255 byte, and information data length k is respectively 223,239 bytes; Checking data length r is respectively 32,16 bytes; It is characterized in that said parallel encoder mainly comprises with lower component based on the multiplexing mechanism of many inputs XOR gate:
Shift register is by 32 eight bit register R
0, R
1..., R
31Cascade forms;
8 two input XOR gates, between register, totally 31;
Sum array is sued for peace to 8 elements among the multiplicand vector b;
Product selector S
l, accomplish 32 finite field gfs (2 simultaneously
8) parallel multiplication, its input number and working method and multiplier constant c
K, lClosely related, wherein, 0≤l≤31, k=223 or 239.
2. parallel encoder as claimed in claim 1 is characterized in that, said sum array has 8 inputs and 127 outputs, and its inside is made up of the XOR gate of input more than 127.
3. parallel encoder as claimed in claim 1 is characterized in that, said sum array is sued for peace to 8 elements among the multiplicand vector b, can use 127 summation expression formulas, and they are α
jBinary vector form and the inner product of vectorial b, wherein, α is a primitive element, j ∈ { 0～12; 24～37,43～57,59～73,76～88; 97～104,126～136,170～180,213～220; 230～242,249～254}, 127 summation expression formulas realize with the XOR gate of input more than 127.
4. parallel encoder as claimed in claim 1 is characterized in that, said product selector is accomplished 32 finite field gfs (2 simultaneously on the basis of sum array operation result
8) parallel multiplication, product selector S
lLink to each other its input number and multiplier constant c with the part output of sum array
K, lClosely related, working method also is controlled by c
K, l
5. parallel encoder as claimed in claim 1 is characterized in that, said product selector S
lThe input number depend on 2 multiplier constant c
K, lIn non-zero number:
When 0≤l≤15, has only c
223, lNon-zero, S
l1*8=8 input arranged;
When 16≤l≤31, c
223, lAnd c
239, lNon-zeros all, S
l2*8=16 input arranged.
6. parallel encoder as claimed in claim 1 is characterized in that, said product selector S
lInput link to each other with the part output of sum array, according to multiplier constant c
K, lFrom 127 outputs of sum array, select 8 and form a finite field gf (2
8) result of parallel multiplication:
When 0≤l≤31, product selector S
lThe 1st group of 8 inputs depend on multiplier constant c
223, l
When 16≤l≤31, product selector S
lThe 2nd group of 8 inputs depend on multiplier constant c
239, l
7. parallel encoder as claimed in claim 1 is characterized in that, said product selector S
lWorking method be controlled by multiplier constant c
K, l:
For product selector S
0~ S
15, when control end is c
223, lThe time, their output equals input separately respectively, is c and work as control end
239, l=0 o'clock, their output complete zero;
For product selector S
16~ S
31, when control end is c
223, lAnd c
239, lThe time, they export the 1st group and the 2nd group of input respectively.
8. parallel encoding method that is suitable for 2 kinds of different code check RS sign indicating numbers that the CCSDS standard adopts; For 2 kinds of code checks; The RS code length is the n=255 byte, and information data length k is respectively 223,239 bytes, and checking data length r is respectively 32,16 bytes; It is characterized in that said coding method may further comprise the steps:
(1) zero clearing shift register R
0, R
1..., R
31, be respectively product selector S according to the RS code check
0, S
1..., S
31The appropriate multiplier constant c of control end configuration
K, 0, c
K, 1..., c
K, 31
(2) close switch Z
1And Z
2, cut-off switch Z
3, the k byte information data is sent into encoder successively encodes;
(3) close switch Z
3, cut-off switch Z
1And Z
2, the numerical value of Output Shift Register obtains r byte check data one by one.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117752A (en) * | 2013-01-18 | 2013-05-22 | 苏州威士达信息科技有限公司 | High-speed parallel RS encoder and encoding method for consultative committee for space data system (CCSDS) system |
| CN103152059A (en) * | 2013-01-18 | 2013-06-12 | 苏州威士达信息科技有限公司 | Device and method of generating of constant coefficient matrix of radio sonde (RS) of consultative committee for space data system (CCSDS) |
| CN105322973A (en) * | 2014-10-16 | 2016-02-10 | 航天恒星科技有限公司 | RS code coder and coding method |
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| US20060090119A1 (en) * | 2004-10-07 | 2006-04-27 | Qiujie Dong | System and method for implementing a Reed Solomon multiplication section from exclusive-OR logic |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103117752A (en) * | 2013-01-18 | 2013-05-22 | 苏州威士达信息科技有限公司 | High-speed parallel RS encoder and encoding method for consultative committee for space data system (CCSDS) system |
| CN103152059A (en) * | 2013-01-18 | 2013-06-12 | 苏州威士达信息科技有限公司 | Device and method of generating of constant coefficient matrix of radio sonde (RS) of consultative committee for space data system (CCSDS) |
| CN103117752B (en) * | 2013-01-18 | 2015-12-09 | 苏州威士达信息科技有限公司 | CCSDS system high-speed walks abreast RS encoder and coding method |
| CN105322973A (en) * | 2014-10-16 | 2016-02-10 | 航天恒星科技有限公司 | RS code coder and coding method |
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Application publication date: 20121226 |