WO2024021360A1

WO2024021360A1 - Counter

Info

Publication number: WO2024021360A1
Application number: PCT/CN2022/130232
Authority: WO
Inventors: 严波; 方超敏; 王悦
Original assignee: 普源精电科技股份有限公司
Priority date: 2022-07-28
Filing date: 2022-11-07
Publication date: 2024-02-01
Also published as: CN115189691A

Abstract

Provided in the embodiments of the present application is a counter, comprising: a counting module, which comprises a plurality of cascaded sub-counters and a delay unit connected between at least two adjacent sub-counters among the plurality of sub-counters, wherein the sub-counters are used for counting the number of clock pulses to output count output signals and carry output signals, and the delay unit is used for receiving a carry output signal from the sub-counter at the former stage among the at least two sub-counters, delaying the received carry output signal and outputting same to the sub-counter at the latter stage; and a data alignment module, which is used for receiving the count output signals from the plurality of sub-counters and performing, according to a correspondence with a delay time caused by the delay unit, data alignment on a plurality of received count output signals that belong to the same counting period, so as to output a counting result. In this way, the operating speed of the counter is increased while the counting accuracy is ensured, thereby facilitating the implementation of a counter having more bits.

Description

counter

Technical field

The invention relates to the technical field of circuits and systems, and in particular to a counter.

Background technique

The counter is a commonly used sequential logic circuit and an important part of digital circuits. Its most basic function is to count by counting the number of clock pulses.

The higher the number of bits (digits/number of bits) of the counter, the more difficult it is to achieve high speed. This is mainly related to the structure of the counter. The counter uses the AND gate to generate carry. As the number of digits in the counter increases, the inputs of the AND gate will increase one level at a time. When the input of the AND gate exceeds a certain level, the AND operation has to be performed hierarchically, that is, the first few data are ANDed first, and the result of the operation then enters the new AND gate for the next level operation. However, this will cause the propagation delay of the carry signal to increase, and when the number of AND gate levels increases to the point where the propagation delay of the carry signal becomes comparable to the clock cycle, the speed of the counter reaches its limit. It can be seen that the higher the number of digits in the traditional counter structure, the slower the speed; this becomes the biggest limitation of high-speed counters. In addition, propagation delays can easily cause counting errors.

How to continuously improve the running speed of the counter and realize a high-digit counter while ensuring the counting accuracy is an important technical problem that this field has been trying to solve.

Contents of the invention

In view of this, embodiments of the present application provide a counter to solve at least one problem existing in the background art.

An embodiment of the present application provides a counter, including:

A counting module includes a plurality of cascaded sub-counters and a delay unit connected between at least two adjacent sub-counters in the plurality of sub-counters; wherein the sub-counters are used to count the number of clock pulses. Count to output a count output signal and a carry output signal; the delay unit is used to receive the carry output signal of the previous sub-counter in the at least two sub-counters, and delay the received carry output signal before outputting it to The next level sub-counter;

A data alignment module, configured to receive counting output signals of multiple sub-counters, and align the received multiple counting output signals belonging to the same counting cycle according to the relationship corresponding to the delay time caused by the delay unit. Data alignment to output count results.

In an optional implementation, a delay unit is provided between every two adjacent levels of sub-counters in the plurality of sub-counters.

In an optional implementation, the delay unit includes a flip-flop, which uses a clock pulse as a control signal to receive the carry output signal of the previous stage sub-counter and output the delayed carry output signal to the The next level sub-counter.

In an optional implementation, at least one of the sub-counters is an n-bit (n-bit) counter, where n is greater than 1; a carry signal is generated between each bit in the n-bit counter through an AND gate;

The input end of at least one AND gate in the n-bit counter is connected to the input end of the previous one-bit AND gate;

The n-bit counter including no more than one AND gate adopts the following connection method: the input end of the AND gate of this bit is connected to the output end of the previous bit AND gate.

In an optional implementation, the data alignment module includes a trigger, and the data alignment module performs data alignment based on the trigger.

In an optional implementation, the sub-counter is an n-bit counter, where n is greater than or equal to 1; each bit in the n-bit counter includes a first flip-flop; the first flip-flop The device includes a counting input terminal and a counting output terminal; the counting output signal includes a signal of the counting input terminal and/or a signal of the counting output terminal;

The delay unit includes at least one second flip-flop; the second flip-flop uses a clock pulse as a control signal to receive the carry output signal of the previous sub-counter and output the delayed carry output signal to the subsequent sub-counter. Level sub counter;

The data alignment module includes at least one third flip-flop, and the data alignment module performs data alignment based on the third flip-flop;

The data alignment module includes a plurality of lines corresponding to a plurality of the sub-counters, and each line in the plurality of lines receives a counting output signal of a corresponding sub-counter;

For a line among the plurality of lines in which the received counting output signal is a signal at a counting output terminal, the number of the third flip-flops cascaded on the line is equal to the number of sub-counters in the counting module corresponding to the line. The number of second flip-flops to the last sub-counter is equal;

For a line among the plurality of lines in which the received counting output signal is a signal at the counting input end, the number of the third flip-flops cascaded on the line is equal to the number of sub-counters in the counting module corresponding to the line. The number of second flip-flops to the last sub-counter is incremented by one.

In an optional implementation, the counting output signal received by the line corresponding to the last stage sub-counter in the counting module among the plurality of lines is the signal of the counting input terminal.

In an optional implementation, the counting output signal includes a signal of the counting input terminal and a signal of the counting output terminal; among the plurality of lines, other lines except the line corresponding to the last stage sub-counter , the received counting output signal is the signal at the counting output terminal.

In an optional implementation, it also includes a clock module,

The clock module is used to generate a first clock signal and a second clock signal, the counting module operates based on the first clock signal, and the data alignment module operates based on the second clock signal.

In an optional implementation, the clock module includes a clock signal input end and a first clock generation line and a second clock generation line connected to the clock signal input end; the first clock generation line is used to generate the clock signal based on the clock signal input end. The clock signal input to the clock signal input terminal generates the first clock signal; the second clock generation circuit is used to generate the second clock signal based on the clock signal input to the clock signal input terminal; the first clock A delay unit is connected to the generation line and/or the second clock generation line.

In an optional implementation, at least two delay units are respectively connected to the first clock generation line and the second clock generation line, and the delay unit located at the later stage has a fan-out capacity greater than that at the previous stage. The fan-out capability of the delay unit.

The counter provided by the embodiment of the present application is provided with a delay unit between at least two adjacent sub-counters among the plurality of sub-counters. The delay unit is used to receive the carry output signal of the previous sub-counter in at least two sub-counters, and Delay the received carry output signal and output it to the subsequent sub-counter; further receive the count output signals of multiple sub-counters through the data alignment module, and according to the relationship corresponding to the delay time caused by the delay unit, the received carry output signal belongs to the same Multiple counting output signals in one counting cycle are data aligned, and the counting result is finally output; in this way, the problem of the propagation delay of the carry signal in the traditional counter structure that limits the counting accuracy and operating speed is solved, while ensuring the counting accuracy. Under the premise, the running speed of the counter is improved, which is conducive to realizing a higher-digit counter.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Description of drawings

The drawings described here are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the attached picture:

Figure 1 is a schematic structural diagram of a counter provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of a counting module in an embodiment of the present application;

Figure 3 is a schematic structural diagram of neutron counting according to an embodiment of the present application;

Figure 4 is a schematic structural diagram of a data alignment module in an embodiment of the present application;

Figure 5 is a schematic structural diagram of a clock module in an embodiment of the present application;

Figure 6 is a schematic structural diagram of a counter provided in a specific example of this application.

Detailed ways

In order to make the technical solutions and beneficial effects of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present application are clearly and completely described below by enumerating specific embodiments. Obviously, the described embodiments are only for the purpose of this application. Apply for some of the embodiments, not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, the second resistor may be referred to as a first resistor, without departing from the scope of the present application. The first resistor and the second resistor are both resistors, but they are not the same resistor. When a "first" is described, it does not mean that there must be a "second"; and when a "second" is discussed, it does not mean that there must be a first element, component, region, layer or section in the present application. As used herein, the singular forms "a," "an," and "the" may also be intended to include the plural forms as well, unless the context clearly dictates otherwise. "Plural" means more than two, unless otherwise clearly and specifically limited. It will also be understood that the term "comprising", when used in this specification, identifies the presence of stated features but does not exclude the presence or addition of one or more other features. When used herein, the term "and/or" includes any and all combinations of the associated listed items.

First, please refer to Figure 1. The counter provided by the embodiment of the present application includes a counting module and a data alignment module.

Specifically, the counting module includes a plurality of cascaded sub-counters and a delay unit connected between at least two adjacent sub-counters in the plurality of sub-counters.

Figure 1 shows an example in which the counting module includes a first sub-counter, a second sub-counter... an N-th sub-counter, and a first delay unit and a second delay unit. It should be understood that the number of sub-counters in the embodiment of the present application can be large enough to achieve a larger number of counts. For example, the number of sub-counters can be dozens, hundreds or more; this application does not specify this. limit. Moreover, the improved technical solution proposed in this application is at least applicable to counters with no less than two sub-counters (that is, N can be more than two).

By cascading each sub-counter, the capacity can be expanded. As shown in Figure 3, each sub-counter includes a carry input terminal CI and a carry output terminal CO; the cascade connection of each sub-counter means that the carry output terminal CO of the sub-counter located at the previous stage is coupled to the sub-counter located at the subsequent stage. The carry input terminal CI of the counter. Therefore, the sub-counter located at the previous stage outputs a carry output signal through the carry output terminal CO, and the carry output signal is transmitted as the input of the sub-counter located at the subsequent stage to the carry input terminal CI of the sub-counter at the subsequent stage, To participate in the counting operation of the subsequent sub-counter. It can be understood that "coupling" in the context of this application means that the coupled end and the coupled end have mutual transmission of electrical signals or data, which can be understood as "electrical connection", "communication connection", etc.

In addition, each sub-counter also includes a clock signal input terminal and a counting output terminal. Among them, the clock signal input end can refer to the end of each sub-counter connected to CLOCK1 in Figure 1 or the end of the sub-counter connected to CLOCK in Figure 3. Each sub-counter receives a clock signal through a clock signal input terminal. The clock signal is specifically in the form of a clock pulse. The sub-counter is used to count the number of clock pulses to output a count output signal and a carry output signal.

Taking a 4-bit counter as an example, every time the clock pulse increases, the output count output signal changes once. Specifically, the count changes from 0000, 0001, 0010, 0011... to 1111, and a total of 16 results (the number of clock pulses) can be output From 0 to 15), the signals output by these 16 results through high level representing 1 and low level representing 0 are the counting output signals. After the counting result reaches 1111, the clock pulse increases by one again, which obviously exceeds the maximum value that can be represented by the current 4 bits. At this time, a carry is required, that is, the carry output is 1, and the counting result becomes 0000; understandably, in binary , 10000 means 16, that is, the number of clock pulses changes from 0 to 16. Carry output 1 is specifically reflected in a change in the level of the carry output signal.

It can be seen that the count output signal represents the signal corresponding to the specific result of the counter counting the number of clock pulses; the carry output signal represents the signal that is output when the counter reaches the maximum count value and the clock pulse increases again, and the count result requires a carry. signal of. The carry input terminal CI is used to output the carry output signal; the count output terminal is used to output the count output signal.

The counting output can refer to D1, D2...DN in Figure 1, or DA<0> to DA<3> and/or DS<0> to DS<3> in Figure 3; in the following, DA<0> to DA<3> will be represented by DA<3:0>, and from DS<0> to DS<3> will be represented by DS<3:0>; obviously, DA<3:0> and/or DS in Figure 1 <3:0> corresponds to D1 in Figure 1. Of course, D2 to DN in Figure 1 can also be the same or similar to D1.

The delay unit is configured to receive a carry output signal of a previous sub-counter in at least two sub-counters, delay the received carry output signal and then output it to a subsequent sub-counter. Referring specifically to FIG. 1 , the first delay unit receives the carry output signal of the first sub-counter, delays the received carry output signal, and then outputs it to the second sub-counter. Figure 1 shows the situation where a delay unit is provided between each two adjacent sub-counters in multiple sub-counters; in specific applications, this arrangement can be used to make the components of the entire counting module periodically , thus having a simple structure, high operational stability, and greatly avoiding the impact of the propagation delay of the carry signal. Of course, the number and location of delay units can also be selected based on actual needs. In this embodiment, a delay unit is provided at least between a pair of two adjacent sub-counters, thereby reducing, at least to a certain extent, the impact of the carry signal propagation delay caused by the AND gate operation on the number and accuracy of the counters.

It can be understood that the delay unit can cause the carry output signal of the previous sub-counter to be transmitted to the subsequent sub-counter after a delay of an exact duration or an exact period, so that the subsequent sub-counter can participate in counting at an exact duration or exact period. operation; in other words, the delay made by the delay unit to the carry output signal means that compared with the carry output signal being directly transmitted to the subsequent sub-counter, the carry output signal is transmitted to the subsequent sub-counter at a later time. However, Precisely because the exact duration or exact period can be controlled through the delay unit, there is almost no delay when the carry output signal is transmitted to the subsequent sub-counter compared with the clock signal, thereby avoiding the delay caused by the AND gate operation.

The data alignment module is used to receive the counting output signals of multiple sub-counters and align the received multiple counting output signals belonging to the same counting cycle according to the relationship corresponding to the delay time caused by the delay unit to output the counting results. .

For example, at the first moment, the first sub-counter transmits the counting output signal (such as DS<3:0>) to the data alignment module; due to the existence of the first delay unit, the second sub-counter needs to transfer the count output signal at the second moment. Its counting output signal (such as DS<7:4>) is transmitted to the data alignment module. It can be seen that the delay time caused by the first delay unit causes the gap between the second moment and the first moment; similarly, if the second sub-counter The carry output signal is output to the third sub-counter (not shown in Figure 1) after passing through the second delay unit. Then, the third sub-counter needs to count the output signal at the third moment (such as DS<11:8>) When transmitted to the data alignment module, the third time is later than the second time by the delay time caused by the second delay unit, and the third time is later than the first time by the delay time caused by the first delay unit and the second delay unit. The data alignment module will receive the counting output signals DS<3:0>, DS<7:4> and DS<11:8> of each sub-counter at different times. However, DS<3:0>, DS<7 :4> and DS<11:8> actually belong to the same counting cycle; the data alignment module is configured to time-align DS<3:0> and DS<7 according to the relationship corresponding to the delay time caused by the delay unit. :4> and DS<11:8> are aligned to output the counting result. Among them, the corresponding relationship is as follows: DS<3:0> is earlier than DS<11:8> due to the delay time caused by the first delay unit and the second delay unit, DS<7:4> is earlier than DS<11:8 >The delay time caused by the second delay unit is earlier.

It can be seen from this that the embodiment of the present application sets a delay unit between at least two adjacent sub-counters among the plurality of sub-counters. The delay unit is used to receive the carry output signal of the previous sub-counter in at least two sub-counters, and The received carry output signal is delayed and output to the subsequent sub-counter; further, the count output signals of multiple sub-counters are received through the data alignment module, and the received ones belong to the same one according to the relationship corresponding to the delay time caused by the delay unit. Multiple counting output signals of the counting cycle are data aligned, and the counting result is finally output; thus solving the problem that the propagation delay of the carry signal in the traditional counter structure limits the counting accuracy and operating speed, while ensuring the counting accuracy. , which improves the running speed of the counter and is conducive to the realization of higher-digit counters.

In a specific embodiment, the delay unit includes a flip-flop, which uses clock pulses as control signals to receive the carry output signal of the previous stage sub-counter and output the delayed carry output signal to the subsequent stage sub-counter.

It can be understood that the flip-flop can provide a delay of an integer period, and as a commonly used circuit element in counters, it can simplify the device structure and achieve a stable and reliable delay effect. However, the specific selection of the delay unit in this application is not limited to this. Other components that can delay the carry output signal of the previous sub-counter can also be applied here, such as programmable delay modules.

Figure 2 shows a schematic structural diagram of a specific counting module. The counting module includes a plurality of cascaded sub-counters and a flip-flop connected between each two adjacent levels of sub-counters. The flip-flop includes a clock signal input terminal, a D terminal that receives a data signal, and a Q terminal that outputs a delayed data signal. The clock signal input end of the flip-flop can refer to the end connected to CLOCK1 in the figure. The flip-flop receives the clock signal through the clock signal input end. The clock signal is specifically in the form of a clock pulse. The flip-flop uses the clock pulse as the control signal to start from a stable state. flip to another stable state. The clock signal input terminal of the flip-flop and the clock signal input terminal of each sub-counter are connected to the same clock signal (CLOCK1 in the figure), and thus work under the control of the same clock signal. The D terminal of the flip-flop is connected to the carry output terminal of the previous sub-counter (the carry output terminal refers to CO0 and CO1 in the figure), thereby receiving the carry output signal of the previous sub-counter; the Q terminal of the flip-flop is connected to the carry output terminal of the subsequent sub-counter. The carry input terminal of the counter is connected to output the delayed carry output signal to the subsequent sub-counter. In specific applications, the flip-flop can be directly connected to the previous-level sub-counter and the subsequent-level sub-counter, that is, no other components other than wires are included therebetween.

In order to facilitate distinction, in the following description, the flip-flop serving as the delay unit may also be referred to as the "second flip-flop". In various embodiments, the second flip-flop may be a D flip-flop. Of course, the present application is not limited to this. In other embodiments, other delay circuits may also be used.

Next, please refer to Figure 3. It should be understood that in the description of this application, it is considered that the counting module in the timer is composed of multiple counters cascaded, so for the convenience of distinction, the cascaded counters are called "sub-counters"; however, this does not mean that Sub-counters are different from counters as commonly understood by those skilled in the art. As an example, Figure 3 shows a schematic structural diagram of a sub-counter. As shown in the figure, the sub-counter includes a flip-flop, an XOR gate and an AND gate; for ease of distinction, in the following description, the flip-flop in the sub-counter may also be called the "first flip-flop". The sub-counter is a 4-bit counter, including 4 groups of periodically arranged flip-flops, XOR gates and AND gates, and each group of flip-flops, XOR gates and AND gates corresponds to one bit in the 4-bit counter. Among them, CI is the carry input terminal, CO is the carry output terminal; DS in each bit is the counting output terminal of the bit, and DA is the counting input terminal of the bit. Since the signal of DS is output after a flip-flop delay compared with DA, the signal at DS is usually one clock cycle later than the signal at DA. The counting result at DA can also be called the counter output minus 1.

As the first-stage sub-counter in the counting module, its carry input terminal CI may not be connected to a signal, such as being left vacant; as the last-stage sub-counter in the counting module, its carry output terminal CO may not be coupled to other sub-counters, such as Vacant; in addition, the carry input terminal CI of the sub-counter cascaded in the middle of the counting module is used to receive the output signal of the carry output terminal CO of the previous sub-counter, and its carry output terminal CO is used to transfer the output signal It is transmitted to the carry input terminal CI of the subsequent sub-counter.

The XOR gate has two input terminals, one of which is connected to the Q terminal of the flip-flop in the same group (or the same bit), and the other input terminal is connected to the AND in the previous group (or the previous bit). The output of the gate is connected. The two input terminals corresponding to the XOR gate receive the same input signal. If both receive a high level 1, or both receive a low level 0, then the output terminal of the XOR gate outputs a low level 0; The two input terminals corresponding to the XOR gate receive different input signals. If they receive a high level 1 and a low level 0 respectively, the output terminal of the XOR gate outputs a high level 1. The output terminal of the XOR gate is connected to the D terminal of the first flip-flop.

An AND gate consists of multiple inputs and an output. A carry signal is generated between each bit in the sub-counter through an AND gate. If multiple input terminals corresponding to the AND gate all receive high-level 1, then the output terminal of the AND gate outputs a high-level 1; otherwise, the output terminal of the AND gate outputs a low-level 0. As mentioned before, the output of the AND gate is connected to the input of the XOR gate in the next group (or last bit). One input terminal of the AND gate is connected to the Q terminal of the flip-flop in the same group; other input terminals of the AND gate may have different connection methods depending on the number of bits in which the AND gate is located.

The input terminal of the AND gate located in the first group (or first bit) of the sub-counter is connected to the carry input terminal CI of the sub-counter. The input terminals of the AND gates located in the second group (or second bit) and the third group (or third bit) of the sub-counter are connected to the input end of the AND gate in the previous bit. The input terminal of the AND gate located in the fourth group (or fourth bit) of the sub-counter is connected to the output terminal of the previous AND gate. It can be understood that whether it is connected to all the input terminals of the previous AND gate or to the output terminal of the previous AND gate, based on the working principle of the AND gate, the output result is the same. However, for the case where all the input terminals of the AND gate of the previous bit are connected, the signal does not need to go through the AND gate of the previous bit for AND operation, but is only transmitted through the wire, with almost no propagation delay; conversely, if it is connected to the AND gate of the previous bit If the output of the AND gate is connected, the AND operation needs to be performed through the previous AND gate, which will increase the propagation delay due to the AND gate.

Although Figure 3 shows a 4-bit counter as an example, it can be understood that as the number of bits in the counter increases, the number of inputs to the AND gate will increase. However, the number of input terminals of the AND gate is limited and cannot be increased infinitely. When the input of the AND gate exceeds a certain level, the AND operation has to be performed hierarchically. That is, just like the AND gate in the fourth bit in Figure 3, the previous bit AND gate performs an AND operation on the previous bits of data, and the result of the operation is then output to the fourth bit AND gate for the next level operation.

As an optional implementation manner of this application, at least one sub-counter is an n-bit (n-bit) counter, where n is greater than 1; a carry signal is generated between each bit in the n-bit counter through an AND gate; at least one of the n-bit counters The input end of the AND gate of one bit is connected to the input end of the AND gate of the previous bit; the n-bit counter including no more than one AND gate adopts the following connection method: the input end of the AND gate of this bit is connected to the input end of the previous bit AND gate. Connect to the output of the AND gate. It can be understood that when more than one-bit AND gate needs to be connected with the input terminal of the previous-bit AND gate, that is, the number of input terminals of the AND gate cannot bear to receive the previous-bit AND gate. For all input signals, the AND gate may not be used. In other words, the sub-counter including two or more AND gates using the above connection method may not be used, and the technical solution provided by the embodiment of the present application may be used to solve this problem.

Optional, n is less than or equal to 6.

In practical applications, the sub-counter can be a 4-bit counter or a 3-bit counter. The sub-counter may include and only include one AND gate connected using the following connection method: the input end of the AND gate of this bit is connected to the output end of the AND gate of the previous bit; or, it may not exceed the number of connections using the following connection method. AND gate: The input end of the AND gate of this bit is connected to the output end of the AND gate of the previous bit.

Figure 4 shows a schematic structural diagram of a data alignment module. As shown in the figure, the data alignment module includes a counting output signal receiving end, a clock signal input end, and a counting result output end.

Among them, please refer to DA1-N and DS1-N in the figure for the counting output signal receiving end; the structure shown in the figure does not mean that there are two counting output signal receiving ends of the data alignment module. In fact, the counting output signal receiving end There can be more than one; and, the counting output signal receiving end can receive both DA1-N and DS1-N signals, or only DA1-N or DS1-N signals, and can also receive part of DA1-N. signals as well as receiving signals from parts of the DS1-N. DA1-N and DS1-N can be understood in conjunction with Figure 2 and Figure 3; taking DA1 as an example, it represents the counting input end of the first-level sub-counter (n bit counter) in Figure 2, corresponding to Figure 3 DA<3:0>; Similarly, DS1 represents the counting output terminal of the first-level sub-counter in Figure 2, corresponding to DS<3:0> in Figure 3. DA1-N means from DA1 to DAN; similarly, DS1-N means from DS1 to DSN.

For the clock signal input end of the data alignment module, please refer to CLOCK2 in Figure 4. CLOCK2 and CLOCK1 can be clock synchronized or have phase differences.

For the counting result output terminal of the data alignment module, please refer to DOUT in Figure 4. The counting result output terminal is configured to output the counting result.

Please refer to Figure 6. In an optional embodiment of the present application, the data alignment module includes a flip-flop, and the data alignment module performs data alignment based on the flip-flop.

In a more specific optional embodiment, the sub-counter is an n-bit counter, where n is greater than or equal to 1; each bit in the n-bit counter includes a first flip-flop; the first flip-flop includes a counting input terminal and counting output terminal; the counting output signal includes the signal of the counting input terminal and/or the signal of the counting output terminal; the delay unit includes at least one second flip-flop; the second flip-flop uses the clock pulse as the control signal to receive the previous stage sub-counter The carry output signal and the delayed carry output signal are output to the subsequent sub-counter; the data alignment module includes at least one third flip-flop, and the data alignment module performs data alignment based on the third flip-flop; the data alignment module includes and multiple sub-counters Corresponding multiple lines, each line in the multiple lines receives the counting output signal of the corresponding sub-counter; for the line in which the received counting output signal is the signal of the counting output terminal, the cascaded third line on the line The number of three flip-flops is equal to the number of second flip-flops in the counting module from the sub-counter corresponding to the line to the last sub-counter; for the counting output signal received in multiple lines, it is the signal of the counting input terminal line, the number of third flip-flops cascaded on this line is equal to the number of second flip-flops in the counting module from the sub-counter corresponding to the line to the last sub-counter plus 1.

It can be understood that Figure 6 shows a cascade of four sub-counters as an example, and each sub-counter uses a 4-bit counter, thereby realizing a 16-bit counter. Among them, 4 4-bit counters are divided into 4-level pipeline structure; therefore, the counting module can also be called "pipeline counter core". Of course, the embodiments of the present application are not limited to this. The pipeline counter core may include multiple n-bit counters; the number of bits in each sub-counter may be the same or different.

The carry output signals of the first-level sub-counter are snapped together by a flip-flop and enter the second-level pipeline to participate in the counting operation. The carry output signal of the second-level sub-counter passes through a flip-flop and then participates in the third-level operation, and so on. Finally, each sub-counter generates 4 bits of DA and DS. It can be known that when the carry output signal of the first-level sub-counter is generated, it takes one clock cycle before it participates in the second-level operation. After the carry output signal passes through the second stage of pipeline processing, it passes through a flip-flop before entering the third stage to participate in the operation. After the third level, a level of flip-flop is required to perform the final fourth level operation and final output. Therefore, the counting result of the first-level sub-counter (counting output signal) ultimately needs to go through three additional flip-flops to complete the operation. This means that the count of the first-level sub-counter is transmitted to the data alignment module 3 cycles earlier than the count result of the last-level sub-counter. Therefore, when the data is finally aligned, DS<3:0> of the first-level sub-counter needs to be delayed by three clock cycles before it can be used as part of the final output counting result and matched with the counting output signals output by other sub-counters. Piece together. In the same way, DS<7:4> of the second-level sub-counter needs to go through a delay of two clock cycles; the third-level sub-counter needs to go through a delay of one clock cycle. In this way, in the data alignment module, three third flip-flops are cascaded on the line that receives DS<3:0> of the first-level sub-counter; two third flip-flops are cascaded on the line that receives DS<7:4> of the second-level sub-counter. A third flip-flop; a third flip-flop is cascaded on the line receiving DS<11:8> of the third-level sub-counter.

As for the fourth-level sub-counter, as an optional implementation method, similar to the previous sub-counters, the DS<15:9> of the fourth-level sub-counter can be output to the data alignment module, so that no delay is required. When , it is directly output as part of the counting result; accordingly, there is no need to cascade the third flip-flop on the line receiving DS<15:9> of the fourth-level sub-counter. However, as another optional implementation, the last stage (specifically the fourth stage in this implementation) sub-counter preferably also passes through a flip-flop, that is, a line that receives the counting output signal of the last stage sub-counter. A third flip-flop is cascaded up. In this way, it can be ensured that the final output counting result is triggered by the synchronous clock (requirement of the synchronous sequence counter), avoiding that the DS of the last stage counter is driven by CLOCK1, and the output counting result is driven by CLOCK2, resulting in asynchronous question. For the implementation in which a third flip-flop is cascaded on the line that receives the count output signal of the last stage sub-counter, DA<15:9> is used as the final output instead of DS<15:9>.

Optionally, the counting output signal received by the line corresponding to the last sub-counter in the counting module among the multiple lines is the signal of the counting input terminal. In this way, for a line among multiple lines in which the received counting output signal is a signal at the counting input terminal, the number of third flip-flops cascaded on the line is equal to the number of the counting module from the sub-counter corresponding to the line to the last sub-counter. The number of second flip-flops between counters is increased by 1; specifically for the last sub-counter, there is no second flip-flop behind it, that is, the number is 0, and the number of third flip-flops cascaded on its corresponding line is equal to 0+1, that is, connect a third flip-flop.

Optionally, the counting output signal includes the signal of the counting input terminal and the signal of the counting output terminal; among the multiple lines, except for the line corresponding to the last stage sub-counter, the counting output signal received is the signal of the counting output terminal. In this way, on the one hand, it is ensured that the final output counting result is triggered by the synchronous clock, on the other hand, the number of flip-flop settings is saved as much as possible and the device cost is reduced.

It should be understood that the embodiments of the present application are not limited to this. Among the multiple lines corresponding to other sub-counters except the last stage in the counting module, the received counting output signal can also be the signal of the counting input terminal, and should also be considered. It works.

Next, please combine Figure 1, Figure 5 and Figure 6. The counter provided by the embodiment of the present application can also include a clock module. The clock module is used to generate a first clock signal and a second clock signal. The counting module is based on the first clock signal. To work, the data alignment module works based on the second clock signal.

As shown in Figure 5, the clock module includes a clock signal input terminal (please refer to CLOCK in the figure), a first clock signal output terminal (please refer to CLOCK1 in the figure), and a second clock signal output terminal (please refer to CLOCK2 in the figure). The clock module mainly generates the first clock signal and the second clock signal for use by the counting module and the data alignment module based on the clock signal input from the clock signal input terminal.

The phase difference between the first clock signal and the second clock signal can be set according to actual conditions. Specifically, the phase relationship between the two clock signals can be formulated according to the delay of the device that implements the counter, thereby ensuring maximum timing margin. As an optional implementation manner, there may be no phase difference between the first clock signal and the second clock signal, and the two clock signals may be synchronized. As another optional implementation manner, there is a phase difference between the first clock signal and the second clock signal. It is understandable that sometimes in order to achieve a higher speed, CLOCK2 can be made faster or slower than CLOCK1, so as to achieve sufficient timing margin.

Considering that as the number of counter bits increases, the driving requirements of the synchronous clock will gradually increase, which may cause coordination problems with the synchronous clock. If the flip-flops of each flip-flop do not flip at the same time, counting errors will occur. Therefore, in addition to the function of adjusting the phase relationship between the first clock signal and the second clock signal, the clock module also needs to consider increasing the driving capability of the clock.

Please refer to Figure 6. As an optional implementation, the clock module includes a clock signal input terminal and a first clock generation line and a second clock generation line connected to the clock signal input terminal; the first clock generation line is used to generate a clock signal based on the clock signal input terminal. The clock signal input at the signal input terminal generates a first clock signal; the second clock generation line is used to generate a second clock signal based on the clock signal input at the clock signal input terminal; the first clock generation line and/or the second clock generation line are connected There are delay units.

Specifically, in Figure 6, two delay units (delay unit 1 and delay unit 2) are connected to the first clock generation line and two delay units (delay unit 3 and delay unit 4) are connected to the second clock generation line as an example. Out, a total of four delay units are used.

In an optional implementation, at least two delay units may be connected to the first clock generation line and the second clock generation line respectively; thus, compared with using one delay unit, the flexibility of phase adjustment is further increased. Moreover, when there are more than two delay units connected on the line, the fan-out capability of the delay unit located at the next level is greater than the fan-out capability of the delay unit located at the previous level; thus, the fan-out capability is gradually expanded to achieve stronger driving ability.

Each embodiment of the present application can be applied to a high-speed pattern generator. The embodiment adopts a pipeline structure. After the carry bit of each sub-counter is output, it is clicked by a flip-flop to form a pipeline structure to offset the delay of the carry chain; each sub-counter will output its own DA and DS, data The alignment module mainly receives the DS and DA values output by the pipeline counter, and through the determined timing relationship, aligns the data belonging to the same counting cycle to form the final output. In this way, the problem that the carry chain of the traditional counter structure is too long causes the carry delay to be too long, thereby restricting the maximum operating speed of the counter. Using clock tree redistribution, the clock phase relationship can be freely adjusted according to the characteristics of the process device itself, maximizing the counter speed under the same set of processes.

Each embodiment of the present application can achieve a great improvement in the running speed of the counter without changing the digital standard device used, which is of great significance in terms of function and cost.

The technical features of the above-described embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, All should be considered to be within the scope of this manual.

The above-mentioned embodiments only express several implementation modes of the present invention. The descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the patent of the present invention should be determined by the appended claims.

Claims

A counter, characterized in that it includes:

A counting module includes a plurality of cascaded sub-counters and a delay unit connected between at least two adjacent sub-counters in the plurality of sub-counters; wherein the sub-counters are used to count the number of clock pulses. Count to output a count output signal and a carry output signal; the delay unit is used to receive the carry output signal of the previous sub-counter in the at least two sub-counters, and delay the received carry output signal before outputting it to The next level sub-counter;

A data alignment module, configured to receive counting output signals of multiple sub-counters, and align the received multiple counting output signals belonging to the same counting cycle according to the relationship corresponding to the delay time caused by the delay unit. Data alignment to output count results.
The counter according to claim 1, wherein a delay unit is provided between every two adjacent sub-counters in the plurality of sub-counters.
The counter according to claim 1 or 2, characterized in that the delay unit includes a flip-flop, which uses a clock pulse as a control signal to receive the carry output signal of the previous stage sub-counter and output the delayed The carry output signal is sent to the subsequent sub-counter.
The counter according to claim 1, characterized in that at least one of the sub-counters is an n-bit (n-bit) counter, where n is greater than 1; a carry signal is generated between each bit in the n-bit counter through an AND gate. ;

The input end of at least one AND gate in the n-bit counter is connected to the input end of the previous one-bit AND gate;

The n-bit counter including no more than one AND gate adopts the following connection method: the input end of the AND gate of this bit is connected to the output end of the previous bit AND gate.
The counter according to claim 1, wherein the data alignment module includes a flip-flop, and the data alignment module performs data alignment based on the flip-flop.
The counter according to claim 1, characterized in that:

The sub-counter is an n-bit counter, where n is greater than or equal to 1; each bit in the n-bit counter includes a first flip-flop; the first flip-flop includes a counting input terminal and a counting output terminal; the counting output signal includes the signal of the counting input terminal and/or the signal of the counting output terminal;

The delay unit includes at least one second flip-flop; the second flip-flop uses a clock pulse as a control signal to receive the carry output signal of the previous sub-counter and output the delayed carry output signal to the subsequent sub-counter. Level sub counter;

The data alignment module includes at least one third flip-flop, and the data alignment module performs data alignment based on the third flip-flop;

The data alignment module includes a plurality of lines corresponding to a plurality of the sub-counters, and each line in the plurality of lines receives a counting output signal of a corresponding sub-counter;

For a line among the plurality of lines in which the received counting output signal is a signal at a counting output terminal, the number of the third flip-flops cascaded on the line is equal to the number of sub-counters in the counting module corresponding to the line. The number of second flip-flops to the last sub-counter is equal;

For a line among the plurality of lines in which the received counting output signal is a signal at the counting input end, the number of the third flip-flops cascaded on the line is equal to the number of sub-counters in the counting module corresponding to the line. The number of second flip-flops to the last sub-counter is incremented by one.
The counter according to claim 6, wherein the counting output signal received by the line corresponding to the last stage sub-counter in the counting module among the plurality of lines is the signal of the counting input terminal.
The counter according to claim 7, wherein the counting output signal includes a signal of the counting input terminal and a signal of the counting output terminal; among the plurality of lines, except for the signal corresponding to the last stage sub-counter For lines other than the line, the counting output signal received is the signal at the counting output terminal.
The counter according to claim 1, further comprising a clock module,

The clock module is used to generate a first clock signal and a second clock signal, the counting module operates based on the first clock signal, and the data alignment module operates based on the second clock signal.
The counter according to claim 9, wherein the clock module includes a clock signal input terminal and a first clock generation circuit and a second clock generation circuit connected to the clock signal input terminal; the first clock generation circuit The circuit is used to generate the first clock signal based on the clock signal input by the clock signal input terminal; the second clock generation circuit is used to generate the second clock signal based on the clock signal input by the clock signal input terminal; A delay unit is connected to the first clock generation line and/or the second clock generation line.
The counter of claim 10, wherein at least two delay units are respectively connected to the first clock generation line and the second clock generation line, and the delay unit at the subsequent stage has a fan-out capability of Greater than the fan-out capability of the delay unit located at the previous stage.