CN1321500C - High speed synchronous counter - Google Patents
High speed synchronous counter Download PDFInfo
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- CN1321500C CN1321500C CNB2004100130336A CN200410013033A CN1321500C CN 1321500 C CN1321500 C CN 1321500C CN B2004100130336 A CNB2004100130336 A CN B2004100130336A CN 200410013033 A CN200410013033 A CN 200410013033A CN 1321500 C CN1321500 C CN 1321500C
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Abstract
The present invention relates to a high speed synchronous counter which is provided with a counting signal input wire and n bits of counting stages, wherein n is larger than or equal to 2, and the counting signal input wire is connected to the counting signal input ends of all stages of counters. The present invention is characterized in that each counter is provided with a counting circuit and at least a counting pre-setting device, wherein the counting circuit is provided with at least a counting pre-setting input port, each counting pre-setting device is provided with at least two input ends and at least an output end, the input end of the counting pre-setting device is connected with the output end of the stage of counter and the output ends of the previous counters of the counter, and the output end of the counting pre-setting device is connected with a counting pre-setting input port of the stage of counter; the delay time of the counting pre-setting devices of all the counters is consistent, and the counting pre-setting devices are run parallelly. Therefore, the present invention can has higher counting rate and synchronizing precision for devices with the same speed, and the ranges of counting input signal frequency are wider.
Description
Technical field
The invention belongs to the digital circuit field, a kind of high-speed synchronous counter particularly is provided, it can improve counting rate and synchronization accuracy.
Background technology
Counter commonly used adopts the counting input of the output of previous stage counter as back one-level counter, counters at different levels connect with the form of series connection, the total delay of counter equal counters at different levels delay and, the variation of the state of counters at different levels is nonsynchronous.Such counter is only applicable to counting rate and the less demanding application of counting synchronously, the circuit that its typical circuit adopts as 7493 chips.
United States Patent (USP) 3,943,478 and 4,679,216 output signals that disclose a kind of all previous stages of progression gate make the synchronous binary counter on its input signal that propagates into the back one-level.Yet repeated use at different levels makes the input of NOT-AND gate used in the gate complicated, and this is disadvantageous to the integrated of counter circuit.United States Patent (USP) 4,037,085 has introduced and has a kind ofly monitored that electric currents at different levels determine the counter of state of back one-level.But, make the efficient of operating rate fail satisfactory because of carry signal passes to the partial transmission time from the first order.94118088.3 receive the output signal of previous stage counter and the low level carry signal that low counter produces with a circuit, thereby producing next carry signal is added at least one back one-level counter, carry out the transmission rate of this signal in the electronic circuit of serial transmission operation of a signal to improve the carry signal that produces according to previous stage, its counting rate still can not be fast.
Existing high-speed synchronous counter adopts the control signal of the output of the prime counter of will be correlated with as logic device, the output signal of logic device and the clock signal of incoming line are input to conversion equipment, whether the clock signal pulse of control incoming line can arrive back one-level counter, make back one-level counter status change, list of references sees 96105127.2.96105127.2 the core of high-speed synchronous counter circuit be to adopt the output of prime counter as control signal, whether the clock signal of control incoming line can arrive back one-level counter, controlling object is the clock signal of incoming line.96105127.2 the high-speed synchronous counter circuit because it adopts between at different levels is series system, the output that is the logic device of previous stage will be as the input of the logic device of one-level afterwards, and the output of the logic device of back one-level is relevant with the state of the counter of previous stages.Because each grade logic device all has the regular hour to postpone, the state of the counter of previous stages need just can reach logic device at the corresponding levels through logic devices at different levels, when the frequency of the clock of or incoming line many when number of counter bits is very high, because the delay of logic device, when logic device at the corresponding levels does not also reach due stable state, the clock of incoming line just arrives, and instability or counting loss will appear in counter.The figure place of counter is many more, and the highest count frequency that can reach is just low more.96105127.2 high-speed synchronous counter circuit another one problem be the clock frequency that the performance of its counter depends on incoming line, Fig. 1 be the clock frequency of incoming line when being 5MHz embodiment 1 and each digit counter output waveform of embodiment 2; Fig. 2 be the clock frequency of incoming line when being 50MHz embodiment 1 and each digit counter output waveform of embodiment 2; Fig. 3 be the clock frequency of incoming line when being 100MHz embodiment 1 and each digit counter output waveform of embodiment 2.Fin is the clock waveform of incoming line among the figure, and Q1 is the output waveform of counter 1, and q2 is the output waveform of counter 2, and Q3 is the output waveform of counter 3, and Q4 is the output waveform of counter 4, and Q5 is the output waveform of counter 5.As seen from Figure 1, when the clock frequency of incoming line was not high, this scheme had lost the function of counting, and the delay of the variation of the state of counters at different levels.As seen from Figure 2, when the clock frequency of incoming line was higher, the output of second counter of this scheme was not expectation state.As seen from Figure 3, when the clock frequency of incoming line in suitable scope, the output of the counter of this scheme is only expectation state.
96105127.2 the problem of high-speed synchronous counter circuit be summarized as follows:
The count status serial transfer, when counter progression for a long time, total delay time is longer; The clock frequency of incoming line can only be in certain scope, can not be too high, can not be too low, and this frequency range depends on the speed of circuit devcie, the frequency range of the device of friction speed is different; The synchronizing speed of each rolling counters forward is lower.This counter can not be applicable to high-speed counting, and the application of reading at a high speed, as high-speed timer.The application that the clock pulse interval that this counter can not be used for incoming line changes at relative broad range is as timer at random.
Summary of the invention
Purpose of the present invention is exactly for solving the problem that the above-mentioned background technology exists, adopt new counting scheme, a kind of high-speed synchronous counter that can adapt to the reference clock frequency of wideer incoming line being provided.
Technical scheme of the present invention is: a kind of high-speed synchronous counter, have count signal incoming line and n position counting stage, n 〉=2, the count signal incoming line is connected to the count signal input of described counters at different levels, it is characterized in that: all have a counting circuit and at least one counting presetter device in every digit counter, counting circuit has at least one counting and presets the input port, each counting presetter device has at least two inputs and at least one output, the counting presetter device comprises at least one AND circuit, at least one OR circuit or at least one not circuit, the input of the AND circuit in the counting presetter device is connected with the output of counter, the output of the AND circuit of counting in the presetter device is connected with the input of OR circuit in counting presetter device, count the output connection count circuit input end of the OR circuit in the presetter device or pass through not circuit connection count circuit input end, the input of counting presetter device is connected with the output of counter at the corresponding levels and the output of its whole prime counters, and the counting of the output termination counter at the corresponding levels of counting presetter device presets the input port.
Aforesaid high-speed synchronous counter, it is characterized in that the current output state of described counter at different levels, before next count signal incoming line signal is effective, be input to the counting presetter device of corresponding counter, the counting presetter device according to input produce corresponding counter when next count signal incoming line signal is effective the state that should export.
Aforesaid high-speed synchronous counter is characterized in that the output state of described counting presetter device when next count signal incoming line signal is effective, being placed in the output of counter at the corresponding levels.
Aforesaid high-speed synchronous counter is characterized in that described counting presetter device is made up of logical circuit, and logical circuit comprises at least one AND circuit or at least one OR circuit;
Aforesaid high-speed synchronous counter is characterized in that:
Described high-speed synchronous counter can carry out the above-mentioned counter of polylith cascade and form longer counter;
An input of the counting presetter device of the first order counter of a back counter block of cascade links to each other with the counting presetter device of the afterbody counter of the last counter block of cascade, and its another input links to each other with the output of the last counter block afterbody counter of cascade.
High-speed synchronous counter of the present invention comprises the count signal incoming line, in order to input counting input signal; At least two-stage counting unit is in order to produce the multidigit count value according to the counting input signal; Counting units at different levels all have a counter and a counting presetter device; Counting presets the input port in order to the low level counting stage unit in the prset counter, the output state when next one counting input signal is effective.
The counting of the counter of counting units at different levels presets the counting presetter device that the input port connects, and according to the output state of each counter of this digit counter and its high position, produces the preset condition of next counting input signal this digit counter when effective.When next one counting input signal was effective, each digit counter was changed to the output state of this digit counter the state that the counting presetter device of this digit counter presets simultaneously.After this count status of each digit counter is stable, the counting of each digit counter presets the counting presetter device that the input port connects, according to the output state of each counter of the high position of this current digit counter and it, the output that produces the counting presetter device of this new digit counter.
Because the output state of each counter is just to have preset before the counting input signal is effective, so when the counting input signal was effective, each digit counter can be realized the conversion of output state simultaneously.Be consistent the time of delay of the counting presetter device of each digit counter, and be parallel running, so device for same speed, the present invention can reach higher counting rate and synchronization accuracy, and the counting input signal frequency range is wideer, and what can be used for counting input signal is at random application at interval.
The present invention at most can direct-connected number of counter bits, depends on the load driving ability of counter output, the counting presetter device number that promptly can drive.For the more counter application of long number, can adopt cascade system to be expanded.The total delay time of the counting presetter device that expansion connects than the preceding block count presetter device of cascade time of delay the one-level of manying gate circuit time of delay.
, and, be described further principle of the present invention and characteristic below in conjunction with embodiment for the application of cascade expansion and the influence of delay.
Description of drawings:
Fig. 1: each digit counter output waveform of 96105127.2 embodiment 1 and embodiment 2 when the clock frequency of incoming line is 5MHz;
Fig. 2: each digit counter output waveform of 96105127.2 embodiment 1 and embodiment 2 when the clock frequency of incoming line is 50MHz;
Fig. 3: each digit counter output waveform of 96105127.2 embodiment 1 and embodiment 2 when the clock frequency of incoming line is 100MHz;
Fig. 4: the circuit diagram of the embodiment of the invention 1;
Fig. 5: the circuit diagram of the embodiment of the invention 2;
Fig. 6: the circuit diagram of the embodiment of the invention 3;
Embodiment
Fig. 4 is the circuit diagram of the preferred embodiment of the present invention, and counting input signal 1 is connected to the input end of clock of six digit counter 2-7.Constitute the counting presetter device with door 10,15,20,25,30,35 and XOR gate 13,18,23,28,33,38.The output 12,17,22,27,32,37 of counter is with the state output of each digit counter.
Be connected to the output 12 of counter 2 with two inputs of door 15.The output 19 of XOR gate 18 depend on counter 3 output 17 and with the output 16 of door 15.When the output 17 of counter 3 when identical with the output 16 of door 15, the output 19 of XOR gate 18 is low level; When the output 17 of counter 3 with the output 16 of door 15 when inequality, the output 19 of XOR gate 18 is high level.Counter 3 effectively the time, is changed to the output 17 of counter 3 state of the output 19 of XOR gate 18 at counting input signal 1.
Be connected to the output 12 of counter 2 with an input of door 20, another input is connected to the output 17 of counter 3.The output 24 of XOR gate 23 depend on counter 4 output 22 and with the output 21 of door 20.When the output 22 of counter 4 when identical with the output 21 of door 20, the output 24 of XOR gate 28 is low level; When the output 22 of counter 4 with the output 21 of door 20 when inequality, the output 24 of XOR gate 23 is high level.Counter 4 effectively the time, is changed to the output 22 of counter 4 state of the output 24 of XOR gate 23 at counting input signal 1.
12, one inputs of output that are connected to counter 2 with an input of door 25 are connected to the output 17 of counter 3, and another input is connected to the output 22 of counter 4.The output 29 of XOR gate 28 depend on counter 5 output 27 and with the output 26 of door 25.When the output 27 of counter 5 when identical with the output 26 of door 25, the output 29 of XOR gate 28 is low level; When the output 27 of counter 5 with the output 26 of door 25 when inequality, the output 29 of XOR gate 28 is high level.Counter 5 effectively the time, is changed to the output 27 of counter 5 state of the output 29 of XOR gate 28 at counting input signal 1.
17, one inputs of output that 12, one inputs of output that are connected to counter 2 with an input of door 30 are connected to counter 3 are connected to the output 22 of counter 4, and another input is connected to the output 27 of counter 5.The output 34 of XOR gate 33 depend on counter 6 output 32 and with the output 31 of door 30.When the output 32 of counter 6 when identical with the output 31 of door 30, the output 34 of XOR gate 33 is low level; When the output 32 of counter 6 with the output 31 of door 30 when inequality, the output 34 of XOR gate 33 is high level.Counter 6 effectively the time, is changed to the output 32 of counter 6 state of the output 34 of XOR gate 33 at counting input signal 1.
Be connected to the output 12 of counter 2 with an input of door 35, an input is connected to the output 17 of counter 3, an input is connected to the output 22 of counter 4, an input is connected to the output 27 of counter 5, and another input is connected to the output 32 of counter 6.The output 39 of XOR gate 38 depend on counter 7 output 37 and with the output 36 of door 35.When the output 37 of counter 7 when identical with the output 36 of door 35, the output 39 of XOR gate 38 is low level; When the output 37 of counter 7 with the output 36 of door 35 when inequality, the output 39 of XOR gate 38 is high level.Counter 7 effectively the time, is changed to the output 37 of counter 7 state of the output 39 of XOR gate 38 at counting input signal 1.
Because the restriction of the driving force of counter output, the figure place of counter can not be oversize, when the needs long counter, can adopt polylith counter of the present invention to carry out cascade.Counter 2 is during as back of the cascade of long counter the first order, back and the input 8 or 9 door 10 of cascade is connected to the output 37 of the preceding block counter 7 of cascade, and the back and input 9 or 8 door 10 of cascade is connected to the output 36 of preceding piece with the door 35 of cascade.
The high-speed synchronous counter of present embodiment, in general, have count signal incoming line and n position counting stage, n 〉=2, the count signal incoming line is connected to the count signal input of described counters at different levels, it is characterized in that: have n-1 low counter in the n digit counter, n-1 counting presets input port and n-1 counting presetter device, the input of counting presetter device is connected with the output of counter at the corresponding levels and the logical that is output into of its whole prime counters, and the counting of the output termination counter at the corresponding levels of counting presetter device presets the input port.
Fig. 5, Fig. 6 showed that the present invention counts presetter device other be equal to the logical circuit scheme.Only provided the variation of one-level among the figure, other are at different levels all can to duplicate.
Fig. 5 is the circuit diagram of the embodiment of the invention 2, and counting input signal 40 is connected to the input end of clock of five digit counter 41-45.With door 48,55,59,64,69,74, XOR gate 51,67,72,77, not gate 53,57 and or door 61 formation counting presetter devices.The output 50,63,66,71,76 of counter is with the state output of each digit counter.
Counter 41 is during as the first order of whole counter, is changed to high level with two inputs 46 and 47 of door 48, and its output 49 is always high level.The output 52 of XOR gate 51 depend on counter 41 output 50 and with the output 49 of door 48.When the output 50 of counter 41 when identical with the output 49 of door 48, the output 52 of XOR gate 51 is low level; When the output 50 of counter 41 with the output 49 of door 48 when inequality, the output 52 of XOR gate 51 is high level.Counter 41 effectively the time, is changed to the output 50 of counter 41 state of the output 52 of XOR gate 51 at counting input signal 40.
Be connected to the output 54 of not gate 53 with an input of door 55, the input of not gate 53 is connected to the output 50 of counter 41; Be connected to the output 63 of counter 42 with another input of door 55.Be connected to the output 58 of not gate 57 with an input of door 59, the input of not gate 57 is connected to the output 63 of counter 42; Be connected to the output 50 of counter 41 with another input of door 59.Or door 61 output 62 be with the output 56 of door 55 and with the output 60 of door 59 or the result.Counter 42 is at counting input signal 40 effectively the time, the output 63 of counter 42 is changed to or the state of the output 62 of door 61.
Be connected to the output 50 of counter 41 with an input of door 64, another input is connected to the output 63 of counter 42.The output 68 of XOR gate 67 depend on counter 43 output 66 and with the output 65 of door 64.When the output 66 of counter 43 when identical with the output 65 of door 64, the output 68 of XOR gate 67 is low level; When the output 66 of counter 43 with the output 65 of door 64 when inequality, the output 68 of XOR gate 67 is high level.Counter 43 effectively the time, is changed to the output 66 of counter 43 state of the output 68 of XOR gate 67 at counting input signal 40.
50, one inputs of output that are connected to counter 41 with an input of door 69 are connected to the output 63 of counter 42, and another input is connected to the output 66 of counter 43.The output 73 of XOR gate 72 depend on counter 44 output 71 and with the output 70 of door 69.When the output 71 of counter 44 when identical with the output 70 of door 69, the output 73 of XOR gate 72 is low level; When the output 71 of counter 44 with the output 70 of door 69 when inequality, the output 73 of XOR gate 72 is high level.Counter 44 effectively the time, is changed to the output 71 of counter 44 state of the output 73 of XOR gate 72 at counting input signal 40.
63, one inputs of output that 50, one inputs of output that are connected to counter 41 with an input of door 74 are connected to counter 42 are connected to the output 66 of counter 43, and another input is connected to the output 71 of counter 44.The output 78 of XOR gate 77 depend on counter 45 output 76 and with the output 75 of door 74.When the output 76 of counter 45 when identical with the output 75 of door 74, the output 78 of XOR gate 77 is low level; When the output 76 of counter 45 with the output 75 of door 74 when inequality, the output 78 of XOR gate 77 is high level.Counter 45 effectively the time, is changed to the output 76 of counter 45 state of the output 78 of XOR gate 77 at counting input signal 40.
Because the restriction of the driving force of counter output, the figure place of counter can not be oversize, when the needs long counter, can adopt polylith counter of the present invention to carry out cascade.Counter 41 is during as back of the cascade of long counter the first order, back and the input 46 or 47 door 48 of cascade is connected to the output 76 of the preceding block counter 45 of cascade, and the back and input 47 or 46 door 48 of cascade is connected to the output 75 of preceding piece with the door 74 of cascade.
Fig. 6 is the circuit diagram of the embodiment of the invention 3, and counting input signal 79 is connected to the input end of clock of five digit counter 80-84.With door 88,97,98,104,109,114, XOR gate 91,107,112,117, not gate 93,94 and NOR gate 101 constitute the counting presetter device.The output 90,92,106,111,116 of counter is with the state output of each digit counter.
Counter 80 is during as the first order of whole counter, is changed to high level with two inputs 86 and 87 of door 88, and its output 85 is always high level.The output 89 of XOR gate 91 depend on counter 80 output 90 and with the output 85 of door 88.When the output 90 of counter 80 when identical with the output 85 of door 88, the output 89 of XOR gate 91 is low level; When the output 90 of counter 80 with the output 85 of door 88 when inequality, the output 89 of XOR gate 91 is high level.Counter 80 effectively the time, is changed to the output 90 of counter 80 state of the output 89 of XOR gate 91 at counting input signal 79.
Be connected to the output 90 of counter 80 with two inputs of door 15.The output 19 of XOR gate 18 depend on counter 81 output 92 and with the output 16 of door 15.When the output 92 of counter 81 when identical with the output 16 of door 15, the output 19 of XOR gate 18 is low level; When the output 92 of counter 81 with the output 16 of door 15 when inequality, the output 19 of XOR gate 18 is high level.Counter 81 effectively the time, is changed to the output 92 of counter 81 state of the output 19 of XOR gate 18 at counting input signal 1.
Be connected to the output 90 of counter 80 with an input of door 104, another input is connected to the output 92 of counter 81.The output 103 of XOR gate 107 depend on counter 82 output 106 and with the output 105 of door 104.When the output 106 of counter 82 when identical with the output 105 of door 104, the output 103 of XOR gate 107 is low level; When the output 106 of counter 82 with the output 105 of door 104 when inequality, the output 103 of XOR gate 107 is high level.Counter 82 effectively the time, is changed to the output 106 of counter 82 state of the output 103 of XOR gate 107 at counting input signal 79.
90, one inputs of output that are connected to counter 80 with an input of door 109 are connected to the output 92 of counter 81, and another input is connected to the output 106 of counter 82.The output 108 of XOR gate 112 depend on counter 83 output 111 and with the output 110 of door 109.When the output 111 of counter 83 when identical with the output 110 of door 109, the output 108 of XOR gate 112 is low level; When the output 111 of counter 83 with the output 110 of door 109 when inequality, the output 108 of XOR gate 112 is high level.Counter 83 effectively the time, is changed to the output 111 of counter 83 state of the output 108 of XOR gate 112 at counting input signal 79.
92, one inputs of output that 90, one inputs of output that are connected to counter 80 with an input of door 114 are connected to counter 81 are connected to the output 106 of counter 82, and another input is connected to the output 111 of counter 83.The output 113 of XOR gate 117 depend on counter 84 output 116 and with the output 115 of door 114.When the output 116 of counter 84 when identical with the output 115 of door 114, the output 113 of XOR gate 117 is low level; When the output 116 of counter 84 with the output 115 of door 114 when inequality, the output 113 of XOR gate 117 is high level.Counter 84 effectively the time, is changed to the output 116 of counter 84 state of the output 113 of XOR gate 117 at counting input signal 79.
Because the restriction of the driving force of counter output, the figure place of counter can not be oversize, when the needs long counter, can adopt polylith counter of the present invention to carry out cascade.Counter 80 is during as back of the cascade of long counter the first order, back and the input 86 or 87 door 88 of cascade is connected to the output 116 of the preceding block counter 84 of cascade, and the back and input 87 or 86 door 88 of cascade is connected to the output 115 of preceding piece with the door 114 of cascade.
When carrying out cascade, every increase one-level connection counter block, the output of the counting presetter device of the back block counter of cascade is than the time of delay of the late AND circuit of output of the counting presetter device of the preceding block counter of cascade.Even so, counting rate of the present invention also will be higher than the method in the background technology, and the synchronization accuracy of whole counter also will be higher than the method in the background technology, helps high-speed counting like this and reads the application of count value at a high speed, as high-speed timer.
Claims (8)
1. high-speed synchronous counter, have count signal incoming line and n position counting stage, n 〉=2, the count signal incoming line is connected to the count signal input of described counters at different levels, it is characterized in that: all have a counting circuit and at least one counting presetter device in every digit counter, counting circuit has at least one counting and presets the input port, each counting presetter device has at least two inputs and at least one output, the counting presetter device comprises at least one AND circuit, at least one OR circuit or at least one not circuit, the input of the AND circuit in the counting presetter device is connected with the output of counter, the output of the AND circuit of counting in the presetter device is connected with the input of OR circuit in counting presetter device, count the output connection count circuit input end of the OR circuit in the presetter device or pass through not circuit connection count circuit input end, the input of counting presetter device is connected with the output of counter at the corresponding levels and the output of its whole prime counters, and the counting of the output termination counter at the corresponding levels of counting presetter device presets the input port.
2, according to the described high-speed synchronous counter of claim 1, it is characterized in that the current output state of described counter at different levels, before next count signal incoming line signal is effective, be input to the counting presetter device of corresponding counter, the counting presetter device according to input produce corresponding counter when next count signal incoming line signal is effective the state that should export.
3, high-speed synchronous counter according to claim 1 and 2 is characterized in that the output state of described counting presetter device when next count signal incoming line signal is effective, being placed in the output of counter at the corresponding levels.
4, high-speed synchronous counter according to claim 1 and 2 is characterized in that described counting presetter device is made up of logical circuit, and logical circuit comprises at least one AND circuit or at least one OR circuit.
5, high-speed synchronous counter according to claim 3 is characterized in that described counting presetter device is made up of logical circuit, and logical circuit comprises at least one AND circuit or at least one OR circuit.
6, according to claim 1 or 2 or 5 described high-speed synchronous counters, it is characterized in that:
Described high-speed synchronous counter can carry out the above-mentioned counter of polylith cascade and form longer counter;
An input of the counting presetter device of the first order counter of a back counter block of cascade links to each other with the counting presetter device of the afterbody counter of the last counter block of cascade, and its another input links to each other with the output of the last counter block afterbody counter of cascade.
7, high-speed synchronous counter according to claim 3 is characterized in that:
Described high-speed synchronous counter can carry out the above-mentioned counter of polylith cascade and form longer counter;
An input of the counting presetter device of the first order counter of a back counter block of cascade links to each other with the counting presetter device of the afterbody counter of the last counter block of cascade, and its another input links to each other with the output of the last counter block afterbody counter of cascade.
8, high-speed synchronous counter according to claim 4 is characterized in that:
Described high-speed synchronous counter can carry out the above-mentioned counter of polylith cascade and form longer counter;
An input of the counting presetter device of the first order counter of a back counter block of cascade links to each other with the counting presetter device of the afterbody counter of the last counter block of cascade, and its another input links to each other with the output of the last counter block afterbody counter of cascade.
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| CNB2004100130336A CN1321500C (en) | 2004-04-14 | 2004-04-14 | High speed synchronous counter |
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| CNB2004100130336A CN1321500C (en) | 2004-04-14 | 2004-04-14 | High speed synchronous counter |
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| CN1564463A CN1564463A (en) | 2005-01-12 |
| CN1321500C true CN1321500C (en) | 2007-06-13 |
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| CN102609317B (en) * | 2012-01-13 | 2014-05-14 | 从兴技术有限公司 | Semaphore processing method and semaphore processing system |
| CN102901871B (en) * | 2012-08-30 | 2015-02-04 | 河南科技大学 | Signal frequency detection system and method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3943478A (en) * | 1974-12-18 | 1976-03-09 | Therm-O-Disc Incorporated | Adjustable thermostat |
| US4037085A (en) * | 1975-08-27 | 1977-07-19 | Hitachi, Ltd. | Counter |
| EP0212589A2 (en) * | 1985-08-19 | 1987-03-04 | Kabushiki Kaisha Toshiba | Synchronous binary counter |
| CN1088941C (en) * | 1993-11-08 | 2002-08-07 | 三星电子株式会社 | synchronous binary counter |
| CN1094270C (en) * | 1995-05-15 | 2002-11-13 | 现代电子产业株式会社 | High-speed counter circuit |
-
2004
- 2004-04-14 CN CNB2004100130336A patent/CN1321500C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3943478A (en) * | 1974-12-18 | 1976-03-09 | Therm-O-Disc Incorporated | Adjustable thermostat |
| US4037085A (en) * | 1975-08-27 | 1977-07-19 | Hitachi, Ltd. | Counter |
| EP0212589A2 (en) * | 1985-08-19 | 1987-03-04 | Kabushiki Kaisha Toshiba | Synchronous binary counter |
| CN1088941C (en) * | 1993-11-08 | 2002-08-07 | 三星电子株式会社 | synchronous binary counter |
| CN1094270C (en) * | 1995-05-15 | 2002-11-13 | 现代电子产业株式会社 | High-speed counter circuit |
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