CN107733426B - Voter with hysteresis function and design method thereof - Google Patents
Voter with hysteresis function and design method thereof Download PDFInfo
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- CN107733426B CN107733426B CN201711089104.4A CN201711089104A CN107733426B CN 107733426 B CN107733426 B CN 107733426B CN 201711089104 A CN201711089104 A CN 201711089104A CN 107733426 B CN107733426 B CN 107733426B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
Abstract
The invention discloses a voter with a hysteresis function and a design method thereof, which are used in a receiving end of a high-speed serial port communication system. The design method obtains a statistical result by counting voting results of the first 3 moments of the current moment, and generates a voting result of the current moment by using the statistical result and the 10-bit input of the current moment to jointly participate in voting operation. The voter with the hysteresis function comprises 3 delay DFFs and 9 full adders, and judges whether the timing relation of the serial data and the sampling clock is advanced or lagged according to a minority majority principle. The invention can further resist noise interference, especially instantaneous noise interference with large burst, thereby improving communication quality.
Description
Technical Field
The invention relates to a voter with a hysteresis function for a receiving end of a high-speed serial port communication system and a design method thereof, belonging to the technical field of integrated circuits in high-speed communication.
Background
A high-speed serial communication system includes a transmitter, a channel, and a receiver. The transmitter converts low speed parallel data to high speed serial data for transmission onto the channel. The channel attenuates the data and adds noise. The receiver (as shown in fig. 1) performs edge sampling on jittered serial data according to a serial clock CLK _ I, performs intermediate sampling on the jittered serial data by CLK _ Q, performs serial/parallel conversion and phase discrimination on the sampled data to output a 10-bit data stream (lead/lag), the voter votes the 10-bit lead/lag data under the minority majority principle to generate a one-bit lead/lag signal, and the filter filters the output of the voter and controls and adjusts the clock phases CLK _ I, CLK _ Q and CLK.
Because the received data are disturbed and the phases of the received data are randomly shifted left and right relative to the phase of the sampling clock CLK _ I, CLK _ Q, errors can occur in the sampled data, the voter reduces the error rate according to the minority-obeying majority principle, and because 8b/10b coding is widely applied to high-speed serial communication, the working principle is described by taking 10 bits as an example. A logic "1" represents a data transition edge leading the sampling clock transition edge, and a logic "0" represents a data transition edge lagging the sampling clock transition edge. In order to realize the correspondence relationship in accordance with the majority rule in a minority case, as shown in table 1 and (a) and (b) of fig. 2, when the number of inputs "1" is 6 or more, "1" is output, "0" is output when the number of inputs "1" is 4 or less, and when the number of inputs "1" is 5, "1" or "0" is output.
TABLE 1 conventional 10-bit input-1-bit output correspondence
When sampling is approximately stable, the transition edge of the serial data and the transition edge of the sampling clock are basically aligned, and the sampling clock edge and the data edge are not aligned due to the sudden large interference, so that error data is sampled, namely, the output data 1 outputs 0, and the output data 0 outputs 1. Wrong data can lead to wrong phase discrimination results (the input of the voter has wrong data), and although the voter adopts a minority obeys a majority principle, the possibility of errors cannot be completely eliminated, particularly when the input number of '1' is about 5.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the voter with the hysteresis function is optimally designed to overcome the defect of sudden instantaneous large interference, and the voter with the hysteresis function is adopted to further enhance the anti-interference capability.
The invention adopts the following technical scheme for solving the technical problems:
a design method of a voter with a hysteresis function comprises 10-bit input and 1-bit output, voting results at t-3, t-2 and t-1 moments are counted to obtain a statistical result, and the statistical result and the 10-bit input at the current moment t are jointly used for participating in voting operation to generate a voting result at the current moment t;
the voting results at the moments of t-3, t-2 and t-1 are counted to obtain a statistical result, and the method comprises the following steps: delaying the voting result at the t-3 moment by 3 clock cycles, delaying the voting result at the t-2 moment by 2 clock cycles, delaying the voting result at the t-1 moment by 1 clock cycle, and simultaneously sending the delayed three voting results to statistics at the t moment to obtain a statistical result;
and (3) jointly participating in voting operation by utilizing the statistical result and the 10-bit input of the current moment t to generate a voting result of the current moment t, wherein the method comprises the following steps: and (3) adopting a minority majority-compliant principle to generate a voting result at the current moment, namely outputting '0' when the number of input '0' is greater than that of input '1' and outputting '1' when the number of input '1' is greater than that of input '0' in the statistical result and 10-bit input.
A voter with hysteresis function comprises first to ninth full adders and first to third delay units, wherein each full adder comprises 1 to 3 th input ends, 1 carry output end and 1 summation output end, and each delay unit comprises an input end, a clock and an output end; the carry output end of the first full adder is connected with the 3 rd input end of the seventh full adder, the carry output end of the second full adder is connected with the 3 rd input end of the fifth full adder, the sum output end of the second full adder is connected with the 3 rd input end of the sixth full adder, the carry output end of the third full adder is connected with the 2 nd input end of the fifth full adder, the sum output end of the third full adder is connected with the 2 nd input end of the sixth full adder, the carry output end of the fourth full adder is connected with the 1 st input end of the fifth full adder, the sum output end of the fourth full adder is connected with the 1 st input end of the sixth full adder, the carry output end of the fifth full adder is connected with the 3 rd input end of the eighth full adder, the sum output end of the fifth full adder is connected with the 2 nd input end of the seventh full adder, the carry output end of the sixth full adder is connected with the 1 st input end of the seventh full adder, the carry output end of the seventh full adder is connected with the 2 nd input end of the eighth full adder, the 1 st input of eighth full adder is connected to the summation output of seventh full adder, the input of first delay unit is connected to the carry output of eighth full adder, the input of second delay unit, the 3 rd input of ninth full adder is connected to the output of first delay unit, the input of third delay unit, the 2 nd input of ninth full adder is connected to the output of second delay unit, the 1 st input of ninth full adder is connected to the output of third delay unit, the 3 rd input of first full adder is connected to the carry output of ninth full adder.
As a preferred embodiment of the voter of the present invention, the first to third delay units are all D flip-flops.
As a preferred solution of the voter of the present invention, the length of the delay chain of the D flip-flop is 3.
As a preferred scheme of the voter of the present invention, when the input of the 3 rd input terminal of the first full adder is "1", and the number of input "1" in the 10 th input of the voter is less than or equal to 4, the carry output terminal of the eighth full adder outputs "0"; when the input of the 3 rd input end of the first full adder is 0, the carry output end of the eighth full adder outputs 1 when the number of input 1 in10 bit inputs of the voter is more than or equal to 6.
Compared with the prior art, the invention adopting the technical scheme has the following technical effects:
the invention provides an optimization design aiming at the defect that the voter deals with sudden and large instantaneous interference, the voting output OUT _ FB at the first 3 moments and the input IN 1-IN 10 at the current moment are jointly used for voting operation and generating the output OUT at the current moment, and the voter with the hysteresis function designed by the design method can further resist noise interference, particularly sudden and large instantaneous noise interference, thereby improving the communication quality.
Drawings
Fig. 1 is a schematic diagram of a receiver in a high-speed serial communication system.
FIG. 2 is a corresponding relationship of conventional 10-bit input-1-bit output, wherein (a) indicates that the output is 1 when the number of input 1 is 5; (b) when the number of the input 1 is 5, the output is 0.
FIG. 3 is a schematic diagram of the voter with hysteresis function according to the present invention.
FIG. 4 shows the input-output correspondence of the voter with hysteresis according to the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
Since the noise is approximately gaussian distribution at random, under the noise interference, the probability that the number of input "1" is changed from 4 to 5, from 5 to 4, from 5 to 6, from 6 to 5 is much greater than the probability that the number is changed from 4 to 6, from 6 to 4. The invention provides an optimization design aiming at the defect that the voter deals with sudden instantaneous large interference, and adopts the voter with a hysteresis function to further enhance the anti-interference capability.
As shown in fig. 3, a schematic structural diagram of the voter with hysteresis function of the present invention includes 9 full adders, where A3-a 1 of the full adders are 3 inputs, CO is carry output, SUM is SUM output, SUM is "0" and CO is "0" representing that 0 inputs of A3-a 1 are "1", SUM is "1" and CO is "0" representing that 1 input of A3-a 1 is "1", SUM is "0" and CO is "1" representing that 2 inputs of A3-a 1 are "1", SUM is "1" and CO is "1" representing that 3 inputs of A3-a 1 are "1".
Fig. 3 also includes 3 DFFs, which are D flip-flops, input data D and a clock CLK, and output data Q.
The inputs IN 1-IN 10 total 10 bits, OUT is a 1-bit output, OUT 1-OUT 3 generate OUT _ FB. That is, the voting output OUT _ FB at the first 3 times and the current time inputs IN1 to IN10 jointly participate IN the voting operation and generate the current time output OUT. A logic "1" represents a transition edge of data leading a sampling clock transition edge; a logic "0" represents a data transition edge lagging the sampling clock transition edge. The operation rule of the voter is shown in table 2: outputting "0" (not easily jumping to lag) when OUT _ FB is "1" (preceding result is leading) the current judgment tends to lead outputting "1", that is, the number of inputs "1" is less than or equal to 4; when OUT _ FB is "0" (the previous result is lagging), the current judgment tends to lag and output "0", and "1" is output (not easy to jump to advance) when the number of input "1" is more than or equal to 6, as shown in FIG. 4, the input and output relationship of the hysteresis voter can be clearly seen.
TABLE 2 truth table of voter input-output with hysteresis
The specific operation is as follows: the summation operation results in the first column of X1, X2, and X3 being "1" represents that 1 input is "1", and X4, X5, X6, and X7 being "1" represents that 2 inputs are "1"; the second column X8, X9 being "1" means that there are 2 inputs being "1", X12 being "1" means that there are 4 inputs being "1"; a third column X10 of "1" represents 2 inputs of "1", and X11 of "1" represents 4 inputs of "1"; a fourth column OUT of "1" represents at least 6 inputs of "1". The method comprises the steps that OUT is sent to a shift register chain consisting of DFFs and outputs OUT 1-OUT 3, the OUT is delayed for one CLK period to obtain OUT1, the OUT1 is delayed for one CLK period to obtain OUT2, and the OUT2 is delayed for one CLK period to obtain OUT 3. OUT is the voting result at the current time t, OUT1 is the voting result at the time t-1, OUT2 is the voting result at the time t-2, and OUT3 is the voting result at the time t-3. OUT _ FB is the statistical effect of the voting results (OUT1 OUT3) at the three moments before OUT (at least 2 voting values are "1", then OUT _ FB is "1").
FIG. 3 provides a voter with an input bit output of 10 bits, and in practice, the circuit can be modified appropriately to implement a voter with more or less than 10 bits.
The DFF in fig. 3 provides a delay chain, and other delay units may be used in actual use, and the length of the delay chain may be set as required, and is set to 3 in the present invention.
The OUT _ FB in FIG. 3 can also be processed by other means such as adding or subtracting counters to obtain the previous voting results to obtain the current correct lead/lag signal.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention.
Claims (5)
1. A design method of a voter with a hysteresis function is characterized in that the voter comprises 10-bit input and 1-bit output, voting results at t-3, t-2 and t-1 moments are counted to obtain a statistical result, the statistical result and the 10-bit input at the current moment t are jointly used for participating in voting operation, and a voting result at the current moment t is generated;
the voting results at the moments of t-3, t-2 and t-1 are counted to obtain a statistical result, and the method comprises the following steps: delaying the voting result at the moment t-3 by 3 clock cycles, delaying the voting result at the moment t-2 by 2 clock cycles, delaying the voting result at the moment t-1 by 1 clock cycle, and simultaneously sending the delayed three voting results to a full adder at the moment t for statistics to obtain a carry output statistical result;
the statistical result of carry output and 10-bit input of the current time t are used for jointly participating in voting operation to generate a voting result of the current time t, and the method comprises the following steps: and (3) adopting a minority majority-obeying principle to generate a voting result at the current moment, namely voting the carry output statistical result and the 10-bit input as a whole, outputting the '0' when the number of the input '0' is greater than that of the input '1', and outputting the '1' when the number of the input '1' is greater than that of the input '0'.
2. A voter with a hysteresis function is characterized by comprising first to ninth full adders and first to third delay units, wherein each full adder comprises 1 to 3 th input ends, 1 carry output end and 1 summation output end, and each delay unit comprises an input end, a clock and an output end; the carry output end of the first full adder is connected with the 3 rd input end of the seventh full adder, the carry output end of the second full adder is connected with the 3 rd input end of the fifth full adder, the sum output end of the second full adder is connected with the 3 rd input end of the sixth full adder, the carry output end of the third full adder is connected with the 2 nd input end of the fifth full adder, the sum output end of the third full adder is connected with the 2 nd input end of the sixth full adder, the carry output end of the fourth full adder is connected with the 1 st input end of the fifth full adder, the sum output end of the fourth full adder is connected with the 1 st input end of the sixth full adder, the carry output end of the fifth full adder is connected with the 3 rd input end of the eighth full adder, the sum output end of the fifth full adder is connected with the 2 nd input end of the seventh full adder, the carry output end of the sixth full adder is connected with the 1 st input end of the seventh full adder, the carry output end of the seventh full adder is connected with the 2 nd input end of the eighth full adder, the 1 st input of eighth full adder is connected to the summation output of seventh full adder, the input of first delay unit is connected to the carry output of eighth full adder, the input of second delay unit, the 3 rd input of ninth full adder is connected to the output of first delay unit, the input of third delay unit, the 2 nd input of ninth full adder is connected to the output of second delay unit, the 1 st input of ninth full adder is connected to the output of third delay unit, the 3 rd input of first full adder is connected to the carry output of ninth full adder.
3. A voter having a hysteresis function according to claim 2, wherein the first to third delay units are D flip-flops.
4. A voter having hysteresis as defined in claim 3, wherein the length of the D flip-flop delay chain is 3.
5. A voter having a hysteresis function as defined in claim 2, wherein when the input of the 3 rd input terminal of the first full adder is "1", and the number of inputs "1" in the 10 th inputs of the voter is not more than 4, the carry output terminal of the eighth full adder outputs "0"; when the input of the 3 rd input end of the first full adder is 0, the carry output end of the eighth full adder outputs 1 when the number of input 1 in10 bit inputs of the voter is more than or equal to 6.
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| US6118297A (en) * | 1997-12-23 | 2000-09-12 | Texas Instruments Incorporated | Voting circuit and method |
| CN103117773A (en) * | 2013-01-24 | 2013-05-22 | 厦门大学深圳研究院 | Chaos ultra wide brand traffic flow collection system utilizing terminal cooperation and collection method |
| CN103326711A (en) * | 2013-06-17 | 2013-09-25 | 天津大学 | Anti-radiation hardening latch based on TMR and DICE |
| US8896476B2 (en) * | 2013-01-25 | 2014-11-25 | Technische Universiteit Eindhoven | Data-driven noise reduction technique for analog to digital converters |
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2017
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Patent Citations (4)
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|---|---|---|---|---|
| US6118297A (en) * | 1997-12-23 | 2000-09-12 | Texas Instruments Incorporated | Voting circuit and method |
| CN103117773A (en) * | 2013-01-24 | 2013-05-22 | 厦门大学深圳研究院 | Chaos ultra wide brand traffic flow collection system utilizing terminal cooperation and collection method |
| US8896476B2 (en) * | 2013-01-25 | 2014-11-25 | Technische Universiteit Eindhoven | Data-driven noise reduction technique for analog to digital converters |
| CN103326711A (en) * | 2013-06-17 | 2013-09-25 | 天津大学 | Anti-radiation hardening latch based on TMR and DICE |
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