CN111786865B - Data processing method and equipment - Google Patents
Data processing method and equipment Download PDFInfo
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- CN111786865B CN111786865B CN202010518291.9A CN202010518291A CN111786865B CN 111786865 B CN111786865 B CN 111786865B CN 202010518291 A CN202010518291 A CN 202010518291A CN 111786865 B CN111786865 B CN 111786865B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
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Abstract
The invention discloses a data processing method and equipment, which comprises the steps of firstly obtaining a home bus signal comprising a first logic sub-signal, wherein the first logic sub-signal comprises a low level signal and a first high level signal, when determining the duty ratio data of the low level signal and the duty ratio data of the first high level signal, determining a first sampling point for acquiring the low level signal and a second sampling point for acquiring the first high level signal according to the determined duty ratio data and a preset sampling point selection rule, further acquiring the low level signal according to the first sampling point, acquiring the first high level signal according to the second sampling point, and then determining a first target signal corresponding to the first logic sub-signal according to a preset signal conversion rule, so that even under the condition that the duty ratio data changes, the low level signal, the first high level signal and the second high level signal can still be determined, The first high-level signal avoids the problem of acquisition error caused by the change of the duty ratio, and successful communication is realized.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a data processing method and device.
Background
The home bus home hus signal includes a logic "0" signal and a logic "1" signal, see the encoding manner of the home hus signal shown in fig. 1, when the transmission frequency is 10KHz, the logic "1" signal is a high level signal with a pulse width of 100us, and the logic "0" signal includes: a low signal having a pulse width of 50us and a high signal having a pulse width of 50us, and the duty ratios of the low signal and the high signal are 50% in the logic "0" signal, respectively.
When a home hus signal is sent, a delay phenomenon may occur when a logic "0" signal is inverted to a logic "1" signal, which may cause pulse widths of a high level signal and a low level signal in the logic "0" signal to be unequal, that is, duty ratios of the high level signal and the low level signal in the logic "0" signal are not 50%, and further when the home bus signal is received, due to variation of the duty ratios, when the high level signal and the low level signal in the logic "0" signal are acquired, an acquisition error may occur, thereby causing a communication failure.
Based on this, how to accurately acquire the high-level signal and the low-level signal in the logic "0" signal to achieve successful communication is a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The embodiment of the invention provides a data processing method and data processing equipment, which are used for accurately acquiring a high-level signal and a low-level signal in a logic '0' signal to realize successful communication.
In a first aspect, an embodiment of the present invention provides a data processing method, including:
acquiring a home bus signal comprising a first logic sub-signal; wherein the first logic sub-signal comprises a low level signal and a first high level signal;
determining duty cycle data of the low level signal and duty cycle data of the first high level signal;
determining a first sampling point for acquiring the low level signal and a second sampling point for acquiring the first high level signal according to the determined duty ratio data and a preset sampling point selection rule;
and determining a first target signal corresponding to the first logic sub-signal according to the low level signal acquired by the first sampling point, the first high level signal acquired by the second sampling point and a preset signal conversion rule.
Optionally, in an embodiment of the present invention, after acquiring the home bus signal and before determining the duty ratio data of the low level signal and the duty ratio data of the first high level signal, the method further includes:
and carrying out burr signal filtering processing on the home bus signal.
Optionally, in this embodiment of the present invention, the performing glitch signal filtering on the home bus signal specifically includes:
when the fact that the N same home bus signals are continuously acquired is judged, the fact that the N same home bus signals are all effective signals is determined;
n is an integer greater than 1, and the value of N is determined according to the width of a glitch signal, the bit width of a register and the period of a system clock;
determining the duty cycle data of the low level signal and the duty cycle data of the first high level signal specifically includes:
duty cycle data of the low level signal in the active signal and duty cycle data of the first high level signal in the active signal are determined.
Optionally, in this embodiment of the present invention, determining the duty ratio data of the low level signal and the duty ratio data of the first high level signal specifically includes:
determining pulse widths of Q low-level signals; q is an integer greater than 1;
respectively determining the maximum pulse width and the minimum pulse width in the pulse widths of Q low-level signals;
and determining the maximum pulse width and the minimum pulse width of the first high-level signal according to the maximum pulse width and the minimum pulse width in the pulse widths of the Q low-level signals.
Optionally, in an embodiment of the present invention, the sampling point selection rule includes:
m sampling points are arranged and are evenly distributed in the first logic sub-signal, one sampling point is set for each of the first sampling point and the second sampling point, and M is an integer greater than 1;
the first sampling point is: the sampling point which is closest to one half of the duty ratio of the low-level signal with the minimum pulse width is selected from the sampling points in the low-level signal with the minimum pulse width;
the second sampling point is: the sampling point which is nearest to one half of the duty ratio of the first high-level signal with the minimum pulse width is selected from the sampling points in the first high-level signal with the minimum pulse width.
Optionally, in this embodiment of the present invention, a value of M is determined according to a baud rate clock period.
Optionally, in this embodiment of the present invention, the home bus signal further includes a second logic sub-signal, where the second logic sub-signal includes a second high-level signal;
the data processing method further comprises the following steps:
determining a third sampling point for acquiring the second high-level signal;
determining a second target signal corresponding to the second logic sub-signal according to the second high-level signal acquired by the third sampling point and the signal conversion rule;
and determining the uart signal of the asynchronous transceiver corresponding to the home bus signal according to the first target signal and the second target signal.
Optionally, in an embodiment of the present invention, the signal conversion rule includes:
when the low level signal collected by the first sampling point and the first high level signal collected by the second sampling point are the same, the first target signal is the low level signal;
the number of the third sampling points is two, and when the second high level signal is acquired by the two third sampling points, the second target signal is the second high level signal.
In a second aspect, an embodiment of the present invention provides a data processing apparatus, including:
a memory for storing program instructions;
a processor for calling the program instructions stored in the memory, and executing according to the obtained program:
acquiring a home bus signal comprising a first logic sub-signal; wherein the first logic sub-signal comprises a low level signal and a first high level signal;
determining duty cycle data of the low level signal and duty cycle data of the first high level signal;
determining a first sampling point for acquiring the low level signal and a second sampling point for acquiring the first high level signal according to the determined duty ratio data and a preset sampling point selection rule;
and determining a first target signal corresponding to the first logic sub-signal according to the low level signal acquired by the first sampling point, the first high level signal acquired by the second sampling point and a preset signal conversion rule.
In a third aspect, the embodiment of the present invention provides a computer-readable non-volatile storage medium, where the computer-readable non-volatile storage medium stores computer-executable instructions, and the computer-executable instructions are used to cause a computer to execute the processing method.
The invention has the following beneficial effects:
the data processing method and the data processing equipment provided by the embodiment of the invention firstly obtain a home bus signal comprising a first logic sub-signal, wherein the first logic sub-signal comprises a low-level signal and a first high-level signal, when duty ratio data of the low-level signal and duty ratio data of the first high-level signal are determined, a first sampling point for acquiring the low-level signal and a second sampling point for acquiring the first high-level signal can be determined according to the determined duty ratio data and a preset sampling point selection rule, then the low-level signal can be acquired according to the first sampling point, the first high-level signal can be acquired according to the second sampling point, then a first target signal corresponding to the first logic sub-signal is determined according to a preset signal conversion rule, and thus, even under the condition that the duty ratio data are changed, the low-level signal can still be acquired according to the determined first sampling point, the first high level signal is acquired according to the determined second sampling point, so that the problem of acquisition error caused by the change of the duty ratio is avoided, the low level signal and the first high level signal can be effectively acquired, and successful communication is facilitated; moreover, the method provided by the embodiment of the invention can be completed on the basis of the structure of the existing data processing equipment without additionally increasing logic, thereby being beneficial to reducing the manufacturing cost of the equipment.
Drawings
FIG. 1 is a schematic diagram illustrating a method for encoding a home hus signal in the prior art;
fig. 2 is a flowchart of a data processing method provided in an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a relationship between a home bus signal, a uart signal, and a square wave signal according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a first sampling point provided in an embodiment of the present invention;
FIG. 5 is a schematic diagram of a second sampling point provided in an embodiment of the present invention;
FIG. 6 is a schematic diagram of a home bus signal and a uart signal provided in an embodiment of the present invention;
FIG. 7 is a flow chart of a method of an embodiment provided in an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a first data processing apparatus provided in an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a second data processing apparatus provided in an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a third data processing apparatus provided in the embodiment of the present invention.
Detailed Description
The following describes in detail a specific implementation of a data processing method and apparatus according to an embodiment of the present invention with reference to the accompanying drawings. It should be noted that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a data processing method, as shown in fig. 2, which may include:
s201, acquiring a home bus signal including a first logic sub-signal; wherein the first logic sub-signal comprises a low level signal and a first high level signal;
the specific process of acquiring the home bus signal may be implemented by using the prior art, and is not specifically limited herein.
As shown in fig. 3, the acquired home bus signal may be determined from the uart signal and the square wave signal.
The specific process comprises the following steps:
for uart signals, the signal in each time T is a high level signal or a low level signal;
for square wave signals, each time T can be understood as a repetition period, and each repetition period comprises a low level signal and a high level signal;
therefore, for any time T, the uart signal and the square wave signal may be subjected to phase or processing to determine a home bus signal corresponding to the time T; specifically, if at least one of the square wave signal and the uart signal is a high level signal, the obtained home bus signal is a high level signal, and if both of the square wave signal and the uart signal are low level signals, the obtained home bus signal is a low level signal.
Also, the first logic sub-signal may be regarded as a signal represented by logic "0" in fig. 1, and the logic "0" signal may include a low level signal and a first high level signal.
S202, determining duty ratio data of a low-level signal and duty ratio data of a first high-level signal;
the duty ratio is a ratio of the energization time to the total time in one pulse cycle.
For example: pulse width 1 mus, signal period 4 mus, the duty cycle of the pulse sequence is
S203, determining a first sampling point for acquiring a low-level signal and a second sampling point for acquiring a first high-level signal according to the determined duty ratio data and a preset sampling point selection rule;
s204, determining a first target signal corresponding to the first logic sub-signal according to the low level signal acquired by the first sampling point, the first high level signal acquired by the second sampling point and a preset signal conversion rule.
Therefore, even under the condition that the duty ratio data changes, the low level signals can be still acquired according to the determined first sampling points, and the first high level signals are acquired according to the determined second sampling points, so that the problem of acquisition errors caused by the change of the duty ratio is solved, the low level signals and the first high level signals can be effectively acquired, and the successful communication is favorably realized; moreover, the method provided by the embodiment of the invention can be completed on the basis of the structure of the existing data processing equipment without additionally increasing logic, thereby being beneficial to reducing the manufacturing cost of the equipment.
In specific implementation, in the embodiment of the present invention, after acquiring the home bus signal and before determining the duty ratio data of the low level signal and the duty ratio data of the first high level signal, the method further includes:
and carrying out burr signal filtering processing on the home bus signal.
So, carry out burr signal filtering processing to home bus signal, that is to say, got rid of the interference (the burr signal promptly), avoided the burr signal to the problem of home bus signal interference, be favorable to the duty cycle data of the low level signal in the first logic sub-signal of follow-up calculation and the duty cycle data of first high level signal more accurate.
Specifically, in the embodiment of the present invention, the filtering processing of the glitch signal on the home bus signal specifically includes:
when the N same home bus signals are continuously acquired, determining that the N same home bus signals are all effective signals;
n is an integer greater than 1, and the value of N is determined according to the width of a glitch signal, the bit width of a register and the period of a system clock;
determining duty cycle data of the low level signal and duty cycle data of the first high level signal, specifically including:
duty ratio data of a low level signal in the valid signal and duty ratio data of a first high level signal in the valid signal are determined.
It should be noted that if it is not determined that N identical home bus signals are continuously acquired, the signals are regarded as glitches, and the glitches are filtered out. At this time, the counter for counting the number of samples is cleared, and after the counter is cleared, the obtained home bus signal is counted again.
The value of N is determined according to the width of the glitch signal, the bit width of the register, and the system clock cycle, and mainly includes the following points:
reason 1, the width for valid data (which can be understood as the home bus signal from which the glitch signal has been filtered) can be set as: the width of the valid data is greater than or less than the width of the glitch signal. That is to say, the width of the effective data is different from the width of the glitch signal, and the purpose set up like this is mainly in order to distinguish the effective data from the glitch signal, also separates the effective data from the glitch signal, and then can carry out filtering processing with the glitch signal that separates.
Reason 2, if the maximum filter width is configured by the register as N:
the bit width of the register is t, then the filtering range is: 1 clock _ period-2tClock _ period, and the value of t may be set according to actual conditions, which is not specifically limited herein, so as to improve the flexibility of design.
For example, taking the bit width t of the register as 32 bits as an example, in order to ensure that the filtering range is wide enough, the filtering range is: 1 clock _ period-232Clock _ period; wherein, clock _ period is a system clock period;
for another example, taking the bit width t of the register as 64 bits as an example, in order to ensure that the filtering range is wide enough, the filtering range is: 1 clock _ period-264Clock _ period; wherein clock _ period is a system clock cycle.
Therefore, the value of N is related to the bit width of the register and the system clock cycle, that is, the value of N is determined by the bit width of the register and the system clock cycle.
It should be noted that, for the calculation of the duty ratio data, only the duty ratio data of the low level signal and the duty ratio data of the first high level signal in the valid signal are considered, that is, the glitch signal is not considered, and the glitch signal is filtered.
Therefore, after the home bus signal is acquired, the effective signal is determined, the burr signal is removed, the duty ratio data of the low-level signal in the calculated effective signal and the duty ratio data of the first high-level signal in the effective signal are more accurate, and the determination of the first sampling point and the second sampling point according to the duty ratio data is facilitated subsequently.
In specific implementation, in the embodiment of the present invention, determining the duty ratio data of the low level signal and the duty ratio data of the first high level signal specifically includes:
determining pulse widths of Q low-level signals; q is an integer greater than 1;
respectively determining the maximum pulse width and the minimum pulse width in the pulse widths of the Q low-level signals;
and determining the maximum pulse width and the minimum pulse width of the first high-level signal according to the maximum pulse width and the minimum pulse width in the pulse widths of the Q low-level signals.
The value of Q can be set according to the actual condition required by a user, and is not specifically limited, so that the design flexibility is improved, and the requirements of different scenes are met.
And, when determining the maximum pulse width and the minimum pulse width of the first high level signal according to the maximum pulse width and the minimum pulse width of the Q low level signal pulse widths determined, since the first logic sub-signal includes a low level signal and a first high level signal, therefore:
assuming that, among the pulse widths of the Q low-level signals, when the pulse width of the i-th low-level signal is the largest and the pulse width of the i + m-th low-level signal is the smallest, the pulse width of the i-th first high-level signal corresponding to the i-th low-level signal is the smallest, and similarly, the pulse width of the i + m-th first high-level signal corresponding to the i + m-th low-level signal is the largest.
Therefore, the pulse width data of the low level signal and the first high level signal can be determined, namely, the determined duty ratio data of the low level signal and the determined duty ratio data of the first high level signal are beneficial to determining a first sampling point and a second sampling point according to the duty ratio data subsequently, and therefore the sampling accuracy of the low level signal and the sampling accuracy of the first high level signal are beneficial to being improved.
Specifically, in the embodiment of the present invention, the sampling point selection rule includes:
m sampling points are arranged and are evenly distributed in the first logic sub-signal, the first sampling point and the second sampling point are both set to be one, and M is an integer larger than 1;
the first sample point is: among the sampling points in the low-level signal with the minimum pulse width, the sampling point closest to one half of the low-level signal with the minimum pulse width;
the second sampling point is: among the sampling points in the first high level signal having the smallest pulse width, the sampling point closest to one-half of the first high level signal having the smallest pulse width.
Alternatively, for the first sampling point, when it is assumed that there are two sampling points closest to one-half of the duty ratio from among the sampling points in the low-level signal having the smallest pulse width, any one of the two sampling points may be selected as the first sampling point.
Likewise, for the second sampling point, assuming that there are two sampling points closest to one-half of the duty ratio among the sampling points in the first high-level signal having the smallest pulse width, any one of the two sampling points may be selected as the second sampling point.
For example, an example in which M is 16 will be described.
As shown in fig. 4 and 5, there are 16 solid lines corresponding to sixteenth, each solid line representing a sampling point, and the 16 sampling points are evenly distributed in the first logic sub-signal of the home bus signal;
referring to fig. 4, which shows the low level signal with the minimum pulse width, assuming there are 4 corresponding sampling points (i.e., from 1/16 to 4/16), since 5/16 is at the boundary (i.e., rising edge) between the low level signal and the first high level signal, 5/16 can be considered as being neither in the low level signal nor in the first high level signal; and, of these 4 sampling points, the 2 nd sampling point (i.e., the solid line corresponding to position 2/16 in the figure), and the 3 rd sampling point (i.e., the solid line corresponding to position 3/16 in the figure) are all closest to one-half of the duty cycle of the low-level signal having the smallest pulse width (as shown in position C1 in the figure), and the distance between the 2 nd sampling point and position C1, and the distance between the 3 rd sampling point and position C1 are the same, at which time, this sampling point 2/16 or the sampling point 3/16 may be taken as the first sampling point;
referring to fig. 5, a first high level signal with a minimum pulse width is shown, and assuming that the first high level signal corresponds to 3 sampling points (i.e., from 13/16 to 15/16), since the two sampling points 12/16 and 16/16 are respectively above the rising edge and the falling edge, the two sampling points can be considered to be neither in the low level signal nor in the first high level signal; and, of the 3 sampling points, the 2 nd sampling point (i.e., the corresponding solid line at the position 14/16 in the figure) is closest to one-half of the duty ratio of the first high level signal (as shown by the position C2 in the figure), so this 14/16 sampling point is taken as the second sampling point.
Optionally, the set number M of the sampling points is not fixed and is not limited to 16, and the more sampling points are theoretically set, the more sampling can be guaranteed to reach a correct value, that is, the set number of the sampling points is not specifically limited, and can be determined according to actual conditions, so that the flexibility of design is improved.
The setting principle for the position of the sampling point may include:
(1) even under the condition that the duty ratio data is changed, the set first sampling point and the second sampling point can still sample correct data, and therefore normal communication is guaranteed.
(2) The position of the first sampling point is at the position where the low level signal is close to the middle, and similarly, the position of the second sampling point is at the position where the first high level signal is close to the middle.
So, set up the position of first sampling point, second sampling point at the intermediate position that is close to low level signal, first high level signal respectively, be favorable to gathering the exact signal through first sampling point and second sampling point, reduce the probability that the collection error takes place, improved the rate of accuracy of gathering greatly.
Meanwhile, the determination process is simple, the calculation amount and the processing amount of the equipment can be reduced, and the processing speed of the equipment can be improved, so that the determination efficiency of the first sampling point and the second sampling point is improved.
Optionally, in the embodiment of the present invention, taking the determination of the first sampling point as an example, in addition to determining the first sampling point according to the minimum pulse width of the low level signal, the first sampling point may also be determined according to the average pulse width and the minimum pulse width of the low level signal, which is described in detail below:
1. before determining the first sampling point, the average pulse width of the low level signal is described.
Specifically, the average pulse width of the low-level signal can be understood as: average value of pulse widths of the Q low-level signals.
2. Determining the first sampling point according to the average pulse width and the minimum pulse width of the low-level signal may specifically include the following processes:
process 1, determining the middle position (temporarily called a) of the average pulse width of the low-level signal;
process 2, determining the middle position (temporarily called b) of the minimum pulse width of the low-level signal;
3, determining the middle position c of a and b;
step 4, judging whether c is in the range of the minimum pulse width of the low-level signal; if yes, executing the process 5; if not, executing the process 6;
step 5, determining c as the position of the first sampling point; the flow is finished;
process 6, determining the intermediate position d of a and c;
step 7, judging whether d is in the range of the minimum pulse width of the low-level signal; if yes, executing the process 8; if not, go to process 9;
step 8, determining c as the position of the first sampling point; the flow is finished;
and 9, determining the middle position e of the a and the d, and determining the middle position e as a first sampling point when determining that the middle position e is within the range of the minimum pulse width of the low-level signal.
That is to say, the finally determined first sampling point needs to be located within the range of the minimum pulse width of the low-level signal to ensure that the low-level signal can be acquired; if the currently determined position is not within the range of the minimum pulse width of the low-level signal, the search is continued until the found position is within the range of the minimum pulse width of the low-level signal.
Similarly, when determining the second sampling point, the average pulse width of the first high-level signal and the minimum pulse width may also be used as the determination, and the average pulse width of the first high-level signal may also be understood as: an average value of pulse widths of the Q first high level signals; in addition, for a specific determination process, reference may be made to the above process of determining the first sampling point according to the average pulse width and the minimum pulse width of the low-level signal, and repeated parts are not described again.
Therefore, when the first sampling point and the second sampling point are determined according to the average pulse width and the minimum pulse width, the situation that the position where the first sampling point is located is within the range of the minimum pulse width of the low-level signal is guaranteed, the conditions of the pulse width of each low-level signal and the pulse width of each first high-level signal can be considered, the considered factors are more and more comprehensive, the influence caused by extreme conditions is reduced, the low-level signal and the first high-level signal can be accurately acquired through the first sampling point and the second sampling point, the first target signal is obtained conveniently, and the signal conversion is achieved.
Specifically, in the embodiment of the present invention, the value of M is determined according to the baud rate clock period.
For example, 1-bit time is taken as an example, wherein 1-bit time is 16 baud rate clock cycles, that is, the baud rate clock cycle is one sixteenth of 1-bit time, so that the 1-bit time can be divided into 16 segments by the baud rate clock cycle for sampling, wherein each segment is provided with one sampling point, and then within 1-bit time, 16 sampling points are provided, that is, the number M of the sampling points is 16.
To illustrate, as shown in fig. 4, the above example mentioned that there are 16 sampling points when the baud rate clock period is 1bit, and then when the first sampling point and the second sampling point are determined, they can be selected from the 16 sampling points, that is, it is determined that the first sampling point and the second sampling point range from one sixteenth to sixteen sixteenth of the 1bit baud rate clock period.
Therefore, the baud rate clock period can be selected according to the actual situation, and is not specifically limited herein, so as to meet the requirements of different scenes and improve the flexibility of design.
In practical implementation, in the embodiment of the present invention, the home bus signal further includes a second logic sub-signal, and the second logic sub-signal includes a second high level signal;
the data processing method further comprises the following steps:
determining a third sampling point for acquiring a second high-level signal;
determining a second target signal corresponding to the second logic sub-signal according to a second high-level signal acquired by the third sampling point and a signal conversion rule;
and determining a uart signal corresponding to the home bus signal according to the first target signal and the second target signal.
Wherein the second logic sub-signal can be regarded as a signal represented by a logic "1" in fig. 1, and the logic "1" includes the second high level signal.
In this regard, the first high-level signal and the second high-level signal may have the same potential, may be different potentials, may be provided according to actual conditions, and is not particularly limited herein.
And, can set up third sampling point position and quantity at random, also can set up according to actual conditions, do not specifically limit here to satisfy the demand of different scenes, improve the flexibility of design.
So, according to first sampling point, second sampling point and third sampling point, determine first target signal and second target signal to determine the uart signal that corresponds with home bus signal, make the uart signal that determines more accurate, be favorable to realizing successful communication.
Specifically, in the embodiment of the present invention, the signal conversion rule includes:
when the low level signal acquired by the first sampling point and the first high level signal acquired by the second sampling point are the same, the first target signal is a low level signal;
the number of the third sampling points is two, and when the second high level signal is collected by the two third sampling points, the second target signal is the second high level signal.
For example, as shown in fig. 6, when a low level signal in the first logic sub-signal is collected at a first sampling point (i.e., point a in fig. 6) and a first high level signal in the first logic sub-signal is collected at a second sampling point (i.e., point B in fig. 6), after performing an and process, it may be determined that the first target signal is a low level signal;
when two second high level signals in the second logic sub-signals are acquired at the third sampling point (i.e., point C, D in fig. 6), it may be determined that the second target signal is the second high level signal after performing the phase and processing;
the uart signal is then composed of a low level signal and a second high level signal.
The signal conversion rule is not limited to the above, and may be set according to factors such as a signal encoding method and uart protocol, and is not particularly limited herein.
Therefore, according to the low level signal collected by the first sampling point, the first high level signal collected by the second sampling point, the second high level signal collected by the third sampling point and the preset signal conversion rule, the first target signal and the second target signal are determined, and the method is favorable for obtaining the uart signal corresponding to the home bus signal, so that successful communication is realized.
The following describes the processing method provided by the embodiment of the present invention with specific examples.
The first embodiment is as follows: taking as an example that when it is determined that 10 identical home bus signals are continuously acquired, it is determined that the 10 identical home bus signals are all valid signals, a first sampling point is determined according to a low level signal with a minimum pulse width, and a second sampling point is determined according to a first high level signal with a minimum pulse width, as shown in fig. 7.
S701, obtaining a home bus signal, wherein the home bus signal comprises a first logic sub-signal and a second logic sub-signal, and the first logic sub-signal comprises a low-level signal and a first high-level signal; the second logic sub-signal comprises a second high level signal;
s702, determining the pulse width of a low-level signal in 10 home bus signals when the 10 home bus signals are determined to be acquired;
s703, respectively determining the maximum pulse width and the minimum pulse width in the pulse widths of the 10 low-level signals, namely determining the duty ratio data of the low-level signals;
s704, determining the maximum pulse width and the minimum pulse width of the first high-level signal, namely duty ratio data of the first high-level signal;
s705, determining a first sampling point for acquiring a low-level signal and a second sampling point for acquiring a first high-level signal according to the determined duty ratio data and a preset sampling point selection rule;
s706, determining a third sampling point for acquiring a second high-level signal;
s707, determining a first target signal corresponding to the first logic sub-signal and a second target signal corresponding to the second logic sub-signal according to the low level signal acquired by the first sampling point, the first high level signal acquired by the second sampling point, the second high level signal acquired by the third sampling point and a preset signal conversion rule;
s708, determining a uart signal corresponding to the home bus signal according to the first target signal and the second target signal.
Based on the same inventive concept, embodiments of the present invention provide a data processing device, an implementation principle of the device is similar to that of the aforementioned data method, and specific embodiments of the device may refer to the implementation manner of the aforementioned method, and repeated details are omitted.
Specifically, the data processing apparatus provided in the embodiment of the present invention, as shown in fig. 8, includes:
a memory 801 for storing program instructions;
the processor 802 is configured to call the program instructions stored in the memory 801, and execute the following steps according to the obtained program:
acquiring a home bus signal comprising a first logic sub-signal; wherein the first logic sub-signal comprises a low level signal and a first high level signal;
determining duty ratio data of a low level signal and duty ratio data of a first high level signal;
determining a first sampling point for acquiring a low level signal and a second sampling point for acquiring a first high level signal according to the determined duty ratio data and a preset sampling point selection rule;
and determining a first target signal corresponding to the first logic sub-signal according to the low level signal acquired by the first sampling point, the first high level signal acquired by the second sampling point and a preset signal conversion rule.
Optionally, in this embodiment of the present invention, the processor 802 is further configured to:
after the home bus signal is acquired, and before the duty ratio data of the low-level signal and the duty ratio data of the first high-level signal are determined, filtering burr signals of the home bus signal.
Optionally, in this embodiment of the present invention, the processor 802 is specifically configured to:
when the N same home bus signals are continuously acquired, determining that the N same home bus signals are all effective signals;
n is an integer greater than 1, and the value of N is determined according to the width of a glitch signal, the bit width of a register and the period of a system clock;
determining duty cycle data of the low level signal and duty cycle data of the first high level signal, specifically including:
duty ratio data of a low level signal in the valid signal and duty ratio data of a first high level signal in the valid signal are determined.
Optionally, in this embodiment of the present invention, the processor 802 is specifically configured to:
determining pulse widths of Q low-level signals; q is an integer greater than 1;
respectively determining the maximum pulse width and the minimum pulse width in the pulse widths of the Q low-level signals;
and determining the maximum pulse width and the minimum pulse width of the first high-level signal according to the maximum pulse width and the minimum pulse width in the pulse widths of the Q low-level signals.
Optionally, in an embodiment of the present invention, the sampling point selection rule includes:
m sampling points are arranged and are evenly distributed in the first logic sub-signal, the first sampling point and the second sampling point are both set to be one, and M is an integer larger than 1;
the first sample point is: among the sampling points in the low-level signal with the minimum pulse width, the sampling point closest to one half of the low-level signal with the minimum pulse width;
the second sampling point is: among the sampling points in the first high level signal having the smallest pulse width, the sampling point closest to one-half of the first high level signal having the smallest pulse width.
Optionally, in this embodiment of the present invention, a value of M is determined according to a baud rate clock period.
Optionally, in this embodiment of the present invention, the processor 802 is further configured to:
the home bus signal further comprises a second logic sub-signal, and the second logic sub-signal comprises a second high-level signal;
determining a third sampling point for acquiring a second high-level signal;
determining a second target signal corresponding to the second logic sub-signal according to a second high-level signal acquired by the third sampling point and a signal conversion rule;
and determining the uart signal of the asynchronous transceiver corresponding to the home bus signal according to the first target signal and the second target signal.
Optionally, in an embodiment of the present invention, the signal conversion rule includes:
when the low level signal acquired by the first sampling point and the first high level signal acquired by the second sampling point are the same, the first target signal is a low level signal;
the number of the third sampling points is two, and when the second high level signal is collected by the two third sampling points, the second target signal is the second high level signal.
Optionally, in an embodiment of the present invention, to implement the function of the processor, as shown in fig. 9, the processor may specifically include: a duty ratio statistic module 901, a sampling module 902 and a filtering module 903;
a filtering module 903, configured to: receiving a home bus signal sent by the analog circuit 906, and after performing burr filtering processing on the received home bus signal, respectively sending the home bus signal to the duty ratio counting module 901 and the sampling module 902;
a duty cycle statistics module 901 configured to: when a home bus signal including a first logic sub-signal is received, determining duty ratios of a low level signal and a first high level signal in the first logic sub-signal, and sending a determination result to the sampling module 902;
a sampling module 902 configured to: receiving a home bus signal; determining a first sampling point and a second sampling point according to a determination result sent by the duty ratio statistic module 901; and when the third sampling point is determined, respectively acquiring a low level signal, a first high level signal and a second high level signal in the received home bus signal through the first sampling point, the second sampling point and the third sampling point, converting the low level signal, the first high level signal and the second high level signal into a corresponding first target signal and a corresponding second target signal, and finally determining a uart signal corresponding to the home bus signal.
Optionally, in this embodiment of the present invention, as shown in fig. 9, the data processing apparatus may further include:
a universal asynchronous transceiver 904 to: receiving or sending uart signals and square wave signals;
Optionally, in the embodiment of the present invention, if the function of the processor is to be implemented, referring to fig. 10, the structure of the processor may be further configured to: a duty ratio statistic module 1001, a sampling module 1002, a filtering module 1003, a register module 1007, and a processing module 1008;
a filtering module 1003 configured to: receiving a home bus signal sent by the analog circuit 1006, and after performing burr filtering on the received home bus signal, respectively sending the home bus signal to the duty ratio statistics module 1001 and the sampling module 1002;
a duty cycle statistics module 1001 configured to: when a home bus signal including a first logic sub-signal is received, determining duty ratios of a low level signal and a first high level signal in the first logic sub-signal, and writing the determination result into the register module 1007;
a processing module 1008 to: reading the determination result in the register module 1007, and sending the read determination result to the sampling module 1002;
a sampling module 1002 to: receiving a home bus signal; determining a first sampling point and a second sampling point according to a determination result sent by the processing module 1001; and when the third sampling point is determined, respectively acquiring a low level signal, a first high level signal and a second high level signal in the received home bus signal through the first sampling point, the second sampling point and the third sampling point, converting the low level signal, the first high level signal and the second high level signal into a corresponding first target signal and a corresponding second target signal, and finally determining a uart signal corresponding to the home bus signal.
For other modules, examples include, but are not limited to: the functions of the universal asynchronous receiver/transmitter 1004, the analog circuit 1006, the logic circuit 1005, and the external device 1009 are similar to the functions of the universal asynchronous receiver/transmitter 904, the analog circuit 906, the logic circuit 905, and the external device 907 mentioned above, and repeated descriptions are omitted here.
Based on the same inventive concept, the embodiment of the present invention provides a computer-readable non-volatile storage medium, in which computer-executable instructions are stored, and the computer-executable instructions are used for enabling a computer to execute the processing method.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, implement the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. A data processing method, comprising:
acquiring a home bus signal comprising a first logic sub-signal; wherein the first logic sub-signal comprises a low level signal and a first high level signal;
determining the duty cycle data of the low level signal and the duty cycle data of the first high level signal specifically includes:
when Q home bus signals are obtained, determining the pulse width of a low-level signal in the Q home bus signals; q is an integer greater than 1;
respectively determining the maximum pulse width and the minimum pulse width in the pulse widths of Q low-level signals;
determining the maximum pulse width and the minimum pulse width of the first high-level signal according to the maximum pulse width and the minimum pulse width in the pulse widths of the Q low-level signals;
determining a first sampling point for acquiring the low level signal and a second sampling point for acquiring the first high level signal according to the determined duty ratio data and a preset sampling point selection rule;
wherein the sampling point selection rule comprises:
m sampling points are arranged and are evenly distributed in the first logic sub-signal, one sampling point is set for each of the first sampling point and the second sampling point, and M is an integer greater than 1;
the first sampling point is: among the sampling points in the low-level signal with the minimum pulse width, the sampling point closest to one half of the low-level signal with the minimum pulse width;
the second sampling point is: among the sampling points in the first high-level signal with the minimum pulse width, the sampling point closest to one half of the first high-level signal with the minimum pulse width;
and determining a first target signal corresponding to the first logic sub-signal according to the low level signal acquired by the first sampling point, the first high level signal acquired by the second sampling point and a preset signal conversion rule.
2. The method of claim 1, after acquiring a home bus signal and before determining the duty cycle data for the low level signal and the duty cycle data for the first high level signal, further comprising:
and carrying out burr signal filtering processing on the home bus signal.
3. The method of claim 2, wherein performing glitch filtering on the home bus signal comprises:
when the fact that the N same home bus signals are continuously acquired is judged, the fact that the N same home bus signals are all effective signals is determined;
n is an integer greater than 1, and the value of N is determined according to the width of a glitch signal, the bit width of a register and the period of a system clock;
determining the duty cycle data of the low level signal and the duty cycle data of the first high level signal specifically includes:
duty cycle data of the low level signal in the active signal and duty cycle data of the first high level signal in the active signal are determined.
4. The method of claim 1, wherein the value of M is determined based on a baud rate clock period.
5. The method of claim 1, wherein the home bus signal further comprises a second logic sub-signal, the second logic sub-signal comprising a second high level signal;
the data processing method further comprises the following steps:
determining a third sampling point for acquiring the second high-level signal;
determining a second target signal corresponding to the second logic sub-signal according to the second high-level signal acquired by the third sampling point and the signal conversion rule;
and determining the uart signal of the asynchronous transceiver corresponding to the home bus signal according to the first target signal and the second target signal.
6. The method of claim 5, wherein the signal conversion rule comprises:
when the low level signal collected by the first sampling point and the first high level signal collected by the second sampling point are the same, the first target signal is the low level signal;
the number of the third sampling points is two, and when the second high level signal is acquired by the two third sampling points, the second target signal is the second high level signal.
7. A data processing apparatus, characterized by comprising:
a memory for storing program instructions;
a processor for calling the program instructions stored in the memory, and executing according to the obtained program:
acquiring a home bus signal comprising a first logic sub-signal; wherein the first logic sub-signal comprises a low level signal and a first high level signal;
determining the duty cycle data of the low level signal and the duty cycle data of the first high level signal specifically includes:
when Q home bus signals are obtained, determining the pulse width of a low-level signal in the Q home bus signals; q is an integer greater than 1;
respectively determining the maximum pulse width and the minimum pulse width in the pulse widths of Q low-level signals;
determining the maximum pulse width and the minimum pulse width of the first high-level signal according to the maximum pulse width and the minimum pulse width in the pulse widths of the Q low-level signals;
determining a first sampling point for acquiring the low level signal and a second sampling point for acquiring the first high level signal according to the determined duty ratio data and a preset sampling point selection rule;
wherein the sampling point selection rule comprises:
m sampling points are arranged and are evenly distributed in the first logic sub-signal, one sampling point is set for each of the first sampling point and the second sampling point, and M is an integer greater than 1;
the first sampling point is: among the sampling points in the low-level signal with the minimum pulse width, the sampling point closest to one half of the low-level signal with the minimum pulse width;
the second sampling point is: among the sampling points in the first high-level signal with the minimum pulse width, the sampling point closest to one half of the first high-level signal with the minimum pulse width;
and determining a first target signal corresponding to the first logic sub-signal according to the low level signal acquired by the first sampling point, the first high level signal acquired by the second sampling point and a preset signal conversion rule.
8. A computer-readable non-volatile storage medium having computer-executable instructions stored thereon for causing a computer to perform the data processing method of any one of claims 1 to 6.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4959713A (en) * | 1989-10-10 | 1990-09-25 | Matsushita Electric Industrial Co., Ltd. | Home automation system |
| CN102103168A (en) * | 2009-12-22 | 2011-06-22 | 比亚迪股份有限公司 | PWM (Pulse-Width Modulation) wave detecting method and device |
| CN102957503A (en) * | 2011-08-31 | 2013-03-06 | 北京中电华大电子设计有限责任公司 | MMC (Multi Media Card) code type data decoding method applicable to different duty ratios |
| CN103605028A (en) * | 2013-11-26 | 2014-02-26 | 国家电网公司 | PWM testing system based on single period multipoint sampling |
| CN108120971A (en) * | 2017-12-12 | 2018-06-05 | 中国特种设备检测研究院 | Desired signal recognition methods, device, ground tracking equipment and system |
| CN210405343U (en) * | 2019-11-19 | 2020-04-24 | 青岛海信日立空调系统有限公司 | Air conditioner family bus test system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI327811B (en) * | 2007-03-26 | 2010-07-21 | Delta Electronics Inc | Method of sampling and adjusting duty ratio |
| CN104570858B (en) * | 2014-12-19 | 2017-08-29 | 深圳市科陆电子科技股份有限公司 | The analog signal method of sampling and sampling system |
-
2020
- 2020-06-09 CN CN202010518291.9A patent/CN111786865B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4959713A (en) * | 1989-10-10 | 1990-09-25 | Matsushita Electric Industrial Co., Ltd. | Home automation system |
| CN102103168A (en) * | 2009-12-22 | 2011-06-22 | 比亚迪股份有限公司 | PWM (Pulse-Width Modulation) wave detecting method and device |
| CN102957503A (en) * | 2011-08-31 | 2013-03-06 | 北京中电华大电子设计有限责任公司 | MMC (Multi Media Card) code type data decoding method applicable to different duty ratios |
| CN103605028A (en) * | 2013-11-26 | 2014-02-26 | 国家电网公司 | PWM testing system based on single period multipoint sampling |
| CN108120971A (en) * | 2017-12-12 | 2018-06-05 | 中国特种设备检测研究院 | Desired signal recognition methods, device, ground tracking equipment and system |
| CN210405343U (en) * | 2019-11-19 | 2020-04-24 | 青岛海信日立空调系统有限公司 | Air conditioner family bus test system |
Non-Patent Citations (1)
| Title |
|---|
| 基于预测电流控制的数字PFC的研究;石榴明璇;《中国优秀硕士学位论文全文数据库 工程科技Ⅱ辑》;20110315;第3.4节 * |
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