CN200976573Y - Sample rate converter - Google Patents

Abstract

The utility model relates to a sample rate converter, which comprises an input buffer cache for the original signals, an adder array for carrying out additive operations, an output buffer cache for outputting the results of the adder array, and a multi-phase sector for selecting data from the input buffer cache. The adder array conducts additive computations according to the output data from the multi-phase sector. The utility model has the advantages of selecting data through multi-phase selector after the step-up of frequency with the zero interpolation method; therefore, the computation work is greatly reduced and the number of the adders in the adder array is significantly reduced. The manufacturing cost is reduced accordingly from the hardware as a whole.

Description

Sampling rate converter

Technical field

The utility model relates to a kind of sampling rate converter that has improved.

Background technology

Sampling rate converter is a kind of device that is widely used in the digital processing field, is used for digital signal from a certain sample rate conversion to another sample rate.

Fig. 1 has disclosed the circuit theory diagrams of a kind of existing raising frequency-filtering-frequency reducing type sampling rate converter 1, it comprises that generally (its raising frequency multiple is L to interpolation upconverter 11, represent interpolation upconverter 11 with L among Fig. 1), low pass filter 12 (LPF, Low-PassFilter, represent low pass filter 12 with LPF among Fig. 1) and extract frequency demultiplier 13 (its frequency reducing multiple is M, extracts frequency demultiplier 13 with the M representative among Fig. 1).Need carry out the digital signal of sample rate conversion from input 10 inputs of interpolation upconverter 11, after digital signal is handled through interpolation upconverter 11, output is through the digital signal of resulting L frequency multiplication after the interpolation, the digital signal of this L frequency multiplication inputs to carries out low-pass filtering treatment in the low pass filter 12, signal after the processing exports to extract in the frequency demultiplier 13 and carries out down conversion process, finally, the output 14 output frequency reducing M digital signal doubly that is extracting frequency demultiplier 13, the sample rate conversion multiple of obviously, the raising frequency-filtering shown in Fig. 1-frequency reducing type sampling rate converter 1 is L/M.Because raising frequency-filtering-frequency reducing type sampling rate converter 1 shown in Figure 1 can be according to different precision and different proportionate relationships, select suitable low pass filter 12, thereby it can realize high-precision sample rate conversion easily by introducing the design of low pass filter 12.Yet,, cause the circuit cost of whole sampling rate converter 1 higher because required multiplier and the memory cell of low pass filter 12 is extremely many.

The application of CN1578137A Chinese invention patent discloses a kind of method and apparatus of rational sample rate conversion.Wherein said method is utilized the characteristic of rational sample rate conversion, reduced signal from the crude sampling rate to the needed multiply-add operation of purpose sample rate conversion.Described device then is made of processor, interpolater, filter, withdrawal device and the buffer of multiplicaton addition unit.The device of this cooperative work of software and hardware has the big advantage of flexibility, but hardware cost is still higher.

Summary of the invention

The purpose of this utility model provides a kind of sampling rate converter cheaply.

For achieving the above object, sampling rate converter provided by the present invention comprises:

The input buffer that is used for the buffer memory primary signal;

Adder array;

Be used for output buffer that the operation result of adder array is exported as the purpose signal;

Be connected between input buffer and the adder array, be used for from the heterogeneous selector of input buffer selection data.

Sampling rate converter provided by the utility model is after adopting zero insertion method raising frequency, by heterogeneous selector the data that need computing are selected, make operand greatly reduce, thereby make that the number of adder significantly reduces in the adder array, on hardware integral body, manufacturing cost decreases.

Concrete circuit structure will be introduced in following embodiment in detail.

Description of drawings

Fig. 1 is the circuit theory diagrams of existing raising frequency-filtering-frequency reducing type sampling rate converter;

Fig. 2 is the circuit theory diagrams that sampling rate converter described in the utility model is finished sample rate conversion;

Fig. 3 is the particular circuit configurations block diagram of the utility model sampling rate converter;

Fig. 4 is the internal circuit configuration schematic diagram of input buffer described in Fig. 3;

Fig. 5 is the internal circuit configuration schematic diagram of heterogeneous selector described in Fig. 3.

Be described in further detail below in conjunction with each embodiment and accompanying drawing thereof.

Embodiment

In conjunction with referring to shown in Fig. 2, Fig. 3, Fig. 2 has disclosed the circuit theory diagrams that sampling rate converter described in the utility model is finished sample rate conversion, its mode that remains employing raising frequency-filtering-frequency reducing realizes the conversion of sample rate, and Fig. 3 then is the particular circuit configurations block diagram that has disclosed the utility model sampling rate converter.

Introduce for the utility model being made clearly, in Fig. 2, the signal bandwidth that is converted is 6MHz by the sampling rate converter of 27MHz to 24MHz to suppose to need to realize one, and bit wide is 10bits (bits, a bit), and the bit wide of purpose signal is 10bits.Among Fig. 2, adopt the mode of zero insertion that the primary signal of input 20 inputs is carried out 8 times of raising frequencies (being the L=8 among Fig. 1), the sample rate of primary signal X (n) is 27MHz, obtain M signal X1 (n) through the flat device 21 of zero insertion raising frequency, its sample rate is 216MHz, and X1 (n) satisfies following relation with X (n):

Suppose that low pass filter 22 is low pass filters of one 30 rank linear phase, its coefficient is H (n) (0＜=n＜=30).

According to the computing formula of filter, the output Y1 (n) that obtains low pass filter 22 satisfies following relation with X1 (n):

$Y1\left(n\right)=\underset{i=0}{\overset{30}{\mathrm{\Σ}}}H\left(i\right)*X1(n-i)$

Use X (n) to replace X1 (n) again and eliminate all zero, can obtain following relation:

Y1(8*k)＝H(0)*X(k)+H(8)*X(k-1)+H(16)*X(k-2)+H(24)*X(k-3)

Y1(8*k+1)＝H(1)*X(k)+H(9)*X(k-1)+H(17)*X(k-2)+H(25)*X(k-3)

Y1(8*k+2)＝H(2)*X(k)+H(10)*X(k-1)+H(18)*X(k-2)+H(26)*X(k-3)

Y1(8*k+3)＝H(3)*X(k)+H(11)*X(k-1)+H(19)*X(k-2)+H(27)*X(k-3)

y1(8*k+4)＝H(4)*X(k)+H(12)*X(k-1)+H(20)*X(k-2)+H(28)*X(k-3)

Y1(8*k+5)＝H(5)*X(k)+H(13)*X(k-1)+H(21)*X(k-2)+H(29)*X(k-3)

Y1(8*k+6)＝H(6)*X(k)+H(14)*X(k-1)+H(22)*X(k-2)+H(30)*X(k-3)

Y1(8*k+7)＝H(7)*X(k)+H(15)*X(k-1)+H(23)*X(k-2)+0*X(k-3)

The output Y (n) that extracts frequency demultiplier 23 is through the signal after the sample rate conversion, and its sample rate is 24MHz, and satisfies following relation with Y1 (n):

Y(n)＝Y1(9*n)

Then satisfy following relation with X (n):

Y(8*k)＝H(0)*X(9*k)+H(8)*X(9*k-1)+H(16)*X(9*k-2)+H(24)*X(9*k-3)

Y(8*k+1)＝H(1)*X(9*k+1)+H(9)*X(9*k)+H(17)*X(9*k-1)+H(25)*X(9*k-2)

Y(8*k+2)＝H(2)*X(9*k+2)+H(10)*X(9*k+1)+H(18)*X(9*k)+H(26)*X(9*k-1)

Y(8*k+3)＝H(3)*X(9*k+3)+H(11)*X(9*k+2)+H(19)*X(9*k+1)+H(27)*X(9*k)

Y(8*k+4)＝H(4)*X(9*k+4)+H(12)*X(9*k+3)+H(20)*X(9*k+2)+H(28)*X(9*k+1)

Y(8*k+5)＝H(5)*X(9*k+5)+H(13)*X(9*k+4)+H(21)*X(9*k+3)+H(29)*X(9*k+2)

Y(*k+6)＝H(6)*X(9*k+6)+H(14)*X(9*k+5)+H(22)*X(9*k+4)+H(30)*X(9*k+3)

Y(8*k+7)＝H(7)*X(9*k+7)+H(15)*X(9*k+6)+H(23)*X(9*k+5)+0*X(9*k+4)

So far can obtain the relation of the input X (n) and the output Y (n) of sampling rate converter: the every bit of output signal Y (n) can be by 4 expressions of input signal X (n).On time shaft, the relation derivation of these four input points and output point is as follows:

The pairing time point of output signal Y (8*k+i) (0＜=i＜=7) is:

t _8*k+i＝(8*k+i)*9*T-15*T＝72*k*T+9*i*T-15*T，

Wherein T is the cycle of Y1 (n), and 15*T is the group delay of low pass filter 22.

Four pairing time points of input signal are:

t _9*k+i＝(9*k+i)*8*T＝72*k*T+8*i*T

t _9*k+i-1＝(9*k+i-1)*8*T＝72*k*T+8*i*T-8*T

t _9*k+i-2＝(9*k+i-2)*8*T＝72*k*T+8*i*T-16*T

t _9*k+i-3＝(9*k+i-3)*8*T＝72*k*T+8*i*T-24*T

Can obtain: X (9*k+i-j) (0＜=j＜=3) is four points of the most close Y (8*k+i) just.Therefore the physical meaning of front input/output relation formula is exactly: each output point can be obtained by the most close its weighted sum of four input points.

Fig. 3 has disclosed the circuit structure of the sampling rate converter of realizing above-mentioned derivation, the utility model sampling rate converter comprises input buffer 31, heterogeneous selector 32, adder array 33 and output buffer 34, wherein input buffer 31 is used for buffer memory primary signal X[n], its internal structure is as shown in Figure 4: comprise that (the signal bit wide is 10bits for mould 9 counters 310 and 9x10bits memory 311, therefore corresponding memory 311 also to need to select 10bits be a storage cell), wherein mould 9 counters 310 are used to produce 4 bit address signals; 311 of memories are used for buffer memory primary signal X[n], it is output as R0 to R8, corresponds respectively to 9 unit of memory.Heterogeneous selector 32 is used for selecting from input buffer 1 data of participation back add operation, its internal structure is as shown in Figure 5: the data selector 330 that comprises mould 8 counters 320 and four groups of 10bits, mould 8 counters 320 are used to characterize the phase position index of the value of current calculating, be Y[8*k+i] in i, data selector 330 is used for from R0 to R8 selecting four data, and (D0～D3) participates in the add operation of back.Adder array 33 is used to realize the weighted sum of primary signal X (n), the H[n that promptly realizes in the aforementioned formula being disclosed] and X[n] multiply-add operation, thereby obtain Y[n].Output buffer 4 is used to export purpose signal Y (n).

That disclosed among Fig. 2, Fig. 3, Fig. 4, Fig. 5 is the embodiment that signal is transformed into the sampling rate converter of 24MHz from 27MHz.For the sample rate signal that is F, through a L/M sampling rate converter, the data processing stream that can summarize the utility model sampling rate converter after summarizing according to last data volume embodiment with and advantage:

Step 1, accept primary signal, and be kept in the input buffer 31.

Step 2, employing zero insertion method rise the L frequency multiplication to primary signal.

Step 3, the signal behind the raising frequency is carried out anti-aliasing filter.According to some characteristic indexs of sampling rate converter, determine the type and the coefficient of filter.The realization of general filter needs a large amount of memory cell and arithmetic element, and the utility model interpolation arithmetic device advantage be: according to some features in the sampling rate converter filter construction is carried out a large amount of abbreviations, thereby significantly reduces memory cell and arithmetic element.Can know that by step 1 entering has L-1 zero in continuous L of the signal point of this filter, and zero multiply by any number and equal zero, any number adds that zero equals itself.The essence of filter is to realize the convolution and the computing of input signal and coefficient, and therefore in the computing formula of filter, every L item product can be eliminated the L-1 item.That is to say that for a filter that N coefficient arranged, it needs N group memory cell, N multiplier and N-1 adder.And after considering elimination zero item, need K group memory cell, K multiplier (multiplying can realize by adder generally speaking) and K-1 adder, wherein K is the smallest positive integral more than or equal to N/L, and the cost of being paid is exactly to have increased K group L to select one data selector 330.

Step 4 is fallen M frequently to signal after the filtering.Be only to get 1 point in every M point in the signal, and lose remaining M-1 point, the signal that obtains like this is exactly through the signal after the sample rate conversion.Can find thus, in the output of filter, only needing to calculate a point in every M the point gets final product, in step 2, there is no need fully to calculate for the point that in this step, needs to lose, therefore can carry out abbreviation to filter again, the operating frequency that is filter is (L/M) * A, rather than L*A.

Obviously, the utility model interpolation arithmetic device is selected by 330 pairs of data of the data selector in the heterogeneous selector 32 after adopting zero insertion method raising frequency, makes the number of adder save greatly, and cost decreases.

The foregoing description only is one of them embodiment of the present utility model, under the prerequisite that does not break away from the utility model aim, those skilled in the art can also make the change of many equivalences according to the foregoing description, and these changes all should be included in the claim restricted portion.

Claims (5)

1, sampling rate converter comprises:

The input buffer that is used for the buffer memory primary signal;

Adder array;

Be used for output buffer that the operation result of adder array is exported as the purpose signal;

It is characterized in that:

A heterogeneous selector that is connected between input buffer and the adder array, is used for selecting data from input buffer.

2, sampling rate converter according to claim 1 is characterized in that: described input buffer comprises that mould is the counter of M and the memory of M unit.

3, sampling rate converter according to claim 2, it is characterized in that: comprise in the heterogeneous selector that data selector and mould are the counter of L, this data selector is selected data from the output of input buffer, and exports to and carry out computing in the adder array.

4, sampling rate converter according to claim 2 is characterized in that: described counter is mould 9 counters.

5, sampling rate converter according to claim 3 is characterized in that: described counter is mould 8 counters.

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