CN110957996A - Multiplier-free FRM filter bank optimization design method based on ABC algorithm - Google Patents
Multiplier-free FRM filter bank optimization design method based on ABC algorithm Download PDFInfo
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Abstract
The invention relates to an ABC algorithm-based multiplier-free FRM filter bank optimization design method, which comprises the following steps: acquiring passband cut-off frequency and cut-off starting frequency index parameters of a prototype filter, an upper branch shielding filter and a lower branch shielding filter in an FRM narrow-band filter bank according to actual requirements; calculating to obtain initial coefficient vectors of each filter in an FRM (fast Fourier transform) polyphase analysis filter bank by combining a frequency sampling method and indexes of each filter; and (3) taking each filter coefficient in the step (2) as an initial bee source of the artificial bee colony algorithm, and performing comprehensive optimization operation on the coefficient by using the artificial bee colony algorithm to finally obtain the overall optimal filter coefficient design. The FRM filter bank structure adopts the artificial bee colony algorithm to optimize the performance of the prototype filter and further reduce the number of adders. Meanwhile, the filter coefficient is optimized by the artificial bee colony algorithm in advance, and effect errors caused by CSD coding of the filter coefficient are reduced.
Description
Technical Field
The invention relates to the field of radio and digital signal processing application thereof, in particular to the field of an optimization design method of a multiplier-free FRM filter bank based on an ABC algorithm.
Background
With the development of multi-rate signal processing technology, filter banks have been widely used in the fields of digital communication, image processing, signal processing, and the like. As algorithms continue to be developed and improved, filter bank techniques are favored for wideband receivers and for image and video processing. The filter bank is not only an important factor determining the performance of the digital channelization processing, but also has an excellent application position in the military industry, and occupies an important position in satellite signal processing, audio image filtering and radar signal processing. Nowadays, digital channelized receivers have higher and higher requirements on the number of sub-filters in a filter bank and the width of a transition band, and a Frequency-response masking (FRM) technology provides an effective method for designing a narrow transition band filter bank with low complexity. Therefore, how to stably utilize the FRM technology to realize the hardware design of the narrow-transition-band filter bank puts higher requirements on the occupied amount of hardware resources and the processing speed.
In the aspect of designing an optimized multiplier-free filter bank, the patent No. 998093866 digital filtering without multipliers adopts a method of directly quantizing filter coefficients, which is different from the structural design of the invention; the literature, "application research of artificial bee colony algorithm in FIR filter design" (information recording material, 2019) mainly studies a bee colony optimization method for a low-pass filter, but the method is not further converted into hardware implementation without a multiplier, is not designed for a filter bank, and is different from the method disclosed by the invention; the document "low complexity HBCEM FRM polyphase filter bank" (data acquisition and processing, 2011) mainly integrates the FRM filter by using a half-band complex index modulation technique to realize the efficient design of the filter, but does not adopt an optimization algorithm and a design without a multiplier, which is different from the method of the present invention; the document "research and application of low-complexity finite impulse response filter design method" (master paper of southeast university, 2018) mainly performs optimization design on an FRM filter based on a design algorithm of a reconfigurable frequency-mask filter optimized by a second-order cone, does not relate to design without a multiplier, is not used for structural design of a filter bank, and is different from the patent of the present invention.
Disclosure of Invention
The invention aims to provide an optimized design method of a multiplier-free FRM filter bank based on an ABC algorithm.
The invention is realized by the following steps:
an optimized design method of a multiplier-free FRM filter bank based on an ABC algorithm comprises the following steps:
(1) acquiring passband cut-off frequency and cut-off starting frequency index parameters of a prototype filter, an upper branch shielding filter and a lower branch shielding filter in an FRM narrow-band filter bank according to actual requirements;
(2) calculating to obtain initial coefficient vectors of each filter in an FRM (fast Fourier transform) polyphase analysis filter bank by combining a frequency sampling method and indexes of each filter;
(3) taking each filter coefficient in the step 2 as an initial bee source of the artificial bee colony algorithm, and performing comprehensive optimization operation on the coefficient by using the artificial bee colony algorithm to finally obtain the overall optimal filter coefficient design;
(4) carrying out regular signed number coding on the optimal filter coefficient to complete the optimization quantization process of the FRM polyphase filter bank coefficient;
(5) respectively carrying out circuit design on the coefficients of the FRM polyphase filter bank after coding in a shift addition mode;
(6) for the filter bank circuit design, a distributed structure is adopted.
In the step (1), the unit sampling response of the prototype filter H (z) is h (n), the frequency band is from-pi/M to pi/M, and the analysis filterGroup neutron filter Hk(z) has a unit sample response of hk(n)，hk(n) is h (n) obtained by complex modulation with a modulation factor of
hkThe relationship between (n) and h (n) is:
filter hkThe Z transform expression of (n) is:
where M is the number of channels, the modulation factor
Can be determined by a rotation factor
And (4) expressing.
In the step (2), the initial coefficient vector h (n) of the filter is:
wherein ,
Hd(ejω) Is a periodic function of the continuous frequency ω, which is the frequency response of an ideal filter.
In step 3, the filter coefficient optimization fitness formula of the artificial bee colony algorithm is as follows:
wherein ,ωp(P-0, 1, …, P-1) is in the range [ - π, π]And taking P frequency sampling points.
The invention has the beneficial effects that: the FRM filter bank structure designed by the invention optimizes the performance of a prototype filter by adopting an artificial bee colony algorithm, and simultaneously optimizes the structure by utilizing the design idea without a multiplier. After CSD coding is carried out on the coefficient of each filter in the FRM polyphase analysis filter bank, the traditional filter coefficient multiplier is replaced by 'shifting' and 'adding and subtracting', and meanwhile, the number of adders is further reduced. Meanwhile, the filter coefficients are optimized by the artificial bee colony algorithm in advance, so that effect errors caused by CSD coding of the filter coefficients are reduced, hardware resource consumption is reduced, the calculation speed is increased, and the performance of the filter bank structure is maintained.
Drawings
FIG. 1 is a flow chart of the optimization design of a multiplier-free FRM filter bank based on the ABC algorithm of the present invention;
FIG. 2 is a block diagram of a FRM filter employed in the present invention;
fig. 3 is a structural diagram of a FRM-based filter bank according to the present invention;
FIG. 4 is a flow chart of the ABC algorithm optimization employed in the present invention;
FIG. 5 is a block diagram of a sequential implementation of partial coefficient product terms in accordance with the present invention;
FIG. 6 is a diagram of the additive combination of coefficient product terms after being optimized by regular expressions in the present invention;
FIG. 7 is a diagram of a distributed algorithm architecture employed by the present invention;
FIG. 8 is a flow chart of the filter bank structural design employed in the present invention;
FIG. 9 is a graph of the amplitude-frequency characteristics of an ABC algorithm optimized prototype filter employed in the present invention;
FIG. 10 is a graph of the amplitude-frequency characteristic of an ABC algorithm optimized upper-branch shielding filter employed in the present invention;
FIG. 11 is a graph of the amplitude-frequency characteristics of the lower branch shielding filter optimized by the ABC algorithm employed in the present invention;
FIG. 12 is a simulation diagram of the output results of a 16-channel filter bank provided in the present invention;
FIG. 13 is a block diagram of the shift and add block of the distributed architecture of a single filter in the present invention;
FIG. 14 is a diagram of the data bit flow and lookup module for the distributed architecture of a single filter in the present invention;
FIG. 15 is a resource comparison diagram of the FRM filter bank without multiplier according to the present invention.
Detailed Description
The present invention is described in further detail below with reference to the attached drawing figures.
The invention belongs to the field of software radio and digital signal processing application thereof, and particularly relates to an optimal design method of a multiplier-free FRM filter bank based on an Artificial Bee Colony (ABC) algorithm.
The invention aims to provide an optimized design method of a multiplier-free FRM filter bank based on an ABC algorithm. The specific implementation process of the invention is as follows:
step 1: acquiring passband cut-off frequency and cut-off starting frequency index parameters of a prototype filter, an upper branch shielding filter and a lower branch shielding filter in an FRM narrow-band filter bank according to actual requirements;
step 2: calculating to obtain initial coefficient vectors of each filter in an FRM (fast Fourier transform) polyphase analysis filter bank by combining a frequency sampling method and indexes of each filter;
and step 3: taking each filter coefficient in the step 2 as an initial bee source of the artificial bee colony algorithm, and performing comprehensive optimization operation on the coefficient by using the artificial bee colony algorithm to finally obtain the overall optimal filter coefficient design;
and 4, step 4: carrying out regular Signed Digit (CSD) encoding on the optimal filter coefficient to complete the optimization quantization process of the FRM multiphase filter bank coefficient;
and 5: respectively carrying out circuit design on the coefficients of the FRM polyphase filter bank after coding in a shift addition mode;
step 6: for the filter bank circuit design, a distributed structure is adopted.
The FRM filter bank structure designed by the invention optimizes the performance of a prototype filter by adopting an artificial bee colony algorithm, and simultaneously optimizes the structure by utilizing the design idea without a multiplier. After CSD coding is carried out on the coefficient of each filter in the FRM polyphase analysis filter bank, the traditional filter coefficient multiplier is replaced by 'shifting' and 'adding and subtracting', and meanwhile, the number of adders is further reduced. Meanwhile, the filter coefficients are optimized by the artificial bee colony algorithm in advance, so that effect errors caused by CSD coding of the filter coefficients are reduced, hardware resource consumption is reduced, the calculation speed is increased, and the performance of the filter bank structure is maintained.
The invention is further described as follows:
the invention relates to an ABC algorithm-based multiplier-free FRM filter bank optimization design method, which comprises the following overall design flow:
step 1: acquiring passband cut-off frequency and cut-off starting frequency index parameters of a prototype filter, an upper branch shielding filter and a lower branch shielding filter in the FRM multi-phase analysis filter bank according to actual requirements;
step 2: calculating the initial coefficient vector of each filter by combining the frequency sampling method and the indexes of each filter;
and step 3: taking each filter coefficient in the step 2 as an initial bee source of the artificial bee colony algorithm, and performing comprehensive optimization operation on the coefficient by using the artificial bee colony algorithm to finally obtain the overall optimal filter coefficient design;
and 4, step 4: carrying out regular signed number CSD coding on the optimal filter coefficient to complete the optimization quantization process of the FRM filter coefficient;
and 5: respectively carrying out circuit design on the encoded filter coefficients in a shift addition mode;
step 6: for the filter coefficient circuit calculation, distributed structure operation is adopted.
The optimization design method is characterized in that circuit design is carried out on a Xilinx System Generator platform by means of MATLAB, a shift module and an addsub module in the platform are used for completing the shifting and adding part of algorithm design, and an M-code module, a bitshare module and an MATLAB code are combined to complete the bit splitting and look-up table functions of data in a distributed structure.
Firstly, the coefficients of a prototype filter, an upper branch shielding filter and a lower branch shielding filter in an FRM multi-phase analysis filter bank are obtained by using a frequency extraction method, and then, the coefficients of each bank are subjected to iterative optimization by using an artificial bee colony algorithm. And then, carrying out iterative optimization on each group of coefficients by using an artificial bee colony algorithm. Performing CSD coding on the optimized filter coefficient, wherein the specific form is N-a 20+a22…a2m. And finally, the coding result of the coefficient is used as the design basis of the multiplier-free circuit. This method can consume the least adder with less precision error.
The method comprises the following steps: the method adopts a distributed structure, the coefficient data after CSD coding corresponds to the input data of the filter, the multiplication operation of the original data and the filter coefficient is converted into the shift addition operation of the data according to a lookup table, and finally the hardware circuit design is carried out. The distributed multiplier-free structure can further reduce the quantity of lookup tables and registers in the hardware design of the optimized FRM filter bank.
As shown in fig. 1, the invention provides an FRM filter bank optimization design method based on ABC algorithm optimization and multiplier-free design, which is characterized in that: and performing iterative optimization on the coefficients of each branch prototype filter, the upper branch shielding filter and the lower branch shielding filter in an FRM filter bank in the multiphase structure by using an ABC algorithm, performing CSD coding on the optimized filter coefficients, and converting the multiplication operation of the data and the filter coefficients into the self-shifting and addition operation of the data by using an adder and a shifter. When the filter is used for circuit design of shift addition, a distributed structure module design is introduced, and finally data output processed by the filter is obtained.
The analysis filter bank may split one complete signal into a plurality of sub-signals. However, under the condition that the number of sub-bands is relatively large or the sampling rate is relatively high, the resource demand of hardware is greatly increased, which is not beneficial to engineering implementation, so that an analysis filter bank based on a multiphase structure is usually adopted. Analyzing M (where M is the number of channels) partitions in a filter bankOne design method of the analysis filter is to design the analysis filters respectively under the optimal condition, and the other method is to design a prototype low-pass filter and then modulate the prototype low-pass filter to obtain the analysis filters of each sub-band, so that the design of the filter can be simplified. Let the unit sampling response of the prototype low-pass filter H (z) be h (n), and the frequency band be from-pi/M to pi/M. Analysis filter bank neutron filter Hk(z) has a unit sample response of hk(n)，hk(n) is h (n) obtained by complex modulation with a modulation factor of
hkThe relationship between (n) and h (n) is:
filter hkThe Z transform expression of (n) is:
wherein the modulation factor
Can be determined by a rotation factor
And (4) expressing.
The analysis filter bank can be simplified using the polyphase representation of the filter, thereby reducing the amount of computation. Firstly to Hk(z) performing a heterogeneous decomposition:
rotation factor
This can be achieved by means of an M-point Inverse fourier transform (IDFT), the time domain being denoted by the index l and the frequency domain by the index k. In order to reduce the sampling rate of the sub-filters in the analysis filter bank, we use Noble identity theory to move the D-fold decimation module in front of the sub-filters, so we can obtain the expression of the transformed sub-filters:
and obtaining the structure of the polyphase analysis filter bank. FRM technology can be utilized to be combined with a polyphase analysis filter bank structure, and lower calculation complexity is obtained while the target of a narrow transition band is achieved. The basic structure of the FRM filter is shown in fig. 2, and the expression of the known FRM filter is:
H(z)＝Fa′(z)FMa(z)+Fc′(z)FMc(z) (6)
wherein ,F′a(z) and F′c(z) is for the prototype low-pass filter Fa(z) and its complementary filter Fc(z) obtaining a filter after L-times interpolation, Fa(z) and Fc(z) all have a length of NaAnd satisfy the relational expression
FMa(z) and FMc(z) are each of length NMa and NMcThe shielding filter of (1).
To shielding filter FMa(z) and FMc(z) by performing a multiphase representation, one can obtain:
substituting the formula (7) and the formula (8) into the formula (6), and combining with the above polyphase analysis filter bank formula to make the interpolation factor L equal to an integer multiple of M, so as to obtain an FRM polyphase analysis filter bank formula as follows:
the final FRM-based analysis filterbank structure is shown in fig. 3.
An ordered long sequence can be accurately recovered by a limited number of samples of the spectrum, provided that the nyquist sampling theorem condition of the frequency domain can be satisfied. Frequency sampling methods FIR digital filters can be designed using a finite number of sample point recovery methods. Frequency response H of a known ideal filterd(ejω) For the periodic function of the continuous frequency ω, H can be considered, assuming that it is necessary to design a filter of order Nd(ejω) Sampling N points at equal intervals in the range of 0 to 2 pi to obtain Hd(k) The relation between the two is as follows:
to Hd(k) By performing IDFT operation, a unit sampling sequence h (N) of N points can be obtained, namely:
wherein h (n) is the coefficient of the designed filter. In order to optimally design each filter in the FRM filter structure, it is necessary to design a prototype filter, an upper-branch shield filter, and a lower-branch filter in the FRM structure by using a frequency sampling method.
The coefficients of a prototype filter, an upper branch filter and a lower branch filter which are respectively h can be obtained by the design of a frequency sampling methoda(n)、hma(n) and hmc(n) of (a). The filter coefficients obtained by the ordinary frequency decimation method do not necessarily allow the designed filter to achieve the best filtering performance,therefore, the artificial bee colony algorithm can be used for carrying out iterative optimization operation on the three filter coefficients in the FRM structure. The artificial bee colony algorithm can use the filter coefficient obtained by a frequency sampling method as an initial value, and iterative computation is carried out on the initial value according to a given fitness criterion by using the worker bees, the observation bees and the detection bees in the algorithm until a global optimal value with the lowest fitness is found. The optimized filter has better stop band attenuation performance and can relieve quantization errors brought by coefficient integer quantization in the following steps to a certain extent. Wherein in [ - π, π]Get P frequency sampling points omegap(P-0, 1, …, P-1), the fitness formula for filter coefficient optimization is shown in formula (12), and the artificial bee colony algorithm optimization process is shown in fig. 4.
After obtaining the global optimal coefficient data of each filter in the FRM polyphase analysis filter bank, in order to achieve multiplier-free design of the filter bank, the original fractional coefficients need to be subjected to integer quantization. The conventional method shifts the coefficients left by M bits, rounds them to an integer and decomposes them by the power of 2. However, if the number of 1 in the decomposition result is increased, the number of times of addition to be performed is increased, and the CSD representation method is applied, the number of non-zero elements can be reduced, the number of times of addition is reduced in the operation, and therefore the operation speed is improved, and the resource occupation is reduced. The regular CSD code representation is different from the traditional binary code representation, the regular code has triple values, and the numerical value range is {0,1, -1}, -1 can also be written as
In this example, assuming that the value of a certain coefficient is 31, the normal power-2 decomposition and CSD coding are as shown in formula (13), the sequential implementation structure of the partial product terms of the following formula operation is as shown in fig. 5, and the addition combination of the optimized product terms is as shown in fig. 6.
Multiplication of coefficients by the input signal in the filter can be converted into a calculation of a shift and an addition of the input signal itself. In a hardware implementation, the occupation of the multiplier can be converted into the occupation of the shifter and the adder, and although the method can reduce the hardware calculation time, the occupation of the register and the adder is increased to a certain extent. In order to further optimize the occupied resources of hardware implementation while reducing the hardware calculation time of the filter, a novel distributed algorithm structure can be used for further optimizing the filter after CSD coding.
The novel distributed architecture principle will be described below with a simple fourth order FIR filter. Assuming a filter of general length K, it can be expressed as:
where x and y are two input and output vectors of length K, akIs the filter coefficient sequence, and K is the number of taps of the filter. In a bit sequence based distributed structure, representing the input signal x as a binary expression of length L may result in expression (15):
substituting equation (15) into (14) can yield:
wherein b is equal to {0,1}, the value of the item in the formula bracket can be 2 through (16)KOne of the values, these binary expressions, is mapped one-to-one with the additive form of the corresponding coefficient. Since the binary expression in brackets is predictable, the sum of the corresponding coefficients can be stored in the look-up table in advance, and the input signal is based on the translated result bk,lAnd searching a corresponding numerical value for subsequent calculation, wherein the structure diagram of the distributed algorithm is shown in FIG. 7.
The flow chart of the FRM filter bank structure based on the combination of ABC algorithm optimization and multiplier-free design obtained by the invention is shown in FIG. 8.
The invention relates to an FRM filter bank design method based on combination of ABC algorithm optimization and multiplier-free design, which mainly comprises the following steps:
step 1: and the artificial bee colony algorithm optimization module calculates initial coefficients of all filters of the FRM multi-phase analysis filter bank by using a frequency sampling method, and then performs iterative optimization on the filter coefficients according to a given fitness formula by using an artificial bee colony algorithm to finally obtain a globally optimal coefficient solution set of all the filters.
Step 2: and the coefficient CSD coding module is used for carrying out integer quantization on the optimal coefficient of the filter according to N bits after obtaining the optimal coefficient of the filter, and carrying out CSD coding on each data after obtaining the integer expression of the coefficient.
And step 3: and the distributed structure module is used for carrying out circuit design of a multiplier-free distributed structure on the filters by using the shifter, the adder and the lookup table after obtaining the CSD coding expressions of the filters.
For the FRM prototype filter optimized by the artificial bee colony algorithm, simulation results of the upper branch shielding filter and the lower branch shielding filter are respectively shown in fig. 9, fig. 10 and fig. 11, in this example, the normalized passband cut-off frequency and the stopband starting frequency of the prototype low-pass filter are respectively 0.468 and 0.532, the normalized passband cut-off frequency and the stopband starting frequency of the upper branch shielding filter are respectively 0.077125 and 0.108375, the normalized passband cut-off frequency and the stopband starting frequency of the lower branch shielding filter are respectively 0.047875 and 0.079125, filter design is performed according to 64 th order, 128 th order and 128 th order by adopting a classical frequency sampling method and an ABC-based optimized frequency sampling method, and the optimized filter coefficients are quantized and subjected to CSD encoding. The iteration number of the ABC algorithm is 300 times, the number of worker bees and detection bees is 100 in total, and the value range of the honey source is [ -1,1]. Compared with the filter with the common design, the prototype filter and the shielding filter which are optimized by the ABC algorithm have lower minimum stop band attenuation. Wherein the algorithm is in a masking filter FMa(z) optimizationThe best results are achieved with a minimum stop-band attenuation of less than 20dB compared to the common design method, followed by the prototype filter Fa(z), after algorithm optimization, the reduction is 15dB compared with the common method, and the reduction is carried out on a shielding filter FMcCompared with the common design method, the ABC algorithm adopted in the step (z) is reduced by 5 dB. Meanwhile, the filter passband after the ABC algorithm is optimized is flatter than that of a filter designed by a common method, so that the superiority of the artificial bee colony algorithm optimization design is verified.
The overall simulation result of the 16-channel FRM filter bank is shown in fig. 12, in this example, the input signal is a 100MHz sinusoidal signal and a chirp signal with a center frequency of 55MHz and a frequency range of 45-65 MHz. Simulation results show that the overall design can detect corresponding signal spectrum peaks in corresponding channels 1, 2 and 14, and therefore the accuracy of the overall design is verified.
The design takes low-resource calling and low-delay as the main design direction, and achieves the aim of low-resource calling and low-delay through the improvement of the algorithm and the optimization of the circuit structure. The hardware validation of the design was designed and implemented on the Xilinx SystemGenerator platform of MATLAB software. The shift and add module of the distributed structure of a single filter is shown in fig. 13, and mainly utilizes the shift module and the addsub module to complete the shift and add functions. The construction of the data bit stream and the lookup module in the distributed structure is shown in fig. 14, and firstly, the bitshare module is used to complete the bit splitting function of the data, and secondly, the M-code module is mainly used to complete the lookup table function in the distributed structure. The M-code module can convert the written simple MATLAB code for executing the judgment function into a hardware design language to complete the design function. The individual addition instances of the coefficients can therefore be listed for storage in the M-code module in the form of MATLAB code. After the XilinxSystem Generator is built, the functional module can be connected to VIVADO software for resource evaluation. The resource use condition of the design after being integrated in the VIVADO software is as follows: the chip model used in the whole design is XC7VX690tffg1157-1, the FRM filter is optimally designed in the optimal design, the normalized passband cut-off frequency and the stopband starting frequency of the filter are 0.077125 and 0.079125 respectively, 21003 units are used in a lookup table displayed in VIVADO, 26646 units are used in a register, and the delay of an average circuit is 2.06 ns. The present design is aligned with the conventional multiplier-less FRM polyphase analysis filter bank approach as shown in fig. 15. It can be seen that the present invention saves more resources and has less path delay than the common multiplier-free filter bank.
In summary, the present invention provides an optimized design method for an FRM filter bank without multiplier based on Artificial Bee Colony (ABC) algorithm, which comprises the following specific implementation steps: firstly, the coefficients of a prototype filter, an upper branch shielding filter and a lower branch shielding filter in an FRM multi-phase analysis filter bank are obtained by using a frequency extraction method, and then the ABC algorithm is used for carrying out iterative optimization on each group of coefficients. And performing regular expression Coding (CSD) on the optimized filter coefficient, converting the multiplication operation of the data and the filter coefficient into self-shifting and addition operation of the data by utilizing an adder and a shifter, and further reducing the required shifter and the adder by adopting a distributed structure in the hardware realization. The invention optimizes the filter coefficient in the FRM filter bank structure by ABC algorithm and processes without multiplier, which not only reduces the operation amount and hardware resource loss, but also improves the processing speed of FRM filter hardware realization, and reduces the filter coefficient quantization error brought by integer quantization. The optimization design method provided by the invention has the characteristics of small calculated amount and low time delay.
Claims (4)
1. An optimization design method of a multiplier-free FRM filter bank based on an ABC algorithm is characterized by comprising the following steps: the method comprises the following steps:
(1) acquiring passband cut-off frequency and cut-off starting frequency index parameters of a prototype filter, an upper branch shielding filter and a lower branch shielding filter in an FRM narrow-band filter bank according to actual requirements;
(2) calculating to obtain initial coefficient vectors of each filter in an FRM (fast Fourier transform) polyphase analysis filter bank by combining a frequency sampling method and indexes of each filter;
(3) taking each filter coefficient in the step 2 as an initial bee source of the artificial bee colony algorithm, and performing comprehensive optimization operation on the coefficient by using the artificial bee colony algorithm to finally obtain the overall optimal filter coefficient design;
(4) carrying out regular signed number coding on the optimal filter coefficient to complete the optimization quantization process of the FRM polyphase filter bank coefficient;
(5) respectively carrying out circuit design on the coefficients of the FRM polyphase filter bank after coding in a shift addition mode;
(6) for the filter bank circuit design, a distributed structure is adopted.
2. The method of claim 1 for optimal design of FRM filter bank without multiplier based on ABC algorithm, wherein: in the step (1), the unit sampling response of the prototype filter H (z) is H (n), the frequency band is from-pi/M to pi/M, and the sub-filter H in the analysis filter bank isk(z) has a unit sample response of hk(n)，hk(n) is h (n) obtained by complex modulation with a modulation factor of
hkThe relationship between (n) and h (n) is:
filter hkThe Z transform expression of (n) is:
where M is the number of channels, the modulation factor
Can be determined by a rotation factor
And (4) expressing.
3. The method of claim 1 for optimal design of FRM filter bank without multiplier based on ABC algorithm, wherein: in the step (2), the initial coefficient vector h (n) of the filter is:
wherein ,
Hd(ejω) Is a periodic function of the continuous frequency ω, which is the frequency response of an ideal filter.
4. The method of claim 1 for optimal design of FRM filter bank without multiplier based on ABC algorithm, wherein: in step 3, the filter coefficient optimization fitness formula of the artificial bee colony algorithm is as follows:
wherein ,ωp(P-0, 1, …, P-1) is in the range [ - π, π]And taking P frequency sampling points.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022095856A1 (en) * | 2020-11-04 | 2022-05-12 | 中兴通讯股份有限公司 | Filtering method, server and storage medium |
| CN115955217A (en) * | 2023-03-15 | 2023-04-11 | 南京沁恒微电子股份有限公司 | Low-complexity digital filter coefficient adaptive combined coding method and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1602815A (en) * | 1977-03-09 | 1981-11-18 | Onera (Off Nat Aerospatiale) | Recursive digital filter having coefficients equal to sums of few powers of two terms |
| CN107682096A (en) * | 2017-09-14 | 2018-02-09 | 大连理工大学 | A kind of narrowband random signal creating method based on multilevel interpolation |
| CN109359267A (en) * | 2018-10-18 | 2019-02-19 | 哈尔滨工程大学 | A kind of low complex degree multiplier-less fixed point FFT optimization method based on dynamic cut position |
| CN110210101A (en) * | 2019-05-27 | 2019-09-06 | 哈尔滨工程大学 | A kind of non-homogeneous narrow transition band filter group of dynamic based on CEM FRM and design method |
| CN110365312A (en) * | 2019-06-21 | 2019-10-22 | 杭州电子科技大学 | The heterogeneous structure and its factor design method of two channel quadrature mirror filter groups |
-
2019
- 2019-12-13 CN CN201911280875.0A patent/CN110957996B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1602815A (en) * | 1977-03-09 | 1981-11-18 | Onera (Off Nat Aerospatiale) | Recursive digital filter having coefficients equal to sums of few powers of two terms |
| CN107682096A (en) * | 2017-09-14 | 2018-02-09 | 大连理工大学 | A kind of narrowband random signal creating method based on multilevel interpolation |
| CN109359267A (en) * | 2018-10-18 | 2019-02-19 | 哈尔滨工程大学 | A kind of low complex degree multiplier-less fixed point FFT optimization method based on dynamic cut position |
| CN110210101A (en) * | 2019-05-27 | 2019-09-06 | 哈尔滨工程大学 | A kind of non-homogeneous narrow transition band filter group of dynamic based on CEM FRM and design method |
| CN110365312A (en) * | 2019-06-21 | 2019-10-22 | 杭州电子科技大学 | The heterogeneous structure and its factor design method of two channel quadrature mirror filter groups |
Non-Patent Citations (5)
| Title |
|---|
| MANJU MANUEL等: "Design of frequency response masking FIR filter in the Canonic Signed Digit space using modified Artificial Bee Colony algorithm" * |
| MANJU MANUEL等: "Design of Multiplier-less FRM FIR Filter Using Artificial Bee Colony Algorithm" * |
| V.J. MANOJ等: "Artificial bee colony algorithm for the design of multiplier-less nonuniform filter bank transmultiplexer" * |
| 刘晓丽;兰英;: "基于人工蜂群算法的FIR数字滤波器设计" * |
| 赵岸;颜毅华;陈林杰;刘东浩;王威;陈志军;: "基于FPGA的高速FIR数字滤波器设计的改进方法" * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022095856A1 (en) * | 2020-11-04 | 2022-05-12 | 中兴通讯股份有限公司 | Filtering method, server and storage medium |
| CN115955217A (en) * | 2023-03-15 | 2023-04-11 | 南京沁恒微电子股份有限公司 | Low-complexity digital filter coefficient adaptive combined coding method and system |
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