GB1602815A - Recursive digital filter having coefficients equal to sums of few powers of two terms - Google Patents

Description

(54) RECURSIVE DIGITAL FILTER HAVING COEFFICIENTS EQUAL TO SUMS OF FEW POWERS OF TWO TERMS (71) We, OFFICE NATIONAL D'ETUDES ET DE RECHERCHES AEROSPATIALES DIT O.N.E.R.A., a French Body Corporate, of 29 Avenue de la Division Leclerc, 92320 Chatillon- sous-Bagneux, France, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention concerns, generally speaking, digital filtering and centres around a recursive digital filter which delivers, from digitized samples of an analog input signal, a series of numbers representing the digitized values of the filtered analog signal.More particularly, the invention concerns low-pass, highpass or rejection recursive digital filters the recurrence relationship coefficients of which are formed by a sum of a small number of integral powers of two. More precisely, these coefficients have the form of a sum of at most three terms 2U+2v+2Z where u, v and z are integers.

In accordance with the present invention there is provided a recursive digital filter deriving the sample of a filtered output signal at a present sampling instant from samples at said present sampling instant and two preceding consentive sampling instants of a first signal which is either an input signal to be filtered or an auxiliary signal having as one of its components the said input signal and at two preceding consecutive sampling instants and from samples at said two preceding consecutive sampling instants of a second signal which is either the filtered output signal or said auxiliary signal, said filter comprising:: first second and third first signal store means for storing the samples of said first signal, respectively at said present sampling instant and at said two preceding consecutive sampling instants; fourth and fifth second signal store means for storing the samples of said second signal, respectively at said two preceding consecutive sampling instants; first, second and third multiplier units for respectively multiplying the samples contained in said first second and third first signal store means; fourth and fifth multiplier units for respectively multiplying the samples contained in said fourth and fifth second signal store means;; said first, second, third, fourth, and fifth multplier units being multipliers by either a single coefficient equal to an integral power of two or sums of coefficients each equal to an integral power of two, said integral power including the zero power of two, the sums comprising at most three coefficients, there being an effective further multiplication of all the samples by 2-" where n is a positive integer at least equal to 5; an output adder means having inputs connected to said first, second and third multiplier units and selectively to said fourth and fifth multiplier units and an output delivering said filtered output signal; an optional input adder means having inputs connected to said fourth and fifth multiplier units and receiving the input signal and an output delivering said auxiliary signal.

In accordance with an embodiment of the invention, the recursive digital filter is a second order one with a damping coefficient n equal to 1/4, of the Butterworth type. Another preferential embodiment refers to a first order recursive digital filter with coefficients of integral powers of two.

A further preferred embodiment concerns second order recursive digital filters with coefficients in reduced numbers of powers of two and for which the damping coefficient n can equal in particular, 0, 1/2, 1/ and 1, and more generally 2k'2 where k is an integer.

Other embodiments of the present invention can make it possible to carry out the synthesis of various types of filters such as, for example, those of Bessel, Legendre or Tchebyscheff.

The recursive digital filters of the invention with power of two coefficients have filtering rates in real time a thousand times faster than those achieved with the help of conventional minicomputers equipped with a wired or microprogrammed floating point calculation module.

The time required by the filters of the invention to calculate a filtered point is of the order of a few hundreds of nanoseconds which allows an increased rate of the analog input signal sampling and minimizes the influence of spectrum overlap.

The low calculation time also allows several digital filter modules of a similar or of differing types to be placed in series enabling transfer functions of a more general nature to be obtained.

The filters in the invention can advantageously replace analog filters when the necessary cut-off frequencies are very low. In actual fact, on the strength of their performance, ease of development and cost price, they should find a wide range of applications. wherever the characteristics of the analog filters prove to be insufficient, which is essentially the case of low-pass filtering with very low cut-off frequencies.

The low-pass filtering of measuring signals is analogically poorly resolved once the cut-off frequencies drop below I Hz. The analog filters available, for these frequencies, lack stability and are not easily reproducible as regards to the phase response; moreover, the cost price is high. The digital filters, on the other hand, are well suited to the filtering of very low frequencies: they do not drift and, for a given calculation algorithm, present a perfectly defined phase response.

A digital filter can operate either in delayed time or in real time. It is said to operate in real time if the calculation of a filtered point at a given moment in time only resorts to input analog signal samples corresponding to previous moments in time or equal to the given moment. Furthermore, the calculation time of a filtered point must be less than the sampling period. The advantage of operating in real time is apparent, for instance, in the reduction of the volume of data to be transmitted to a central data processing computer, or else in the possibility of including the data acquisition and pre-processing system in a control loop.

It is a known fact that, if it is desired to sample a signal at a sampling frequency f3, so as to obviate the spectrum overlap phenomena, it is necessary for the signal to be sampled not to present any frequency components greater than fe/2. It is thus essential, before sampling the signal and filtering it digitally, to set about an analog prefiltering process to eliminate the components of the signal with frequencies greater than half the sampling frequency. To clarify our views on the subject, let us take the case of a second order low-pass analog pre-filtering stage with a cut-off frequency of 10 Hz and with a -40 dB per decade attenuation.We then find that, to digitally filter frequency components of the signal with a given accuracy of 10-2, 10-3 or 10-4, for instance, we have to keep the frequencies below 100, 300 or 1000 Hz respectively in the analog pre-filtering stage. This imposes sampling frequencies f,, of 200, 600 and 2000 Hz respectively.

Description of the Prior Art E. Haziza and J. Appel's article called "The real time filtering of measurements carried out in the wind-tunnel" (NT Office National d'Etudes et de Recherches Aerospatiales, 3/7146 PY) shows to what extent a minicomputer used for measurement, data acquisition and storage is also capable of digitally filtering in real time the signals obtained. The programmed filter is a second order low-pass recursive one and the digital filtering capacity in real time of the minicomputer is 8 measurement channels each sampled 200 times per second.

It at once appears that when the desired accuracy is high (10-4 for example) and the number of channels to be filtered is substantial (of the order of a few tens) such an acquisition and storage minicomputer is no longer able to carry out a real time digital filtering conventionally.

Summary of the Invention The principal object of this invention is to provide a recursive digital filter whose calculation time of a filtered point is considerably reduced relative to those hitherto available. The decrease in the calculation time of the recurrence relationship, and chiefly in the time taken in multiplying, is obtained by replacing the recurrence relationship coefficients by a combination, reduced in number, of powers of two. The multiplications by the recurrence relationship coefficients are then reduced to multiplications by 2" and are carried out by bit shifting.

These multiplications are performed either by multipliers of the shift register type linked to coefficient registers containing the necessary powers of two, or, in a special preferential embodiments, by wiring up to a data transfer "bus" line.

A preferential embodiment of this invention is a second order low-pass recursive digital filter, of the Butterworth type. Before describing this filter in detail, we are going to establish the recurrence relationship and determine what are the best 2" type forms to be given its coefficients.

The analog transfer function of a second order low-pass filter is written:

where p is the Laplace's variable, # is the damping coefficient and w, the angular cut-off frequency. By applying the following conformal transform to the function H (P) l-z-' p= (2) At 1+z' where At is the sampling period and z=eP^t, we obtain the transfer function of the filter in terms of z: A0+A1z-1+A2z-2 H(z)=- (3) l-B1z-1+B2z2 By putting a cAt, the coefficients A0, A1, A2, B, and B2 are defined by the following equations:: a2 A0 (4) 1 +2#α+α A,=2Ao (4') A2=Ao (4") 2(1-α) B, I +2Va+a2 l-2#α+α (6) B 2= (6) 1 +2#α+α2 By calling Eo(z) the output signal of the filter in terms of z and E*(z) the input signal, we know that E0(z) (7) E,(z) and the recurrence relationship can be deduced as E,(z)=B, E,(z)z-'-B ,E,(z)z2+A,Ei(z) +A1E(z)z-1+A2E1(z)z-2 (8) This relationship (8) can be represented graphically by the filter diagram in Figure 1.In Figure 1, the input function Ej(z) is multiplied, via the multiplier circuit 1, by coefficient Ao to give AoEi(z) and, via the multiplier circuit 2 (in fact a delay circuit), by the function z-' to give Ej(z)z-'. The signal Ej(z)z-' is multiplied, via the multiplier circuit 3, by coefficient A, to give A,Ej(z)z-' and, via multiplier circuit 4, by the signal z-' to give E,(z)z-2. The function Ej(z)z-2 is multiplied, via multiplier circuit 5, by coefficient A2 to give A2Ej(z)z-2. The output function Eo(z) is multiplied, via multiplier circuit 6, by z-' to give Eo(z)z-1 which is itself multiplied, via multiplier circuits 7 and 8, to give B,Eo(z)z-1 and Eo(z)z-2 respectively. The function Eo(z)z-2 is multiplied, via multiplier circuit 9, by coefficient (-B2) to give the function -B2E0(z)z-2. The adder circuit 10 adds up the five signals corresponding to the five terms on the right hand side of equation (8) and delivers the output function Eo(z) at its output. The filter diagram in Figure 1 is termed a direct structure diagram because it derives directly from the transfer function (3).

This direct structure is employed by certain preferential embodiments of second order recursive filters with coefficients formed of a reduced number of combinations of powers of two.

If we come back now to equation (7) and introduce an intermediate function F(z) as follows: Eo(z) F(z) H(z)= (9) F(z) Ej(z) then by combining equations (3) and (9), we can write down two coupled functional relationships: E,(z)=F(z)A,e F(z)A,z-'+ F(z)A,z2 (10) F(z)=E,(z)+F(z)B ,z-'-F(z)B,z-2 (11) These two relationships (10) and (11) may be represented graphically by the filter diagram in Figure 2 which is referred to as a canonical structure diagram. In Figure 2, the input function Ej(z) is applied directly to an adder circuit 11 whose output delivers the intermediate function F(z).This functions F(z) is multiplied, via multiplier circuits 12 and 13, by the coefficient Ao and the function z-' respectively to give the respective functions AoF(z) and F(z)z-'. The function F(z)z-' is multiplied, via the multiplier circuits 14, 15 and 16, by the coefficients A, and B, and by the function z-' respectively to give the functions A,F(z)z-', B,F(z)z-' and F(z)z-2. The function F(z)z-2 is multiplied, via the multiplier circuits 17 and 18, by the coefficients A2 and (-B2) respectively to give A2F(z)z-2 and -B,F(z)z2. The adder circuit 11 receives the three functions on the right hand side of equation (11) and delivers, as already mentioned, the intermediate function F(::) at its output.An adder circuit 19 receives the three functions on the right hand side of equation (10) and delivers the output function Eo(z) at its output. This canonic structure in the filter diagram of Figure 2 is employed in certain preferential embodiments of second order recursive digital filters with coefficients formed of a reduced number of combinations of powers of two.

By comparing Figures 1 and 2, it can be seen that the canonic structure of the diagram in Figure 2 contains two z-' multiplier circuits instead of four and two adder circuits instead of one.

In practice, filter designs based on the theoretical diagrams in Figures 1 and 2 would include the same number of multiplier circuits, namely five, and would further comprise four memories plus one adder circuit in the case of the direct structure (Figure 1) and two memories plus two adder circuits in the canonic structure case (Figure 2).

Both the direct structure (Figure 1) and the canonic one (Figure 2) can be built either in a parallel or a series form. In a parallel form, the memories used are registers having as many inputs and as many outputs as the information they contain has bits. Similarly, the adder circuits used in parallel have as many inputs as the information to be added has bits. The multiplications by coefficients equal to powers of two are achieved through wiring by shifting the information pick-ups at the output of the parallel-mounted registers. A multiplication by 2k, for example, is executed by shifting the quantity of k bits towards the left; a multiplication by 2-k is executed by a shift of k bits towards the right.

So as to minimize the size of the parallel-arranged adder circuit used, the shifted information that it must sum up is transmitted to it in succession by means of a bus line. An accumulator is therefore associated with the adder. The filters based on a direct structure in this application are mounted in parallel arrangement.

This parallel arrangement can be transformed into a canonic one with no difficulty. It should be pointed out that a parallel arrangement makes it possible to perform the calculation of a filtered point with maximal rate. In the case of maximum rate being sought, let us look at what structure ought to be adopted so as to minimize the number of components used.

TABLE I

Direct structure Canonic structure Multipliers 5 5 Adders 1 2 Memories 4 2 Referring to Table I, it can be seen that the canonic structure results in two fewer memories but one more adder circuit than for the direct structure. Now, the number of circuits required for producing an extra parallel adder is well above the number of circuits necessary for the two additional input memories. Consequently, if we want to optimize the speed of execution, it is preferable to choose a parallel arrangement associated with a direct structure.

In any event, a serial arrangement leads to a smaller number of components than in a parallel-mounted one. If, therefore, a reduction in the number of components used is being sought to the detriment of the speed, a series arrangement would be preferred. However, contrary to the preceding case, for a series arrangement, the number of components Tequired for a second series adder circuit is lower than the number of components needed for two additional memories.

With a view to optimizing the number of components used in the construction of a filter, in the case of a series arrangement, the canonic structure will be therefore more advisable. In this series case, the memories consist of shift registers and the adders of series-mounted adders.

We are now going to examine the best forms to be given the coefficients in the recurrence relationship by breaking them down into reduced number combinations of powers of two.

The analog angular cut-off frequency, xc, and the digital angular cut-off frequency, w',, are related by the relationship c,)'cAt CAt=tan- (12) 2 as a result of the conformal transform (2).

For digital cut-off frequencies c f'c= 2 of the order of 1 Hz and sampling frequencies 1 fe = #t of the order of 1000 Hz, the quantity W'cAt 2 is of the order of 3.10"3 and equation (12) simplifies down to give W'cAt cAts (12') 2 Equation (12') expresses that, within the range of frequencies examined, the cut-off frequency of the digital filter is twice that of the corresponding analog filter and the quantity vCAt is very small compared to unity.Consequently, the coefficient Ao in equation (4) is of the order of a2, i.e. about 10-5, whereas the coefficients B, and B2 in equations (5) and (6) approximate to a little less than 2 and 1 respectively.

Calculating the recurrence relationship (8) by minicomputer for coefficients of these orders of magnitude is necessarily lengthy, of a few hundreds of microseconds, an elementary floating point operation requiring a time lapse of about 35 ,us.

The principle on which the invention is based is to reduce the calculation time for the recurrence relationship (8) or for the two coupled relationships (10) and (11) and, chiefly, the time devoted to the multiplications, by putting the coefficient Ao arbitrarily equal to 2-" where n is large, and by determining the values of B, and B2 using the condition on the gain of the filter and the damping coefficient tl. The condition on the gain of the filter at zero frequency is obtained by summing the coefficients on the right hand side of the recurrence relationship (8) and taking account of equations (4') and (4"): 4A0+B1-B2=l (13) this equation indicating that the gain of the filter, for a direct current component of the signal, is equal to unity.Furthermore, by resolving equation (4) with respect to l/cr2 and combining equations (4) and (5), we find the relationship expressing B, in terms of Ao and 71; equation (13) then allows us to write B2 in terms of Ao and q:

Relationships (14) and (15) are exact expressions; within the frequency range examined, we saw that the coefficient Ao is of the order of 10-5 which allows the quantity #1+(#-1)A0 to be approximated to one, the quantity 4(172-1) in equation (14) to E1 and the quantity 4# in equation (15) to E2. The quantities E, and E2 are related by the equation E1-E2=-4 and are each chosen to be only equal to a single particular power of two.Under assumptions, for all values of the damping coefficient 77 expressed in the form of a whole or half power of two 9,2U2 where k is an integer (16) the expressions (14) and (15) take the form of combinations of powers of two never exceeding more than three particular powers of two.

The coefficients A0, A,, A2, B, and B2 for a second order low-pass filter of the invention are equal to:

where the different values of the pair (E,, E2) are grouped together in Table II below: TABLE II

El E 1-41-2 141 E2 4 0 2 8 If E2 can be chosen to be equal to 4.r12, there will be no approximation arising from the terms #1 and E2 in the calculation of B, and B2.

Each of these pairs of values (E,, E2) lead to a value of the damping coefficient 77 which differs slightly from the theoretical value of 7p2k/2 in equation (16). This is due to the fact that the expressions (17) for B1 and B2 are approximations of the equations (14) and (15). The damping coefficient is related to the values of the coefficients A0 and B, by the relationship

which is obtained from equations (4) and (5).For values of A0 and B, given by the expressions (17), the true damping coefficient of the filter can be rewritten as:

The values of the true damping coefficients of the filters in the invention having coefficients given by the expressions (17) for various values of the theoretical damping coefficient 2kS2 and the various values of the pair (,, E2), for n=19 or 20, can be seen in Table III below.

TABLE III

# true # true # true # true n k #=2k/2 (E,, E2)=(0, 4) (1, E2)=(-4, 0) (Et, E2)"'(-2, 2) (e1, E2)=(4, 8) ~ . .

20 - 0.00000 (TI < 0) 0.00000 (# < 0) (27 < ) 20 -2 0.50000 0.49927 0.50024 0.49976 0.49829 19 -1 0.70711 0.70641 0.70779 0.70711 0.70503 20 0 1.00000 1.00000 1.00097 1.00048 0.99902 19 1 1.41421 1.41560 1.41699 1.41629 1.41421 20 2 2.00000 2.00294 2.00392 2.00343 2.00196 The values of k appearing in Table III provide the damping coefficients used the most often. However, all other values of k providing smaller or larger damping coefficients result in filters which are just as easily designable. Table III makes it possible to check that the true values of the damping coefficients for the various values of the pair (#" E2) are practically equivalent n=l9 or 20. In the event of n being sufficiently large for the choice of the pair (E,, E2) to be more or less immaterial, the values (0, 4) or (-4, 0) are preferable to the values (-2, 2) and (4, 8) since they minimize the number of powers of two in the two coefficients B, and B2, respectively.If we want to build a low-pass recursive digital filter whose damping coefficient is very close to that of a Butterworth filter, where 7B=l/g, then the coefficients A0, A,, A2, B, and B2 (in expressions (17)) of the z-transform (3) can be rewritten for the choice of (#1, E2)=(0, 4) as:

By substituting the expressions (20) into the relationship (8), the recurrence formula for the second order low-pass recursive digital filter, of the Butterworth type, according to this invention and based on a direct structure, becomes::

where xi, xi~" xj~2 are the sampled values of the input analog signal at the instants iAt, (i-l)At, (i-2)At respectively and Y, Y,, Y,~2 are the corresponding filtered values. The integer # must be odd for the power n+3 2 also to be an integer.

A recursive digital filter is stable if all the poles of its transfer function H(z) lie inside a circle of radius unity. The two poles of the transfer function corresponding to the recurrence formula (21) have moduli of value [22+214-2(7-n)-2]1/2 and the recursive filter derived from (21) is stable whatever the value of the integer n#0.

By inverting equations (4) and (5) and taking into account the values of A0 and B,, we find that 2A0 2A0 2= ~ = ---- (22) 2A0+B1 B, 2n2(n+W2 The analog cut-off frequency wc &alpha;f0 fc 2# 2# corresponding to the recursive filter which obeys the recurrence relationship (21) is therefore given by

The cut-off frequency fc thus depends on the value of the integer n chosen and varies, as a rule, in a discontinuous manner. However, fc is proportional to the sampling frequency f6 and it is possible to modify slightly the latter in such a waythat the cut-off frequency may be adjusted to a desired value.

Up to this point, we have studied the case of second order low-pass recursive digital filters. We are now going to show how, starting from the z-transform of a second order low-pass filter of the invention, to calculate the z-transforms for highpass and rejection filters complying with the invention.

As shown in Figures 3A, 3B and 3C, it is possible to regard a high-pass filter transfer function H(p) as resulting from placing a low-pass filter with a transfer function H,(p) and angular cut-off frequency ,c in series with a filter with a transfer function p2 H2(p)= a)2c where Q)2c=e 1c- If we take as a low-pass filter, a second order filter according to the invention, with a small number of coefficients in the form of integral powers of two, the z-transform H,(z), is given by equation (3) where the coefficients A0, A,, A2, B, and B2 are given by the expressions (17).According to equation (22), the analog angular frequency ,c is approximately equal to

By applying the conformal transform (2) to the function H2(p), the z-transform for the high-pass filter is obtained: Ao I2z-1+z-2 H(z)=- - (25) (w2cAt)2 1--B1z-1+B2Z- If the coefficient Ao (c92cåt)2 is put equal to one, a slight difference between the angular cut-off frequencies co1c and {t)2C is introduced since then

From Table IV below, for a Butterworth filter (k=-l), it can be seen that the relative difference between the two angular cut-off frequencies is small once the odd integer n is greater than 9.

TABLE IV

n 7 9 11 13 15 17 #1&alpha;-#2&alpha; 7% 3 Ó 1.6% 0.8% 0.4% 0.2% #2c gm(dB) 1 0.5 0.25 0.12 0.06 0.03 Figure 4 shows qualitatively, when #1c is slightly greater than c, that the gain of the filter in the pass-band gm is fractionally above zero decibel.The maximum value of this gain, g,, is calculated for an analog frequency of half the sampling frequency, i.e. for z=ei=1. The transfer function H(z) for this value of z=-1 is equal to 4(1+B,+B2)-' or H(1)= ~1 + ------- (27) 1-2(2+k+21/2(n+2i(#1+#2) 2(n-k-21/2 The values of gm in decibels are given for different values of n in the table above when k=-l, i.e. for a Butterworth filter, and the gains are seen to be very close to zero decibel for n)15. This justifies the approximation of putting AO(s2cåt)-2 equal to one in the transfer function (25).

The recurrence formula of a high-pass Butterworth filter of the invention, with coefficients formed of a small number of integral powers of two, based on a direct structure, is thus written, for (E1, E2)=(0, 4), as:

We are now going to concern ourselves with the synthesis of a rejection filter conforming with the principle of the invention.As shown in Figure 5, it is possible to consider a rejection filter with a transfer function H(p) as resulting from placing a low-pass filter with a transfer function H,(p) presenting an angular cut-off frequency 01c and a filter with a transfer function p2 H2(p)=l 2 a)2c in series, where a;20=w, A second order filter of the invention with coefficients formed of a small number of powers of two is taken as a low-pass filter and H,(z) is given by equation (3) where the coefficients are given by the expressions (17) and 1c by equation (24).

By applying the conformal transform (2) to the function H2(p), the z-transform of the rejection filter is written:

We can impose the condition

which, up to the first order in a, is the same as the condition that was imposed on the high-pass filter. The discussion and the validity of this approximation are identical to those of the high-pass filter case.

Under the terms of condition (30), the z-transform (29) of the rejection filter becomes:

The recurrence relationship of a Butterworth type of rejection filter of the invention with coefficients formed of a small number of powers of two is as follows for (E,, E2)=(0, 4):

The recurrence formulae (21), (28) and (32) have been established for Butterworth type low-pass, high-pass and rejection second order recursive digital filters respectively.The formulae are very similar and differ only by the values of the coefficients of xi, x1, and x~2. They may be grouped together in a single recurrence relationship:

with a=l, b=0, c=0 for a low-pass filter, a=0, b=l, c=O for a high-pass filter, a=0, b=l, c=l for a rejection filter. The gain gO at zero frequency is therefore given by gO=a+bc (34) and the gain gm at half the sampling frequency is given by

Equation (33) which combines the 3 recurrence formulae (21), (28) and (32) can be parameterized in different ways.We take an example of parameterization which generalizes the recurrence (21), (28) and (32) for gains different from one:

where q is an integer and with d=l, e=0 for a low-pass filter, d=-l, e=0 for a highpass filter and d=-l, e=l for a rejection filter. The gain gO at zero frequency is thus

and givers 2q for a low-pass filter and 2q-" for a rejection one and, of course, zero for a high-pass filter. The gain gm at half the sampling frequency is given by

and equal approximately 2q-n for high-pass and rejection filters once n is fairly large (nkl 1).Such a parameterization of equation (33') makes it possible to recover the recurrence formulae (21), for d=l, e=0, q=0, (28), for d=-l, e=0, q=n, and (32), for d=-l, e=l, q=n. A different choice of the values of q enables filters having gains differing from one to be defined.

The transfer functions in z of high-pass or rejection second order filter consistent with this invention are always expressed in the form of equation (3), the coefficients B, and B2 being given by the expression (17) but the values of the coefficients A0, A, and A2 now being given by the following expressions for a highpass filter: Ao=l A1= 2 (36) A2=l and by the following expressions for a rejection one: A0=1 A1=-2+2-n (37) A2=1 From a practical point of view, the values of k equal to -l and 0, corresponding to the theoretical damping coefficients 1/g and I respectively, are most commonly used for high-pass and rejection filters.

Table V below displays the values of the coefficients A0, A,, A2, B, and B2 for low-pass, high-pass and rejection second order recursive digital filters of the invention with coefficients formed of a small number of powers of two and a theoretical damping coefficient of 2kl2 and whose z-transforms are given by equation (3).

TABLE V

Type of filter Ao=A2 A, B1 B2 Low-pass 2-n --------- 2-n+1 k+4-n High-pass 1 -2 2 2 2-2+#12-" 1 -2+E22 Rejection I 2+22-fl The values to be given to the digits of the pair (E,, E2) in Table V are those of Table II The parity of n is to be selected in such a way that the quantity n+4+k is always even.In the case of a Butterworth filter for which #=1/#2 and k=-l, we find that B, is equal to 2-n(2n1-3(n/2+2) and that B2 is equal to 2-n(2n-2(n+3)/2+#)., when the pair (E1, E2)=(0, +4), the recurrence relationships (21), (286 and (32) are recovered.

Brief Description of the Drawings We are now going to describe in detail various preferred embodiments of the recursive digital filters of the invention with coefficients formed of a small number of integral powers of two, in relation to the annexed drawings, in which: Figure 1 is a theoretical direct structure diagram of a second order recursive digital filter already commented in the introductory part; Figure 2 is a theoretical canonic structure diagram of a second order recursive digital filter already commented in the introductory part; Figures 3A, 3B and 3C present the synthesis of a high-pass filter derived from a Butterworth low-pass filter and a filter with a transfer function given by p2/o; these figures have been commented in the introductory part;; Figure 4 presents the attenuation characteristic of the high-pass filter synthetized in Figure 3 when the cut-off frequencies lc and Q)2C are slightly different; it has been commented in the introductory part; Figures 5A, 5B and 5C present the synthesis of a rejection filter derived from a Butterworth low-pass filter and a filter with a transfer function given by l+p2/4; they have been commented in the introductory part; Figure 6 explains the principle for calculating a filtered point in accordance with the invention for n=17 for a direct structure; Figure 7 shows a design scheme for a low-pass second order filter with coefficients formed of a small number of powers of two according to the direct structure;; Figure 8 shows a design scheme wired to a data transfer bus line when n=17, for a direct structure; Figures 9 and 10 show, along with Figure 7, design schemes of high-pass and rejection filters of the invention with coefficients formed of a small number of powers of two; Figures 11 and 12 present, in conjunction with Figure 7, design schemes of a filter with coefficient formed of a small number of powers of two, switchable over three filtering positions, a low-pass position, a high-pass position and rejection position; Figures 13 and 14 present the amplitude and phase response curves of the Butterworth low-pass filter of the invention with coefficients formed of a small number of powers of two, for n=5, 11, 13, 15 and 17; Figures 15 and 16 show the amplitude response curves of the high-pass and rejection filters of the invention for n=13;; Figure 17 represents a second order recursive digital filter of the invention, with coefficients formed of small number of powers of two, a series-mounted canonic structure and of the Butterworth low-pass type; Figures 18 to 22 represent low-pass filters of the invention with canonic structures for various values for the damping coefficient rl and a value for n equal to 9 or 10; Figures 23 and 24 represent a high-pass and a rejection filter respectively, with canonic structures, according to the invention for a damping coefficient TI=1/72 and for n=9;; Figure 25 represents a canonic structure filter according to the invention making it possible to select the type of filter, i.e. low-pass, high-pass or rejection, the coefficient of damping 71 and the approximation made on certain terms of the coefficients B1 and B2; and Figure 26 is a summary giving the values of the parameters of the filter structure in Figure 25 in terms of the type of filter described and its damping coefficient.

Description of the Preferred Embodiments Following a preferred embodiment based on the direct structure in Figure 1 and mounted in parallel, a Butterworth type second order low-pass recursive digital filter of the invention with coefficients formed of a small number of integral powers of two uses the recurrence relationship (21) with n=17. Equation (21) becomes then equation (21'): ' 7y -(2'8-2'0)y1,-(2'7-2'0+22)y12+x1+2x11+x12 (21') Figure 6 shows the principle behind calculating a filtered point.The values of xj, x1,, xj~2, yj~, and Yi-2 are stored in 5 different memories and it is a question of summing: x, {filter input) with x,~t shifted towards the left by 1 bit with xi~2 not shifted with y,~, shifted by 18 bits towards the left with y,~, shifted by 10 bits towards the left and the sign changed with Y,-2 shifted by 17 bits towards the left and the sign changed with y12 shifted by 10 bits towards the left with Y,-2 shifted by 2 bits towards the left and the sign changed.

the sum of these 8 quantities is equal to the value of y, shifted by 17 bits towards the left. This value y, is the value of the filtered point leaving the filter.

Figure 7 shows the scheme of one of the embodiments possible with this low pass recursive filter of the invention. The digitized sample x, of the input signal sampled at the sampling frequency 1 fe= At enters by line 110 and is stored in memory Mi. The preceding contents of memory M, is transferred via line 111 to memory M1, and the preceding contents of memory M,~, is transferred via line 112 to memory M,~2 in such a way that, at the instant iAt, the three memories M1, M,~, and M,~2 contain the digitized samples xj, x,~, and x,~2 of the input signal respectively.The sample xi is transmitted via line 113 from memory M, to an adder . The sample x,~, is transmitted via line 114 from memory M,~, to a multiplier 115 which is itself connected to a coefficient register 116 containing the coefficient value 2. The multiplier 115 is linked to the adder z via line 117. The sample x2 is transmitted via line 118 to the adder . The output of the adder is linked via line 119 to a multiplier 120 connected to a coefficient register 121 containing the coefficient value 2-n=2-'7, n being odd so that all the coefficients shown in Figure 7 are integral powers of two.The multiplier 120 is linked via line 122 to the output of the filter, on the one hand, and to a memory M,' on the other hand, which stores the output value yj of the filter. The shifts of the contents of memory M', towards memory M',~, and of the contents of memory M',~, to memory M'12 are carried out via lines 123 and 124 respectively. In this way, the stack of the three memories M'j, M',~, and M'i~2 respectively contains, at the instant iAt, the three values y1, y,~, and Y,-2. Memory M'i~, is linked via lines 125 and 126 to two multipliers 127 and 128 respectively.Multiplier 127 is connected to a coefficient register 129 containing the coefficient value 2n+'=2'8 and is linked to the adder via line 130. Multiplier 128 is connected to a coefficient register 131 containing the coefficient value n+3 2---= 2'0 and is linked to the adder Z via line 132. Similarly, memory M'j2 is linked via lines 133, 134 and 135 to three multipliers 136, 137 and 138 respectively.Multiplier 136 is connected to a coefficient register 139 containing the coefficient value -2"=-2'7 and is linked via line 140 to the adder . Multiplier 137 is connected to a coefficient register 141 containing the coefficient value n+3 2 21 2 and is linked via line 142 to the adder . The third multiplier 138 is connected to a coefficient register 143 containing the coefficient value 22 and is linked via line 144 to the adder . The scheme in Figure 7 that we have just described puts the calculation of recurrrence formula (21) into operation.The seven multipliers 115, 120, 127, 128, 136, 137 and 138, each one associated with its coefficient register, can be shift registers when suitably wired up by taking into account, if we want to multiply the contents of a memory by a negative coefficient, that we have only to multiply the complement of the memory contents by the absolute value of the coefficient and then to add one to the result.

In another preferred embodiment of the same filter, the multipliers and their associated coefficient registers are replaced by a suitable bus line system for transferring data contained in the memories Mj, M11, Mj2, M'j, and M'12, running towards the adder. This latter preferred embodiment eliminates the need for multipliers and reduces the time for calculating the filtered signal. This embodiment, using transfer "bus" line 201 is described in Figure 8 for the particular case of n=17.

The digitized samples xi, x,~, and x,~2 of the input signal corresponding to the times iAt, (i-l)At and (i=2)At are stored in a stack of three registers, 202, 203 and 204 of 16 bits each. For each sampling period At, the stack of x's shifts by one word, i.e. x, takes the place of x1,, xi~, that of x2. Register 202 is linked to data transfer "bus" line 201 via line 213 which connects the 16 bit positions of register 202 with no shift to the "bus" line. Line 214 connects the 16 bit positions of register 203 to the "bus" line 201 with a shift of one bit to the left and line 218 connects the 16 bit positions of register 204 to the "bus" line 201 with no shift.

The values 2'7y1, 2'7yj~, and 2'7y,~2 corresponding to the filtered values y1, y,~, and Y,-2 at the times At, (i-l)At and (i-2)At respectively are stored in a stack of three registers, 205, 206 and 207 of 32 bits each. As for the stack of registers 202, 203 and 204 containing the digitized samples of the input signal, the stack of registers 205, 206 and 207 shifts from one to the following at each sampling period.

The output value of the filter, y1, is given by the bits in bit positions 17 to 31 in register 205. To achieve the transition from the value 2ny~l to 2n+lyj,, line 225 connects the 32 bit positions in register 206 to the "bus" line 201 with a shift of I bit to the left. To achieve the transition from 2"y,~, to n+3 2 y,, 2 which amounts to shifting the contents of register 206 by 7 bits to the right, line 226 connects the bit positions 7 to 31 in register 206 to the "bus" line.Similarly to achieve the transition from 2ny,~2 to the values n+3 2 Y-2 2 and 22y2, lines 234 and 235 connect the bit positions 7 to 31 and 15 to 31 respectively in register 207 to the "bus" line. Line 233 connects the 32 bits positions in register 207 to the "bus" line with no shift. The output of the "bus" line is plugged into the input of an adder-subtractor 208 equipped with a 32-bit accumulator register. The output of adder-subtractor 208 feeds the stack of 32-bit registers 205, 206 and 207. A sequencer 209 makes it possible to transfer the various data contained in the registers to the "bus" line successively and to control the adder-subtractor 208 in terms of the sign of the coefficients.It is also possible to add a sampler and analog to digital converter 210 controlled by clock pulses, to the filtering module thus defined, enabling the sampling frequency fe to be varied. The cut-off frequency fe of the filter may therefore be adjusted to the desired value by selecting a suitable value of the sampling frequency f,, as indicated by equation (23).

The advantage of the arrangement described in Figure 8 lies in the fact that the shifts in the connections of the various registers to the transfer bus line 201 are wired up once and for all and that the multiplications that they perform require no calculation time. The time to calculate a filtered point comes down, therefore, to that required to execute the 7 additions. All the components making up the arrangement in Figure 8 are standard commercial ones, supplied generally in 4-bit sections. Performance-wise, adder-subtractors can be found on the market which perform an operation in 40 nanoseconds. The time to calculate a filtered point, in the light of the data transfer times using a transfer bus line, is therefore of the order of 500 nanoseconds. The cost price of such a module should be competitive alongside that of analog filters with low cut-off frequencies, paired in phase, that exist on the market.

We have studied the various embodiments of Butterworth type second order low-pass recursive digital filters of this invention with coefficients formed of a small number of integral powers of two, based on a direct structure. We can now put forward, in conjunction with Figures 9 to 12, some embodiments of high-pass and rejection filters of the invention, based on a direct structure, with coefficients formed of a small number of powers of two, which derive from the low-pass filter embodiments described above.

A design of deign of a high-pass filter obeying the recurrence equation (28) or of a rejection filter obeying equation (32) is easily obtained from the low-pass filter designs of equation (21) by adequately modifying the section of the assembly which links the x1, x1, and xj~2 memories to the adder. If we take the low-pass filter described in Figure 7, we can obtain equivalent designs for high-pass or rejection filters by replacing the block 101 in Figure 7 by blocks 101' or 101" respectively in Figures 9 and 10. Blocks 101' and 101" differ in the following way from block 101. A multiplier 1131 linked to a coefficient register 1132 containing the value 2n is inserted on line 113.A multiplier 1181 linked to a coefficient register 1182 containing the value 2n is inserted on line 118. Line 114 leads to multiplier 1151 which is linked to the adder by line 1171. This multiplier 1151 is connected to a coefficient register 1161 which contains the value (-2"+'). Finally, in block 101" corresponding to the rejection filter assembly, line 114 is, furthermore, connected to a multiplier 1152 via line 1142. Multiplier 1152 is linked to the adder Z by line 1172 and is connected to coefficient register 1162 which contains the value 22.

An embodiment common to the three low-pass, high-pass and rejection filters and which exploits the generalized recurrence relationship (33), can also be achieved. Figure 11 shows block 101"' which must replace block 101 in Figure 7 to obtain a filter switchable over any one of three low-pass, high-pass and rejection positions. A function selector S includes three coefficient registers with respective contents of a, b and c being able to take the three values (abc)=(100) or (010) or (011). This function selector S is connected to the input lines 113, 114 and 118 coming from the memories Mj, Mj1 and Mi~2 respectively. The 7 lines 1133, 1134, 117, 1171, 1172, 1183 and 1184 are connected to the adder in Figure 7.Block 101"' is equivalent to block 101 for (abc)=(100) in the function selector S; for (abc)=(010), it is equivalent to block 101' in Figure 9 and for (abc)=(Ol 1), to block 101" in Figure 10.

We have described starting from the preferred embodiment of the low-pass filter of Figure 7, how we can develop a high-pass filter, a rejection filter and a filter switchable over the three low-pass, high-pass and rejection functions. We can apply the same parametrization methods to the preferred embodiment of Figure 8 of the low-pass filter wired to a data transfer bus line. We are not going to explain these new modifications, modifications that any specialist is able to apply from the knowledge of what has just been described.

An embodiment common to the three low-pass, high-pass and rejection filters, and which uses the generalized recurrence relationship (33'), may be achieved with a function selector S' including two coefficient registers with respective contents of d and e. The coefficients d and e can assume the three values 0), (-1,0) and (-i, 1). Figure 12 shows block 101'V which must replace block 101 in Figure 7 in order to create such a filter switchable over the three low-pass, high-pass and rejection positions. Block 101 in Figure 12 differs from block 101 in Figure 7 in the following way: a multiplier 1131 linked to cofficient register 1132 containing the value 29 is inserted on line 113.A multiplier 1181 linked to a cofficient register 1182 containing the value 29 is inserted on line 118. Line 114 terminates at the function selector S' which contains two multipliers 190 and 191 linked to two coefficient registers 192 and 193 containing the values d and e respectively. Multiplier 190 connects, via line 1141, line 114 to multiplier 1151. Multiplier 1151 is linked to the coefficient register 1161 containing the value 2q+1 and is connected to the adder F by line 1171. Multiplier 191 connects, via line 1142, line 114 to multiplier 1152.

Multiplier 1152 is linked to the coefficient register 1162 containing the value 2q-n+2 and is connected to the adder l: by line 1172. The value of the integer q is selected in terms of the desired gain, the gains being able to assume only discrete values equal to powers of two. The selection of the integer Q can also be made by the function selector S'. To obtain gains equal to unity, the function selector S' must select the value q=O when the pair of coefficients (d, e) takes the value (1, 0) and must select q=n when (d, e) takes the value (-1, 0) and (-1, 1).The fact that the value of q must be selected in conjunction with the value of the pair of coefficients (d, e) by the function selector S' removes the possibility of transposing the transformation method, in which block 101 in Figure 12 replaces block 101 in Figure 7, to a wired system such as that appearing in Figure 8.

Figures 13 and 14 show the attenuation and phase response curves of the Butterworth type second order low-pass recursive digital filter of the invention, with coefficients formed of a small number of integral powers of two for various values of the odd integer n. It can be noted, with the exception of the curves obtained for n=5, that the form of the curves corresponding to n=1 1, 13, 15 and 17 is entirely identical to those of conventional Butterworth filters. The shortcoming noted for n=5 stems from the fact that, for n too small, the condition a=CAtAl is no longer respected and that the relationship (12') is no longer valid. The frequency deformation of formula (12') due to the conformal transform (2) then becomes apparent.However, the case of n=5 is of practically no interest since the advnatage of the low-pass filter of the invention lies essentially in its low cut-off frequency. Table VI below gives the value of the damping coefficient TI and the digital cut-off frequency f'c of the low-pass filter in the invention for the values n=ll, 13, 15, 17 and 19.

TABLE VI

f'c in Hz for n TI f'c/f, f=l0'Hz 11 0.696 7.13 10-3 7.13 13 0.701 3.63 1073 3.63 15 0.704 1.77 10-3 1.77 17 0.706 0.88 10-3 0.88 19 0.7065 0.44 10-3 0.44 It should be noted that the damping coefficient calculated by the exact equation (18) is very close to the theoretical value of 1/ 20.7071 for a Butterworth filter.

The last column in the above table indicates the value of the digital cut-off frequency f'c for a sampling frequency of 1000 Hz. It can be seen that f'c decreases by roughly half when n passes to n+2. This is due to the fact that the coefficient Ao approximates to a2 when n is large.

Figures 15 and 16 give the attenuation response curves for the high-pass and rejection digital filters of the invention respectively, for n=13.

The design methods which have just been described are not only applicable to the synthesis of Butterworth type second order low-pass recursive digital filters and to the extension to high-pass and rejection filters. It is possible to apply these methods to the synthesis of filters of different characeristics, such as those of Bessel or Legendre, for instance.

As an example, we are now going to describe how to synthesize filters of any order from the transfer function in p of a first order low-pass filter. This example leads to some particularly simple designs.

The transfer function of a first order low-pass filter is expressed by: 1 H(p)= (38) 1+P/CL)c and, by applying the conformal transform (2), the z-transform is given by: 1 + z- H(z)=C (39) 1-Dz-1 where z C= ct+l and D=l-2C. For a=a;At small, C is put equal to 2-" where n is large and the recurrence relationship is written:: 2nyi=(2n-2)yi-1+Xi+Xi-1 (40) The angular cut-off frequency is given by fe =2nf, 2-l The first order low-pass filter with coefficients formed of a small number of integral powers of two thus constructed is particularly simple because it only requires 3 additions over and above the shifts carrying out the multiplications and also because it can be-built with wiring. Placing two first order units in series gives a second order filter whose damping coefficient TI is equal to unity. From the calculation speed viewpoint, the filter formed by placing two first order units in series is a little faster than the second order Butterworth filter of the invention described throughout, as it necessitates only 6 additions instead of 7.

Starting from the first order low-pass filter obeying recurrence relationship (40) as in the case of a second order filter described above, a high-pass filter can be constructed whose recurrence relationship is: 2nyi=(2n-2) yl-l+1 nxi2nx,~l (42) The method of synthesizing the recursive digital filters of the invention with coefficients formed of a small number of material powers of two is thus very general.

The foregoing filters are second order recursive digital ones of the Butterworth type, with damping coefficients 9 equal to 1/ 2 and coefficients formed of a small number of integral powers of two, which are based on a direct structure and mounted in parallel. The filters described up to this stage also cover first order recursive digital ones with coefficients formed of a small number of integral powers of two, based on the same structure. All these filters perform the multiplications by the recurrence relationship coefficients, expressed in the form of a small number of particular powers of two, either by using shift register type multipliers connected to coefficient registers containing the powers of two in question, or via a wiring system on a data transfer bus line.

The second order recursive digital filters according to the invention that we are now going to describe have, as recurrence relationship coefficients, those appearing in Table V and are built according to the theoretical canonic structure diagram in Figure 2 and mounted in series.

These filters, with canonic structures, about to be described have a lower cost price than the direct structure sort because they require less components, whilst still being capable of delivering a filtered signal with the same characteristics.

However; they offer lower calculating speeds and would be preferable to the preceding embodiments if the reduction in the cost price overrides the loss in speed.

Figure 17 shows a Butterworth low-pass filter for which #=1/#2, i.e. k=-l and the pair (E1, E2) is chosen equal to (0.4). The z-transform of such a filter is given by: 2 n( 1 + 2z-1 +z-2) H(z)= (43) l-(2-22'2)z1 +(1-23-n/2+222-n)z-2 and the recurrence relationships (10) and (11) are rewritten as: 2nEo=Fj+2Fi~1 + Fi-2 (44) F1=E1+(2-23-n/2)Fi-1+(-1+23-23-nFi-2 (45) where F, F,~, and F,~2 are the digitalized values at the moments iAt, (i-l)At and (i-2)At of the intermediate signal delivered by the input adder.In Figure 17, the input signal E1 is applied to one of the inputs of input adder 11 whose output is linked to the input of shift register 13 and to an input of output adder 19. The output of output adder 19 delivers the output signal 2nEo. If we want to obtain the filtered signal E0, a 2-" multiplier (not shown on the drawing) must be placed at the output of the output adder. A first output of shift register 13 is linked to the input of shift register 16 and to two multiplying units 14 and IS. Multiplying unit 14 is a multiplier associated with a coefficient register containing the value 2 and its output is linked to one of the inputs of output adder 19.A second output of shift register 13 shifted by (n-3)/2 bits with respect to the first is also linked to multiplying unit 15, the output of this unit 15 being linked to one of the inputs of input adder 11. A first output of shift register 16 is linked to an input of output adder 19 and to multiplying unit 18. Two other outputs of shift register 16 shifted by (n-3)/2 and (n-2) bits respectively in relation to the first output are also connected to multiplying unit 18. The output of multiplying 18 is linked to one of the inputs of input adder 11. The multiplying units 15 and 18 serve to multiply by the coefficients B1=2-2{3-n)/2 and (-B2)=-l+22-12-2(2-n) and are going to be described in detail.

Multiplying unit 15 includes a multiplier 151 associated with a coefficient register containing the value 2, a sign memorizer 152 and a series adder 153. The multiplier 151, being connected to the first output of shift register 13, performs the multiplication of the signal F~, by 2. The sign memorizer 152 receives the second output of shift register 13 which is shifted by (n-3)/2 bits to the left with respect to the first output and therefore delivers the signal 2'3-n)'2F~, . The sign memorizer 152 is mounted in series on the shifted output of shift register 13 and is used for memorizing the sign of the information contained in this register at the moment when this sign arrives at the shifted output.For the whole sequence of bit shifts, it is this memorized sign which is transmitted to the input of series adder 153, thus enabling the sign extension problem to be resolved. The output of multiplier unit 15 delivers the signal (2-2(3-n/2)Fi-1 and has thereby performed the multiplication of Fj, by B,. In a similar fashion, multiplying unit 18 includes two sign memorizers 181 and 182 and a series adder 183. The sign memorizers 181 and 182 are mounted in series on the two shifted outputs of shift register 16 respectively and are used to memorize the sign of the information contained in the register at the moment when this sign arrives at each shifted output respectively.Series adder 183 receives the signals F12, 2(2-fl1i2K2 and 2'2-n'Fj~2 at its three inputs respectively and delivers the signal (-1 +2'3-""2-2'2-"')Fi~, and has thereby performed the multiplication by (-B2). The series adders 153 and 183 can, quite obviously, be comprised in the input adder which will thus comprise 6 inputs. Each of the two multipliers 14 and 151 associated with a coefficient register containing the value 2 may be a simple "flip-flop" set initially at zero and mounted in series between the output of shift register 13 and the input of the corresponding series adder, 19 and 153 respectively.

The design in Figure 17 performs the recurrence relationship (44) in output adder 19 and the recurrence relationship (45) in input adder 11.

Figure 18 shows a particular embodiment of the Butterworth low-pass second order precursive digital filter in Figure 17 for which the series adders 153 and 183 of the multiplier units 15 and 18 are incorporated in input adder 11. In Figure 18, it has been assumed that n=9 and that the input signal is coded over 10 bits. In this case B,=2-2-3 and (-B2)=-l+2-3-2-7.

The same components in Figures 17 and 18 carry the same reference numbers.

The shifted output of shift register 13 is shifted by 3 bits towards the left and delivers the signal 2-3F~,. The shifted outputs of shift register 16 are shifted by 3 and 7 bits towards the left and deliver the signals 2-3F,~2 and 2-7F 2 respectively.

Input adder 11 receives at its six entries, 1111 to 1116, the signals Ei, F~2, 2-3F~2, 2-7F*~2, 2F1, and 2-3Fi~, respectively and delivers the value F1 at its output, in accordance with recurrence relationship (45) for n=9. Output adder 19 receives the signals F1, 2Ft-1 and Fizz at its three entries 1191, 1192 and 1193 and delivers the value 29Eo at its output, in accordance with the recurrence relationship (44) for n=9. The value n=9 has been chosen to illustrate the design in Figure 17 for simplicity's sake, so as not to overburden the diagram. The odd value of n is imposed by the parity condition on n+4+k since, in the case of a Butterworth filter, the value of k is equal to -1.In practice, a larger value for n is generally desirable.

Figures 19 to 22 show embodiments of low-pass recursive digital filters of the invention for various values of the damping coefficient #, namely for 77=0, 1/2, 1/ and 1, giving k=-oo, -2, -l and 0 respectively. In this case, the values of B, and (-B2) in terms of TI are given in Table VII below: TABLE VII

k B, -B2 n 0 -# 2+#12-n -1-E22-n indifferent 1/2 -2 1-2z-+#12-n -1+2-n/2--E,2-" even -1/#2 -1 2-23-n/2 + #12-n -1+23-n/2-#2-n odd 1 0 2-24-n/2+#,2- --1+2111-n7eE222-n even The partiy of n must therefore, for these four cases, be indifferent, even, odd and even respectively and we take, to illustrate the point, the values n=9, 10, 9 and 10 respectively, for simplicity's sake.

In Figure 19, for x7=0, n=9 and (E1, E2) chosen equal to (-4, 0), which corresponds exactly to 2=4772, we find that: B,=22-7 (-B2)=- 1 The values of these coefficients are represented by the connection of one output, shifted by 7 bits towards the left of shift register 13, to input adder 11.

In Figure 20, for #=1/2, n=10 and (E,, 2) chosen equal to (-2, +2), we find that B1=2-2-4-2-9 (-B 2)=- I +2--2- The values of these coefficients are represented by the connections of two outputs, shifted by 4 and 9 bits in both shift register 13 and 16, to input adder 11.

In Figure 21, for TI=1/, n=9 and (E1, E2) chosen equal to (-2, +2), which corresponds exactly to E,r4t12, we find that: B ,=2-2-82-8 (-B2)=-1+2-2-2-a The values of these coefficients are represented by the connections of two outputS, shifted by 3 and 8 bits in both shift register 13 and 16, to input adder 11.

In Figure 22, for 7=1, n=10 and (E1, E2) chosen equal to (0, 4), which again corresponds to E2=4TI2, we find that: B,=22-3 (-B2)=- t2-3-2-8 The values of these coefficients are represented by the connections of one output, shifted by 3 bits in shift register 13, and of two outputs, shifted by 3 and 8 bits in shift register 16, to input adder 11.

In Figures 23 and 24, we can see embodiments of high-pass and rejection recursive digital filters of the invention for a value of the damping coefficient 77 equal to 1/fl; i.e. k=l. The value of n is chosen equal to 9 and the pair (#t, E2) equal to (0, 4) which minimizes the number of shifted outputs towards the input adder.

All the outputs shifted or not going from the shift registers to the input adder are thus connected in the same way as in the case of the low-pass filter of the Butterworth type in Figure 17. On the other hand, the connections going from the shift registers to output adder 19 are no longer the same. For a high-pass filter, we should, in actual fact, have Ao=A2=2 A,=2(-2) and for a rejection one Ao=A2=2" A,=2(-2+22-0) In the high-pass and rejection filters in Figures 23 and 24, the filter input data is 2nEj and no longer E, as in the low-pass filters of Figures 17 to 22. For the high-pass filter in Figure 23, the connection of the output from shift register 13 to output adder 19 is taken into account at the input of adder 19 with the minus sign.For the rejection filter in Figure 24, an additional connection must be made which links an output, shifted by 7 bits towards the left of shift register 13, with output adder 19.

From all these design examples shown in Figures 18 to 24 and the values of the coefficients in Table V, it can be seen that it possible to build a filter structure which can combine all the second order recursive digital filters with coefficients given in Table V.

This universal second order filter structure of the invention, seen in Figure 25, includes an input adder 11 with seven inputs and an output adder 19 with four inputs. The inputs 1111 to 1116 of input adder 11 have +, -, +, -, + and - inputs respectively. Input 1117 is either a + or a - input. A switch 1118 with two positions denoted by 2" and 2n is placed upstream of input 1111. In position 2", the switch 1118 allows the input data Ej to pass without it being modified.In position 2", this switch diverts the input data Ej via a multiplier associated with a coefficient 2", so that the input 1111 of input adder 11 receives the signal 2"E,. The output of input adder 11 is linked to the input 1191 of output adder 19 and the input of shift register 13. A first output of shift register 13 is linked to a times-two multiplier 14, a timestwo multiplier 151 and the input of shift register 16. The output of multiplier 14 is linked to the input 1193 of output adder 19, which is either a plus or a minus input.

The output of multiplier 151 is linked to the plus input 1115 of input adder 11. The output of shift register 16 is linked to the plus input 1194 of output adder 19 and to the minus input 1112 of input adder 11. Three shift register 13 outputs shifted by k,, k2 and k2 respectively are linked via the sign memorizers 161, 152 and 154 and the switches 162, 155 and 156 to the plus, minus and plus or minus inputs 1192, 1116 and 1117 respectively of the input and output adders.

Similarly, two shift register 16 outputs shifted by k4 and k5 are linked by means of sign memorizers 181 and 182 and switches 184 and 185 to the plus and minus inputs 1113 and 1114 respectively of input adder 11. The output of output adder 19 is linked to a multiplier 195 which multiplies the signal delivered by the adder 19 by 2-n. The output of multiplier 195 delivers the filtered signal E,.

The values to be assigned to the shifts k, to k5 of the shifted outputs of the shift registers as well as the positions of the switches i, to i5, the position of the input switch 118 and the sign of the input 1117 of the input adder and of the input 1193 of the output adder are summarized in Figure 26 for certain types of filters, certain values of the damping coefficient and for different values of the pair (E,, E2).

Generally speaking, the input switch 1118 is set to the 20 position for low-pass filters and to 2n for high-pass and rejection ones.

Also, in general, the sign of input 1193 of the output adder 19 is plus for lowpass filters and minus for high-pass and rejection ones.

Finally, switch 162, i,, is usually open for high-pass and low-pass filters and closed for rejection ones, the value of k, always being equal to n-2.

To determine the values of the other parameters, the parameterization of B and (-B2) must be taken into consideration: B,,2-Zk2+2-k5 (-B2)=-1 +2-k42-k5 By comparing these formulae with those in Table V, the following relationships can be deduced: n-4-k k2=k4= 2 E1=+2n k3 2=2n k5 which make it possible to use the universal filter structure of the invention to build a filter of a given type and a given damping coefficient, in compliance with the invention.

It should be noted that the shift registers employed must be of a minimum length given by n+p-2 if p is the number of bits of the input data.

The embodiments of the invention based on a series-mounted canonic structure offer the advantage of restricting the material to be put into use to a minimum. In particular, the problem of the sign extension of the shifted samples is very simply resolved.

The application of the filter to very low cut-off frequencies is achieved by simply extending the two shift registers, the input and output adders not being modified, which is not the case for parallel-mounted arrangements.

The filters with canonic structures described are built using present logical circuits, available on the market and consisting of practically only two types of circuit, namely of series adders and shift registers.

WHAT WE CLAIM IS:- 1. A recursive digital filter deriving the sample of a filtered output signal at a present sampling instant from samples at said present sampling instant and at two

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (15)

1. **WARNING** start of CLMS field may overlap end of DESC **.

   inputs. The inputs 1111 to 1116 of input adder 11 have +, -, +, -, + and - inputs respectively. Input 1117 is either a + or a - input. A switch 1118 with two positions denoted by 2" and 2n is placed upstream of input 1111. In position 2", the switch 1118 allows the input data Ej to pass without it being modified.In position 2", this switch diverts the input data Ej via a multiplier associated with a coefficient 2", so that the input 1111 of input adder 11 receives the signal 2"E,. The output of input adder 11 is linked to the input 1191 of output adder 19 and the input of shift register 13. A first output of shift register 13 is linked to a times-two multiplier 14, a timestwo multiplier 151 and the input of shift register 16. The output of multiplier 14 is linked to the input 1193 of output adder 19, which is either a plus or a minus input.

   The output of multiplier 151 is linked to the plus input 1115 of input adder 11. The output of shift register 16 is linked to the plus input 1194 of output adder 19 and to the minus input 1112 of input adder 11. Three shift register 13 outputs shifted by k,, k2 and k2 respectively are linked via the sign memorizers 161, 152 and 154 and the switches 162, 155 and 156 to the plus, minus and plus or minus inputs 1192, 1116 and 1117 respectively of the input and output adders.

   Similarly, two shift register 16 outputs shifted by k4 and k5 are linked by means of sign memorizers 181 and 182 and switches 184 and 185 to the plus and minus inputs 1113 and 1114 respectively of input adder 11. The output of output adder 19 is linked to a multiplier 195 which multiplies the signal delivered by the adder 19 by 2-n. The output of multiplier 195 delivers the filtered signal E,.

   The values to be assigned to the shifts k, to k5 of the shifted outputs of the shift registers as well as the positions of the switches i, to i5, the position of the input switch 118 and the sign of the input 1117 of the input adder and of the input 1193 of the output adder are summarized in Figure 26 for certain types of filters, certain values of the damping coefficient and for different values of the pair (E,, E2).

   Generally speaking, the input switch 1118 is set to the 20 position for low-pass filters and to 2n for high-pass and rejection ones.

   Also, in general, the sign of input 1193 of the output adder 19 is plus for lowpass filters and minus for high-pass and rejection ones.

   Finally, switch 162, i,, is usually open for high-pass and low-pass filters and closed for rejection ones, the value of k, always being equal to n-2.

   To determine the values of the other parameters, the parameterization of B and (-B2) must be taken into consideration: B,,2-Zk2+2-k5 (-B2)=-1 +2-k42-k5 By comparing these formulae with those in Table V, the following relationships can be deduced: n-4-k k2=k4=

   2 E1=+2n k3 2=2n k5 which make it possible to use the universal filter structure of the invention to build a filter of a given type and a given damping coefficient, in compliance with the invention.

   It should be noted that the shift registers employed must be of a minimum length given by n+p-2 if p is the number of bits of the input data.

   The embodiments of the invention based on a series-mounted canonic structure offer the advantage of restricting the material to be put into use to a minimum. In particular, the problem of the sign extension of the shifted samples is very simply resolved.

   The application of the filter to very low cut-off frequencies is achieved by simply extending the two shift registers, the input and output adders not being modified, which is not the case for parallel-mounted arrangements.

   The filters with canonic structures described are built using present logical circuits, available on the market and consisting of practically only two types of circuit, namely of series adders and shift registers.

   WHAT WE CLAIM IS:- 1. A recursive digital filter deriving the sample of a filtered output signal at a present sampling instant from samples at said present sampling instant and at two

   preceding consecutive sampling instants of a first signal which is either an input signal to be filtered or an auxiliary signal having as one of its component the said input signal and from samples at said two preceding consecutive sampling instants of a second signal which is either the filtered output signal or said auxiliary signal, said filter comprising:: first, second and third first signal store means for storing the samples of said first signal, respectively at said present sampling instant and at said two preceding consecutive sampling instants; fourth and fifth second signal store means for storing the samples of said second signal, respectively at said two preceding consecutive sampling instants; first, second and third multiplier units for respectively multiplying the samples contained in said first second and third first signal store means; fourth and fifth multiplier units for respectively multiplying the samples contained in said fourth and fifth second signal store means;; said first, second, third, fourth and fifth multiplier units being either a single coefficient equal to an integral power of two or sums of coefficients each equal to an integral power of two, said integral power of two including the zero power of two, the sums comprising at most three coefficients, there being an effective further multiplication of all the samples by 2-", where n is a positive integer at least equal to 5; an output adder means having inputs connected to said first, second and third multiplier units and selectively to said fourth and fifth multiplier units and an output delivering said filtered output signal; an optional input adder means having inputs connected to said fourth and fifth multiplier units and receiving the input signal and an output delivering said auxiliary signal.
2. 2. A recursive digital filter as set forth in claim 1, in which the first signal is the input signal to be filtered and the second signal is the filtered output signal, the output adder is connected to the first, second, third, fourth and fifth multiplier units and the optional input adder means is omitted.
3. 3. A recursive digital filter as set forth in claim 2, in which the first, second, third, fourth and fifth multiplier units are multipliers by the respective coefficients: 2-n 2-n+1 2-n 2 "[2n+1~2(n+31tl 2-n[2n2(n+3I!2+ 22] n being an odd integer.
4. 4. A recursive digital filter as set forth in claim 2, in which the first, second, third, fourth and fifth multiplier units comprise a common multiplier by 2-" and respectiye particular multipliers by the respective coefficients: 20 2'

   20 2n+1~2(n+3)/2 ~2n+2(nf3)12~22 n being an odd integer
5. 5. A recursive digital filter of the high-pass type as set forth in claim 2 in which the first, second, third, fourth and fifth multiplier units are multipliers by the respective coefficients: 20 -2

   20 22(3-nlu ~20+2(3--n)12~2(22-n) n being an odd integer.
6. 6. A recursive digital filter of the rejection type as set forth in claim 2 wherein the first, second, third, fourth and fifth multiplier units are multipliers by the respective coefficients:

   20 2+2(2-n) 20 2-2(3-n)/2 20+2(3-n)I22(2-n( n being an odd integer.
7. 7. A recursive digital filter as set forth in claim 2, wherein the first, second and third multiplier units, each comprises a selector function for selectively switching said filter over any one of three low-pass, high-pass and rejection positions, said first, second and third multiplier units being multipliers by the respective coefficients: 2-n+ 1 2-n in the low-pass position, multipliers by the respective coefficients: 20 -2

   20 in the high-pass position, and multipliers by the respective coefficients:

   20 2+2(2-fl) 20 In the rejection position and the fourth and fifth multiplier units being multipliers by the respective coefficients: 22(3-n)!2 20+2(3-n)/22(2-n) n being an odd integer.
8. 8. A recursive digital filter of the low-pass type having a damping coefficient equal to 2k'2 as set forth in claim 2, wherein the first, second and third multiplier units are pultipliers by the respective coefficients: 2 - n 2-n+ 1 2-n and the fourth and fifth multiplier units are multipliers by the respective coefficients: 2-2(k-n+4)12+h12--n 2 -2ik n+4)/2+#22-n n and k being both odd or both even integers and the pair of coefficients (E,, 2) being selected among the pairs (0, 4), (-4, 0), (-2, 2) and (4, 8).
9. 9. A recursive digital filter of the high-pass type having a damping coefficient equal to 2k/2 as set forth in claim 2, wherein the first, second and third multiplier units are multipliers by the respective coefficients: 20 -2

   20 and the fourth and fifth multiplier units are multipliers by the respective coefficients: 2-2(k-n+4)12+E12--n 20-2(k--n+4)12+E222-n n and k being both odd or both even integers and the pair of coefficients (,, 2) being selected among the pairs (0, 4), (-4, 0), (-2, 2) and (4, 8).
10. 10. A recursive digital filter of the rejection type having a damping coefficient equal to 2k/2 as set forth in claim 2, wherein the first, second and third multiplier units are multipliers by the respective coefficients:

    20 2+22-fl 20 and the forth and fifth multiplier units are multipliers by the respective coefficients: 2-21k-n+4/2t#12-n 2 -2(k--n+4)/2+#22-n n and k being both odd or both even integers and the pair of coefficients (1, 2) being selected among the pairs (0, 4), (-4, 0), (-2, +2) and (4, 8).
11. Il. A recursive digital filter as set forth in claim 1 wherein the first and the second signals are the same auxiliary signal having as one of its components the input signal and the input adder means is connected to the fourth and fifth multiplier units and receives the input signal.
12. 12. A recursive digital filter as set forth in claim 11, wherein the first, second and third multiplier units are multipliers by the respective coefficients: 2-n 2-n+1 2-n and the fourth and fifth multiplier units are multipliers by the respective coefficients: 2-2(3-n)/2

    2 +2(3-n)/-2(2-n) n being an odd integer.
13. 13. A recursive digital filter having a damping coefficient of 2k'2=2, whence k=-2, as set forth in claim 11, wherein the first, second and third multiplier units are multipliers by the respective coefficients: 2-n 2-n+1 2-n and the fourth and fifth multiplier units are multipliers by the respective coefficients: 20-2(2--n)12+E122-n 20+2(2-n)/2-#22-n n being an even integer and the pair of coefficients (1, 2) being selected among the pairs (0, 4), (-4, 0), (-2, 2) and (4, 8).
14. 14. A recursive digital filter having a damping coefficient of 2k'2=l/g, z whence k=-l, as set forth in claim 11, wherein the first, second and third multiplier units are multipliers by the respective coefficients: 2 - n 2-n-1 2-n and the fourth and fifth multiplier units are multipliers by the respective coefficients: 2o2(2-fl?!2+ E, 2- 202(2n)I222n n being an odd integer and the pair of coefficients (,' 2) being selected among the pairs (0, 4), (-4, 0), (-2, 2) and (4, 8).
15. 15. A recursive digital filter having a damping coefficient of 2k'2=l, whence k=O, as set forth in claim 11, wherein the first, second and third multiplier units are multipliers by the respective coefficients: 2-n 2 - n + 1 2-n and the fourth and fifth multiplier units are multipliers by the respective coefficients: 2-2(4-n/2+#12-n

    2 +2(4--n1/2)=22-n n being an even integer and the pair of coefficient (,), being selected among the pairs (0, 4), (-4, 0), (-2, 2) and (4, 8).