GB1476603A - Digital multipliers - Google Patents

Abstract

1476603 Digital calculating STANDARD TELEPHONES & CABLES Ltd 27 Aug 1975 35345/75 Heading G4A [Also in Division H3] A digital multiplier comprises an adder, an accumulator in which the adder output is stored and shifted one bit for each addition operation, and input means for applying simultaneously a plurality of serial data words to the adder cells, the input means being arranged so that each serial word so applied may be applied to one or more adder cell input lines simultaneously but no two serial words are applied to the same adder cell input line. Fig. 1, with adder ADD and accumulator ACC, uses a matrix for applying the serial data words D1, D2, which are binary, to form a weighted sum of these words, the weights determining the matrix connections established. Fig. 2 (not shown) shows a modification in which each matrix column can receive any one of three serial input words in either true or inverse (complemented) form (effectively ternary scale). Fig. 3 (not shown) shows another modification which is a fourth order recursive digital filter section and in which all but one of the serial data words used as input are obtained from the output of the multiplier via taps on a chain of one-word delays, the tap outputs being taken variously in true and inverse form, singly and combined (in serial adders). Also provided is a transfer register, loaded in parallel from the accumulator, to feed the (serial) output of the multiplier. The most significant four stages of the transfer register are sensed to determine if the allowable range has been exceeded: if it has, the multiplier output is adjusted to the positive or negative range maximum in an overflow correction circuit. Fig. 4 (not shown) shows a modification of Fig. 2 (not shown), having another adder between the matrix and the firstmentioned adder, this other adder receiving two columns of the matrix to each cell and having an add-subtract control line. Code conversion may be incorporated by appropriate choice of the matrix connections. The least significant carry input of each adder is grounded but may alternatively be used for extra data inputs, rounding, or automatic clearing of the accumulator. Fig. 5 shows a carrysave embodiment, with two (there could be more) adders, each having two data inputs plus a carry input to each cell, the right-hand output being the sum output and the left-hand output being the carry output. A sum accumulator A0-A6, a carry accumulator B0-B7, a sum transfer register S0-S6 and a carry transfer register C0-C7 are connected as shown, the contents of the two transfer registers being added serially at 50. Overflow detection and correction are shown, and also automatic clearing by feedback from 50. The error introduced by inverting for negative sign in the case of twos-complement data can be avoided using a compensation signal or replacing the inverters with suitable subtract-from-zero circuits. Application to digital filters for telecommunica. tions systems is also mentioned generally.