DE2636028A1 - DIGITAL MULTIPLIER - Google Patents

Description

Patent attorney ο η ο c η

Dipl.-PhyS.Leo Thul Zb 0 0 U

Short street 8

7 Stuttgart 30

M.J. Gingell-13

INTERNATIONAL STANDARD ELECTRTC CORPORATION, NEW YORK

DIGITAL MULTIPLIER

The invention relates to a digital multiplier,
especially for digital filters, with an adder and an accumulator in which the output signals of the adder are stored and shifted by one bit with each addition.

State of the art

It is an "add and shift multiplier", which can be used, for example, in digital filters for communication systems.

The adder contains several cells, one for each bit of a digital word. Each cell has two inputs for the two summands, the addend and the auger, and
Outputs for the sum and the carry. A so-called "full adder cell" also has a third input for the carry from the cell with the next lower value.

CS / P-Kg / Scho
5.8.1976

709810/1008

M.J. Gingell-13

In a known multiplier, which has a parallel coefficient B with an incoming serial data word C is supposed to multiply to form the product A = B.C in the accumulator, the multiplicand B becomes in parallel form applied to a number of AND circuits for the duration of word C.

Each bit of word C, starting with the least significant bit, is fed to all AND circuits. If a bit of the word C is a "1", the multiplicand B is added to the contents of the accumulator, and the contents of the accumulator are shifted to the right before the next bit of the word C is fed to the AND circuits. If bit ^{11 is} 0 ", nothing is added. This is continued until all bits of word C have been fed to the AND gates and the multiplication is thus completed. The product A is now in the accumulator and can be, as required, with various known Save procedure.

Negative numbers can be changed with simple modifications to process. For example, if the data is two's complement, the most significant bit will be negative Weight, and only with this bit is the multiplicand B subtracted from the contents of the accumulator instead of added to it.

In digital filters, a digitally encoded sampled signal is filtered by adding various delayed signals Copies of the signal, weighted with various suitable coefficients, are combined with one another. In a digital Filter must therefore generally have a value of the form

P = (D1.E1) + (D2.E2) + D3.E3) + ... (Dn.En) be calculated. D1, D2 etc. are serial data words r and E1, E2 etc. are the weighting coefficients.

709810/1008

M.J. Gingel 1-13

With the simple multiplier described above, such a calculation can only be done in the following way be performed. First the multiplication D1 .El takes place, then the result is saved and the in In parallel form, the coefficient E applied to the AND circuits is changed. Then the next multiplication takes place D2.E2, and its result becomes the previously saved one Product D1.E1 is added and the sum is saved. This process is repeated as often as necessary. Here is the Value P only calculated after η word periods.

task

It is the object of the invention to provide a multiplier of the type mentioned at the beginning to indicate the serial input simultaneously within a single word period η Data words are multiplied simultaneously with given coefficients and the sum of the products is returned.

solution

The task is viewed with those in claim 1 Funds resolved. Further developments result from the subclaims.

description

The invention will now be explained in more detail with reference to the drawings, for example.
It shows:

1 shows a block diagram of a simple one according to the invention digital multiplier with a single full adder and a single accumulator and with a simple input matrix;

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FIG. 2 shows a block diagram of the multiplier according to FIG. 1 with an expanded input matrix;

3 shows a block diagram of a digital filter, its digital multiplier has an accumulator and a shift register and means for overflow detection Has;

4 shows a block diagram of a further modification of the multiplier according to FIG. 1 with a second one Full adder and with an extended input matrix;

Fig.5 is a block diagram of a complete digital Multiplier for processing data present in two's complement, in which the Addition of the carry-save and separate total and carry accumulators and separate sum and carry shift stereo registers are provided.

The simple multiplier shown in FIG. 1 has a six-stage multiplier made up of six "full adder" cells Adder ADD, in which the transfer of each cell is fed to the cell with the next lower value. A seven-stage accumulator ACC takes over the sum output signals Σ0 ... Σ5 in its stages AO to A5 of the adder rows. The most significant stage A6 of the accumulator takes over the transfer C6 from the most significant

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M.J. Gingell-13

Adder cell. The content of each of the accumulator levels A6. · .. A1 is transferred to an input of the next lower value at the bit rate of the input data Adder lines are fed back and the output of the multiplier is serially fed to the accumulator stage AO taken. Each cell of the adder has in addition to the carry and return input (for the auger) a data input (for the addend). via an input matrix serial data words D1 and D2 reach different data inputs of the adder at the same time. Be it assumed that the bill

P = g D1 + ξ D2 should be executed.

I and I are fixed coefficients. The first part of the calculation, the multiplication of D1 by |, can be carried out in two steps:
§ Df- J D1 + J.D1.

To multiply D1 by ^, D1 simply becomes one Bit position shifted to the right, and to multiply by s by 3 bit positions. If input 15 is the most significant Adder cell is assigned a weighting coefficient of 1, i.e. 2 °, then D1 is multiplied by ^, that it is fed to the input 14, which has a weight of i or 2 has. The multiplication of D1 by g happens by entering Di at input 12, which has a weight of

1-3

* or 2 has. If you are on these single ranks at the same time 14 and 12, the accumulator receives the result

J D1 + J D1 = § D1. Similarly, it will be simultaneously

2 8 ö

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M.H. Gingell-13

D2 entered the input 13, so that in the accumulator gives the result P of the entire calculation.

The calculation possibilities of the simple arrangement according to Pig.1 are very limited in practice. A bigger one Flexibility can be achieved by ternary coding the coefficients. Suppose it was the invoice P = ξ Dt + .j-gD2 - 1 D3.

This is possible if the coefficients are as follows be coded:

§ ⁼ ΐοοΤοο = 1
8th 010010 = 1
16 1 _
-4 00T000 = " 1 - • 1 + • -J

1 means that this bit has a negative weight Has. The calculation can be carried out with the arrangement shown in FIG. The adder and the accumulator are the same as those shown in Figure 1, only the input matrix is extended. For each row conductor (Fig. 1) there is a further row conductor via which the input data word can also be fed to the appropriate input of the adder in inverted form.

The data word D1 reaches the input 15 and directly via the inverter INV in complemented form to the input 12. This means that in reality the negative Weights of the ternary represented coefficients are realized by reversing the sign of the data. It

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So § D1 = (1- |) D1 becomes 1.D1 + | . (- D1) treated. D2 and D3 are similarly input to the adder via the input matrix. Again, it's important to emphasize that only one data word, either directly or inverted, is fed to an adder input will.

For cases where different coefficients, which can be considered as data words, are attached to the same Having bits other than zero allows more flexibility through the use of series adders even if the coefficients are represented in ternary form. In other words, in such cases several incoming data words must be fed to the same adder cell. For example, take the invoice

P = (D1.E1) + (D2.E2) + (D3.E3) + (D4.E4) + (D5.E5) considered, the coefficients having the values listed below as fractions and in ternary representation to have.

Value ternary form

E1 136/256 E2 E3 -2 ^ 6 E4 ² / f28 E5 -103/256

OOO1OOO1OOO 01 IoToTooTo TOIOOTOOIOO 0100Ϊ00 00Ϊ0 000Τ0Ι0Τ00Ι

Weight of input 4 2 1 2481632 64128256

There are several non-zero bits in almost every column, but nowhere more than two. The bill can

709810/1008

M.J. Gingell-13

perform in such a way that every two data words that are to be multiplied by a bit of the same place value, are added. In this case, the calculation is as follows:

P = 2 ² (-D3) + 2 ¹ (D2 + D4) + 2 ° (D2 + D3) + 2 ~ ¹ (-D5 + D1) + 2 ~ ² (-D3-D2) + 2 ~ ³ (D5 -D3) + 2 ~ ⁴ (-D2) + 2 ~ ⁵ (-D5 + Di) + 2 ~ ⁶ (D3) + 2 " ⁷ (-D2-D4) + 2 ~ ⁸ (D5).

An arrangement for carrying out this calculation is shown in FIG. This is a recursive digital filter fourth degree, whose only input word is D1 and whose words D2 to D5 from the output signal of the multiplier be derived. D2 is the output data word and D3 through DS are successively delayed versions of it. The delay amounts to one word period in each case. The input 110 with the weight 2 received the word D3 via an inverter. The input 19 (weight 2) receives the serial sum of the values in a serial adder cell 30 added words D2 and D4. The input T8 (weight 2 °) receives the serial sum in a serial adder cell 31 added words D2 and D3 etc.

To prevent the series adder cells from overflowing, the data must be limited to half of the full range, so that after adding any two words, the sum is still within the full range remain.

The filter shown in Fig.3 is designed to with so-called "offset binary data" to work. In such Data is the value of an N-bit word:

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M.j. Gingell-13

D = Z 2 ~ ^{r + 1} (2B ..- 1),
r = 1

where the r-th bit Bj. is equal to 0 or 1. So that is weighted value of this bit is either -2 or +2. The sign reversal, i.e. the multiplication by -1, happens by complementing (inverting) the data bits.

In a digital filter, the output signal can sometimes exceed the permitted data area, so that for this If an overflow protection must be provided. This can be explain as follows. When the multiplication begins, the least significant bits of the result begin, the to leave the least significant adder output. After expiration During the multiplication period, the remaining most significant bits are in the accumulator £ 0 to £ 10 and must are transferred to a shift register Ti to Tn, so that the accumulator for the start of a new multiplication can be emptied. While the multiplier is working on this new multiplication, the bits in the shift register are shifted out of this to reflect the "previous" Complete result. When using fixed point arithmetic, however, it is generally necessary to limit the maximum result to the range that can be expressed by the data format. In digital filters, especially in recursive digital filters, the result can exceed the available data range, so that an undesirable Overflow and thus instabilities are possible if the few most significant bits of the result are simple be dropped. However, if these bits are stored and the result is checked to see if the allowed range has been exceeded, the MuI-

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M.J.GinCTell-13

multiplier can be built in such a way that it has a maximum positive or gives a negative result. In the arrangement according to FIG. 3, this takes place in that the states of bits T8 through T11 are checked to see if an overflow will occur if bits T8 through T11 are dropped and that with the result the output word of the multiplier is corrected in an overflow correction circuit. If no overflow occurs, it can be normal Output word are issued but if an overflow has occurred; so becomes a maximum according to the sign positive or negative data signal issued as a complete result.

Another possibility, the simple one shown in Fig.1 and 2 Making multipliers more flexible is to have multiple inputs per stage of the multiplier, and so on to use a second row of parallel adder cells. If d ± e ternary represented coefficients in the same place value have several bits other than zero, the data can be entered via different inputs without that they need to be added beforehand. Thus, their size does not need to be restricted beforehand either. One such an arrangement is shown in FIG.

The actual multiplier differs from the one shown in the figures described so far in that that an additional row of adder cells ADD 2 is provided which is connected upstream of the first row ADD1. It should be emphasized that the row ADD1 is one more cell than the Row ADD2 must have. The input matrix provides the input

709810/1008

M.J. Gingell-13

Words to the cells in the row ADD2.

Let it be the bill

P = g D1 - I D2 + I D3 considered.

The conductor matrix for entering the input data words in predetermined inputs of the multiplier represents a flexible arrangement. For each input data word, two row conductors are provided, one of which can be used the data word directly and via the other after passing through a sign reverser (inverter) INV in inverted Feed the mold to the entrances. By connecting the row conductors to the input lines of the adder cells forming column ladders at the appropriate crossing points positive or negative data can be entered and the ternary represented coefficients can be implemented. With this arrangement any form of binary coded Process data, such as the normal binary forir, the Two's complement binary form, the binary form with the base -2 etc., provided that the logic of the sign reversal and the adder are adapted to the respective coding. Different codes can be converted into each other by appropriate conversion constants are applied to free inputs and the polarity of the data bits is reversed where necessary.

In the arrangement shown, the carry inputs of the least significant adder cells are grounded. Pie can be used as:
a) additional data inputs;

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M.J. Gingell-13

b) for entering a rounding signal

c) for the automatic extinguishing of the accumulator.

The use according to this last point can reduce the circuit complexity and the processing times of the multiplier considerably simplify, as this means that additional extinguishing elements for each accumulator cell can be dispensed with.

A modified form of the multiplier according to FIG. 4 is described below. This contains adders, the Save the carry (carry-save adder) instead of normal adders that process the carry immediately (ripple through carry) or adders that predict the carry (look-ahead carry). Adders that carry over The carry-save adder is advantageous because it makes the problems of propagation delays more logical Keep signals low.

The Fig.5 shows a complete multiplier that the Two's complement arithmetic and addition with carry-over storage (carey-save-addition) is used. This form allows two inputs per bit. This number of inputs can be but increased by further rows of normal adders or adders with carry-save will. The input data words are fed to the adder inputs via the input matrix already described. the The data is multiplied by -1 by inverting (complementing) the data bits. This is not entirely crenau for data in two's complement, as there is an error in the

709810/1008

M.J. Gingell-13

causes the least significant bit. This creates the result a constant little mistake. In cases where this accuracy is important, the inverters can get through Circuits can be replaced which subtract exactly from zero, or a compensation signal can be fed to a free data input. Each cell of the adder with carry storage (carry-save adder) is a normal full adder with three inputs each with the value 1, a pseudo-sum output of the value 1 and a transfer output of the value The cells in the lower row have two data inputs and an input for the sum returned via an accumulator. The cells in the top row get the sum of the first row, the transfer shifted one bit to the left (left because value = 2), and the transfer via an accumulator repatriated own transfer. The output bits of the cells the top row are loaded in total accumulators AO to A6 and in carry accumulators BO to B7. When returning the sum is shifted one bit to the right as in the previous examples.

The result of the multiplication is the sum of the contents of the total and carryover accumulators r »lus the least significant Bits from the output of the least significant adder cell via a selection circuit in an output delay stage have arrived. The contents of the sum and carry accumulators are stored in sum and carry shift registers SO to S6 or CO to C7 loaded and pushed out, with the sum and the carryover in a holiday adder 50 are added and the result is output via the output delay stage 51. To this

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M.J. Gingell-13

At this point, a new multiplication can begin. There however, at this point in time the sum contained in the two shift registers is the same as that in the contained in both accumulators, it is possible by feeding back the inverted sum of the series adder 51 to the input of the least significant cell of the upper adder to delete the old result without the accumulator cells AO to A6 and BO to B7 to be provided with actual extinguishing devices. Additional improvements can be achieved by an overflow detection and an overflow correction is carried out and that the result is reduced to a predetermined number of bits. is rounded.

709810/100

Claims (4)

M.J. Gingell-13 Claims Digital multiplier, in particular for digital filters, with an adder and an accumulator in which the output signals of the adder are stored and shifted by one bit with each addition, characterized in that for the simultaneous input of several serial data words (D1, D2) into the cells of the adder (ADD) an input matrix is provided via which each serial data word (D1, D2) is fed to one or more adder cells at the same time, with no more than one data word being fed to a single adder cell at the same time. 2. Multiplier according to claim 1, characterized in that the input matrix has a column conductor for each input of the adder and a row conductor for each serial input data word (D1, D2), that each row conductor is connected to the column conductors in accordance with a predetermined digital word, with one single column conductor at most one row conductor is connected. 3. Multiplier according to claim 2, characterized in that a further row conductor is provided for one or more serial input data words (D1, D2, D3), to which the serial input data word is fed in complemented form (via INV), and that each further row conductor is connected to the column conductors in accordance with a predetermined digital word, such that at most one row conductor is connected to a single column conductor (FIG. 2). 709810/1008 M. J. Gingell-13 4. Multiplier according to claim 2 or 3, characterized in that the adder (ADD1, Fig.4) is preceded by a second adder (ADD2) whose inputs the serial input data words (D1, D2, D3) are supplied via the input matrix the input matrix for each cell of the second adder (ADD2) contains two column conductors, so that two simultaneously applied serial input data words (D2, D3 at 13) are added in series that the sum output signals of the second adder (ADD2) as parallel input signals to the first adder (ADD1 ) and that at most one row conductor is connected to a column conductor. 7098 10/1008