CA1073113A

CA1073113A - Digital multiplier

Info

Publication number: CA1073113A
Application number: CA259,572A
Authority: CA
Inventors: Michael J. Gingell
Original assignee: International Standard Electric Corp
Current assignee: STC PLC
Priority date: 1975-08-27
Filing date: 1976-08-20
Publication date: 1980-03-04
Also published as: ES451051A1; GB1476603A; DE2636028A1

Abstract

M. J. GINGELL - 13 (Revision) DIGITAL MULTIPLIER
Abstract of the Disclosure The digital multiplier is of the add and shift type with a matrix type input in which a number of serial data words can be applied simul-taneously to the multiplier enabling the multiplier to compute simul-taneously the sum of a number of products. This multiplier is intended for use in digital filters and single channel coders.

Description

M. J. GINGELI. - 13 313L3 (Revision) ,:
Background of the_nvention , The present invention relates to dlgital multlpllers of the "add and shift" type such as may be used in digital flllers Eor telecommunlca-tlons systems.
In such multipliers multipllcation is achieved b~ performlng a number of addltion operatlons using an adder with an accumulator ln which the adder output is stored and shlfted one bit posltlon Eor each addition operation. An adder comprises a serles of cells, one for each bit in a digltal word, each cell having lnpues for the addend and the augend and outputs for the sum and carry. A so-called "full adder cell" has in additlon a third input to whlch the carry from the cell of next lesser significance may be applied.
In a known form of multiplier where, say, a parallel coefficient B ls to be multiplied by an incomlng serlal data word C to form the lS product A=BxC in the accumulator, the multiplicand B 16 applied ln parallel to a number of AND gates for the duratLon of the word CO Each bit of the word C, starting with the least slgni~icant bit, is applied to all the AND gates. If a bit of word C is a logic "l" then the multl-plicand B is added to the accumulator (if it ls a logic "O'` nothlng ls added) and the contents of the accumulator are right shifted before the next bit of word C is applied to the AND gates. This continues until all the blts of word C have been applied to the gates, then the multiplication is complete. The answer A is now ln the accumulator and may be extracted as required by various known methods.
Negatlve numbers can be handled by varlous known simple modl-ficatiorls. For example, if 2's complement data ls used then the most signiflcant bit of the data has a negatlve walght and for thls bit only

2 ~

- " ; ~:, , ,, .: , :, -

3~:~L3 . (Revislon) the multlplicand B ls subtracted from instead of aàded to the accumu-lator .
In digital filters a digltally encoded sampled signal 1s filtered by combining together various delayed copies of the signal through sult-able weighting coefficlents, In general in a digital filter it ls thus .
necessary to form an accumulated product such as:
P=(DlxEl) + (D2~E2) + (D3xE3) .... (DnXEn)~
where Dl,b2 etc. are fllter signal serial data words and El, E2 etc9 are the filter tap coefficlents. In the simple type of multiplier described above thls type of operation can only be accomplished by performing first the multlpllcation DlxEl, storlng the result, changing the coef ficient E, applied in parallel to the AND gates, performing the next mu:ltlpllcatlon D2xE2, adding the reslllt to the previously stored product DlxEl, storlng the sum, and repeatlng this process as many times as required. It is obvious that it would be advantageous to be able to perform all n multlpllcatlons slmultaneously and produce the pqoduct P at the end of one serial data word period rather than to have to wait for n word perlods. ! , S mary of the Inven_ion An object of the present invention is to provlde an Improved dlgital multlpller capable of being employed In dlgltal filters and slngle channel .
cvders .
A feature of the present lnvention ls the provision of a digital multiplier providing a calculated output signal comprising: a flrst adder having a plurality.of first adder cells; an accumulator coupled to each of the first adder cells to store the.outp-~t of each of the flrst adder cells and to shift the stored output one bit for each addition - 3 - .
.

10'73S.13 (Revlslon) ¦:

operation; and input means coupled to the first adder cells for applylng simultaneously a plurallty of serial data words to the first adder cells, the input means being arranged so that each of the serial words ls applled to predetermined ones of the flrst adder cells but no two serial words are applied to the same one of the first adder cells.
_rief_s~ri~_o of the Drawing Above-mentloned and other features and objects of thls lnvention wlll become more apparent by reference to the following descrlptlon taken in conjunction with the accompanying drawing, ln which:
Fig. 1 is a block schematic diagram of a simple dlgital multlplier according to the princlples of the present inventlon using a slngle full adder to perform addltion operations, a slngle accumulator in which the sum outputs of the full-adder are simultaneously accumulated and right shifted, and a basic form of wired lnput matrix;
Fig. 2 ls a block schematic diagram of a modification of the multiplier of Flg. 1 in which the baslc input matrlx is modifled to improve flexibility;
Fig. 3 is a block schematlc diagram of a fourth order recursive digital fllter section which utilizes a digital multiplier having a separate accumulator and transfer register with p~ovision for overflow detection in accordance with the principles of the present invention;
Fig. 4 Is a block schematic dlagram of a further modification of the basic multiplier of Fig. 1 using a second full adder with a modlfl~d input matrix to enable the number of inputs to the multlplier to be increased still further; and Fig. 5 ls a block schematic diagram of a complete digltal mul~i-plier for handling digital data uslng 2's complement andl carry-save M . J . GINGELT - l 3 il 0'~3113 (Revlslon) addition with separate sum and calry accumulators an~ separate sum and cal~y transfer registers in accordance with the principles of the present invention.
Description f the Pre erred Emboc!i~ents S In ~he simple multiplier arrangement shown in Fig. 1 a 6-stage adder ADD is constructed with "full-adder" cells the carry from each cell being applied to the cell of next greater signlficance.
A 7-stage accumulator ACC receives, in stages AO to A5, the sum outputs o...~ ~5 of the adder cells. The most significant stage A6 of the accumulator receives the carry output C6 of the most significant adder cell, The contents of the accumulator stages A6...Al are fed back at the data bit rate as inputs to the adder cells of next lesser signiflcance while the multiplier output is taken serially from stage A0 of the accumulator ACC. Each adder cell has, in addition to the carry and feedback (augend) inputs a data (addend) lnput which is fed via an input matrix M with serial data words D1 and D2 simul-taneously. Suppose that it is desired to perforrn the calculation:-P = S/8D1 ~ l/4D2, where 5/8 and l/4 are fixed coefficients.
The flrst part of the calculatlon, i.e., multiplying Dl by S/8 can be broken down into two separate operations as follows:
5/8D~ Dl ~ 1/8Dl Multiplying Dl by l/2 is slmply effected by right-shifting Dl by one bit position while multlplying D1 by l/8 is effected by right-shifting Dl by three bit positions. If the lnput I5 to the most slgnifl-cant cell of the adder ADD is regarded as having a vvelghtlng valus of l, i.e., it has a value of 2, then to multiply Dl by 1/2 lt must be fed to input I4 which has a welght of l/2 or 2 l. To multiply Dl by 5 _ .

M. J. GINGELI, - 13 10~731~l3 (Revislon) 1/8 it must b~ fed to input I2, which has a welght of 1/8 or 2-3.
When Dl ls fed simultaneously to these inputs I4 and I2 the result ln the accumulator AC~ will be 1/2Dl + 1/8Dl = 5/8D.
Similarly D2 is fed simultaneously to input I3 and the accumulator ACC will then contain the result of P of the full calculation. It will be noted that each word is fed to one or more lnputs to the adder, but that no two words are fed to the same lnput.
It will be appreciated that such a simple arrangement as that shown ln Fig. 1 has severe llmitations in practiceO Greater flexibillty cail be obtained by using ternary coding of the coefficients. Suppose that ls is deslred to perform the calculatlon:
p = 7/8D1 ~ 9 D2 ~ 1/4 D3 .

This can be achleved by expressing the coefflcients ln a ternary code as follows:
7/8= 100100= 1 - 1/8 9= 010010= 1/2 +

= 001000 = - 1/4 In this table the use of the bar, l.e. I 1, lndlcates that the relevant bit has a negative weight, Thls calculation can then be performed uslng the arrangement shown ln Flg. 2. The adder ADD and accumulator ACG are the same as ln Fig. 1, but the input matrix M' is more complex, each data word being fed either direct and/or inverted - (complemented) to the approprlate adder inputs.
Word Dl is fed directly to lnput I5 and ln complemented form to input I2 by means of the lnverter INV. In practice what this means ls that although the coefEicients are expressed ln a ternary code the " ' 31 M . J . GINGELL - l 3 3 (Revision3 ~ ~, - negative welghts are reallzed by reversing the sign of the data, Thus, in ef~ect 7/8D~ 1/8)1:)1 = lxDl -~ 1/8x(-Dl). D2 ~ D3 are slmilarly fed to the input matrix M' wlth inversion where appropriate, Once again, it is important to note that any one adder lnput recelves not more than one word, either direct or inverted, Further flexlbility can be achleved by uslng serial adders for cases where the coe~ficlents (whlch can be regarded as data words) have bits .
which overlap, even after re-expresslng them in ternary form~ In other words two incoming data words are required to be fed to the same adder cell. Consider as an example the calculation:
P tDlXE1) + (~2 x E2) + (D3xE3) + (D4xE~ (Ds~cE5) where the coefficlents El - E5 have the values glven below and are re-sxpressed ln the ternary forms shown In the followlng tabl~.
ALUE _ TERNARY FORM
El136/256 0 G 0 1 0 0 0 1 0 0 û

Input Equivalent Weight 4 2 1 1 1 1 ; 2 4 8 16 32 64 128 256 It can be seen that in nearly e~ery column there are two over-lapping ternary blts but nowhere are there more than two, This calcu-lation can be realized by pre~adding together two data words where they are each to be multiplied by the same weight blt. In this case the result will be forrned by performlng the calculatlon as follows:

"
il M J. GINGELL - 13 3113 (Revislon~

P-22(-D3) t 21 (D2~ D4) ~ 2 (D2+D3) ~ 2 1 (-Ds+Dl) ~2-2 (-D4-D2~ + 2 3 (D5-D3) + 2 (-D2) ~2-5 (-D5~Dl) ~2 6 (D3) + 2 7 (-D2-D4) + 2 8 (D5) An arrangement for performing the calculation in this manner is shown in Flg. 3. The arrangement of Flg. 3 is designed as a fourth order recurslve digital filter sectlon ln which in fact Dl ls the only external lnput and D2 ~ D5 are derived from the multipller output.
D2 is the multiplier output proper, and D3 - D5 are successively delayed versions of D2, in each case delayed ~y one word period.
To perform the calculatlon the input Ilo, having the weight of 22, recelves word D3 via an inverter, input Ig receives the serLal sum of words D2 and I~4 produced by the serlal adder cell 30, Input I8 recelves the serial sum of words D2 and D3 produced by serial adder cell 31 and so on. To prevent overflow in the serial adder cells the data i5 must be pre-limited to - l/2-full scale range so that an additlon of any two words t~le sum is stlll within the full range.
The filter section shown in Fig. 3 is designed to work with offset blnary data, thal ls for an N-bit word the value 15:-N 2-N~l (2Br-l) r= l ~0 where the rth bit Br is worth "O" or "l" . Thus, the weighted value of that bit is -2- or + 2 , respectively. Slgn reversal (that is multiplication by -1) is achieved by complementary ~inverting) the data bits ~
In a practical digital fllter the output under some circumstances may exceed the allovvable data range and for~that case overflow protection mu~t be provided. This can be accomplished In the followlng manner~

.

~lV~73~ 3 (Revision) , , When multiplicatlon starts the least signlElcant blts of the answer start ~;
coming from the least signiEicant adder output. At the completion of the multiplication period the remaining most sicJnificant blts of the answer are in the accumulator (A0 - A1Q) and must be transferred over to a transfer reglster (T1 - Tll) so that the accumulator can be cleared to start a new multlplication. While the multlplier ls working on this new multiplication the bits ln the transfer register are shlfted out to complete the previous answer. In general, however, when worklng with flxed point arithmetic, it is necessary to llmit the maximum answer to the available range expressible by the data format, In digital filters, particularly of the recurslve types the answer may exceed the available data ran~e so that if the most significant few bits of the accumulated result are slmply ignored an undesirable overflow characterlstic may occur leading to instability. However, by storing the bits to be dropped and checking the answer to see if the allowable range ~as been exceeded the multiplier can be made to saturate giving a maximum positive or nsgative result, This is done in the arrangement of Fig. 3 by checking the states of bits T8 to Tl1 in overflow detector OD to detect whether overflow will occur if Tg to Tll are dropped and using the result to control the multiplier output in an overflow correction circuit OC . If no overflow occurs then the normal output is allowed to flow out but if overflow has occu~ed then a maximum positive or negative data signal is substituted for the completed answer according to the slgn.
.

Another way of achieving flexibility while adhering to the general rule stated earlier is to provide multiple inputs per stage of the multl-plier using a second rank of parallel adder cells. Where there are overlapping bits in the ternary expressed coe~iclent~; the data can be _ g _ M. J. GINGELL - 13 3113 (Revision) fed into individual lnputs without the need for serial pre-additlon and, hence, pre-limitlng of the data lnput magnitude. Such an arrangement is shown in Fig. 4, The basic multiplier design of Flg. 4 ls similar to that of the pre-ceding figures but with the additional rank of adder cells ADD 2 preceding the final rank of adder ceIls ADD 1. Note that the flnal `
rank of adder cells ADD 1 has to have one more cell than the additional rank of adder cells ADD 2. The inputs to the multipliers are by way of the input matrix M" feeding the cells of the addition rank of adder cells ADD 2.
Conslder the following calculation:-p = 7/8Dl - 3/8D2 ~ 4D3 By constructing a general purpose X-Y interconnection matrix as shown in Fig. 4 and making connections only at the appropriate crossings a ve~y flexible arrangement results. Each input da-ta line drives one input line directly and a second lnput line through a sign reverser (inverter) so that either data or minus data can be connected to give coefficients expressed In ternary. This scheme vylll work wIth any form of binary coded data, such as ordlnary binary, 2's complement blnary, offset-binary, negabinary (radix -2) etc., provided the logic in the slgn reversers and adders is appropriate to the type of c~ding.
Conversion between different codes can be simultaneously accomplished ;~ by feeding in appropriate conversion constants to unused-inputs and inverting the polarity of data bits where necessary.
In the arrangement illustrated the least significant bit carry inp~lts of the adders are shown grounded. They may in fact be used (a) as extra data inputs, (b) for ieeding in a rounding signal, ~c) for - M. J. GINGELL - 13 iLQi~3i13 (Revision) providlng an automatic clear of the accumulator ACC.
Thls last item can consiclerably simpllfy the hardware and timln~
of multipliers since lt elimlnates the need for individual clear elements ln each accumulator cell.
The method will be descrlbed using a modlified design of Fig. 4 with carry-save adders ins~ead of fully parallel ripple or look-ahead carry types. The method can equally well be used with ripple through carry addition, but it is useful to consider a carry-save additLon type ~;
which minimlzes problems of loglc propagation delayO
F1~. 5 shows a complete multipller deslgn using 2's complement arithmetlc anà carry-save addition. Thls deslgn allows two inputs per blt but th~s can be lncreased by addltional ranks of ordinary or carry-sa~e adders. Input data is routed to the adder lnputs vla the coefficient connection matrix M"' previously described. Multlplica-tion of data by -1 is achleved by invertlng (complemeIiting) the data bits. This is not strictly accurate with 2's complemen~ data slnce lt introduces an error of one least significant bit. This will cause a constant small error in the result. In cases where this is im~ortant the inverters can be replaced by true subtract from zero circuits or a compensation signal can be fed into an unused data lnput. Each carry-save adder cell is a normal full adder with three inputs each worth one unit and pseudo sum and carry outputs worth one and two units, respectively. The first rank takes two data inputs plus the fed back sum accumulator and feeds the second rankO The second rank takes the sum from the first rank plus the left shifted carry (shifted left since the carry ls worth 2 units) plus the fed back carry accumu-lator. The outputs are loaded into the sum and car~y accumulators A0-A6 and B0-B7, respectively. On feedback the sum i3 shlfted one place .
,~

M. J. GINGELL - 13 ~llV~Y3113 (Revision) ;

rlght as ln prevlous examples, but the carry shift right ls neu~allzed by the fact that belng worth twlce as much as the sum it needs shlfting one place left.
On cvmpletion of the multiplicatlon the answer is the sum of the contents of the sum and carry accumulators plus the least significant 1 bits which have flowed out the least-slgnificant-bit-sum output through the selector and into the output delay. The contents of the sum and carry accumulators are loaded into sum and carry transfer reglsters SCTR and shifting beglns, addlng the two together in serial adder 50 and routing the result through the output delay 51. At the same time a new multipllcation can start. However, slnce at thls point the sum contalned in the two transfer reyisters ls the same as the sum con talned in the two accumulators lt is possible by feedlng back minus the sum of the two transfer reglsters into the accumulators to remove the old result from the calculation wlthout the physlcal necesslty for clearlng the accumulator cells Ao to A6 and Bo to B7. Additional reflnements can include overflow detectlon and correctlon and also roundlny the answer to a given number of bits.
While I have descrlbed above the prlnciples of my inventlon in connection with speciflc apparatus it is to be clearly understood that thls description is made only by way of example and not as a llmlta-tion to the scope of my invention as set forth in the ob~ects thereof and ln the accompanying clalms.

AC H: ~/g s/o~

Claims

M . J . GINGELL - 13 (Revision) I CLAIM:

1. A digital multiplier providing a calculated output signal comprising:
a first adder having a plurality of first adder cells;
an accumulator coupled to each of said first adder cells to store the output of each of said first adder cells and to shift said stored output one bit for each addition operation; and input means coupled to said first adder cells for applying simultaneously a plurality of serial data words to said first adder cells, said input means being arranged so that each of said serial words is applied to predetermined ones of said first adder cells but no two serial words are applied to the same one of said first adder cells.

2. A multiplier according to claim 1, further including first means coupled to said accumulator for examining a given number of the most significant bits of said calculated output signal to determine if the complete calculated output signal value will exceed a predetermined range of values; and second means coupled to said accumulator and a given one of said first adder cells for substituting for said calculated output signal a selected one of a maximum positive and negative data signal according to the sign of said calculated output signal when the value of the latter exceeds said predetermined range of values.

3. A multiplier according to claim 1, wherein said input means includes an input matrix having a plurality of column conductors and a plurality of row conductors each of said column conductors being coupled to a different one of said first adder cells and each of said row conductors being coupled M. J. GINGELL - 13 (Revision) to a different one of said serial words, the interconnection of each of said row conductors with said column conductors being arranged in a pattern corresponding to a predetermined digital word, said interconnection pattern for each of said row conductors being different from said interconnection pattern of every other one of said row conductors with no more than one of said row conductors having an interconnection with any one of said column conductors.

4. A multiplier according to claim 3, wherein said calculated output signal is provided by said accumulator.

5. A multiplier according to claim 3, further including first means coupled to said accumulator for examining a given number of the most significant bits of said calculated output signal to determine if the complete calculated output signal value will exceed a predetermined range of values; and second means coupled to said accumulator and a given one of said first adder cells for substituting for said calculated output signal a selected one of a maximum positive and negative data signal according to the sign of said calculated output signal when the value of the latter exceeds said predetermined range of values.

M. J. GINGELL - 13 (Revision)

6. A digital multiplier comprising:
input means for serially receiving a plurality of serial n-bit digital inputs at a predetermined clock rate for deriving a plurality of parallel n-bit serial digital inputs therefrom;
weighting means for weighting each of said n-bit serial digital inputs with a plurality of constant coefficients, such that each of said n-hit serial digital inputs is weighted with one of said plurality of coefficients;
accumulator means having said plurality of weighted n-bit serial digital inputs coupled thereto in parallel for adding said parallel n-bit serial inputs in parallel to obtain a calculated digital output; and output means for serially coupling said calculated digital output from said accumulator at said predetermined clock rate.

7. A digital multiplier in accordance with claim 6 wherein said input means includes a plurality of shift register delays each of which shift register delays being adapted t o derive one of said parallel n-bit serial digital inputs.

8. A digital multiplier in accordance with claim 7 wherein said weighting means includes a weighting matrix for deriving said constant coefficients, one of said constant coefficients being derived for each of said parallel n-bit serial inputs.

M. J. GINGELL - 13 (Revision)

9. A digital multiplier in accordance with claim 8 wherein the addition of said plurality of weighted parallel n-bit serial digital inputs by said accumulator to derive said calculated digital output is performed in an n-bit time duration.