US4825397A - Linear feedback shift register circuit, of systolic architecture - Google Patents
Linear feedback shift register circuit, of systolic architecture Download PDFInfo
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- US4825397A US4825397A US07/064,482 US6448287A US4825397A US 4825397 A US4825397 A US 4825397A US 6448287 A US6448287 A US 6448287A US 4825397 A US4825397 A US 4825397A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/582—Pseudo-random number generators
- G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/58—Indexing scheme relating to groups G06F7/58 - G06F7/588
- G06F2207/581—Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/58—Indexing scheme relating to groups G06F7/58 - G06F7/588
- G06F2207/582—Parallel finite field implementation, i.e. at least partially parallel implementation of finite field arithmetic, generating several new bits or trits per step, e.g. using a GF multiplier
Definitions
- the present invention relates to a linear feedback shift register circuit suitable for providing respective digital samples at successive time instants, each of which samples represents a linear combination of prior digital samples and comprises M significant bits together with an optional addition of X sign extension bits, where X may optionally be zero, said circuit comprising N similar cells each of which forms a bit flow path comprising in series between a main input and a main output of said cell: a P-bit upstream register; a weighting operator; a two-input combining operator; and a Q-bit downstream register; with the output from the upstream register and one of the two inputs to the combining operator respectively constituting a secondary output and a secondary input of the cell suitable for being respectively connected to a main input and to a main output of a following cell in the circuit, and with the main output of the first cell being fed back to the main input of said cell in order to allow the digital samples produced to be recirculated.
- Linear feedback shift register circuits have been used for several years and are generally known under the English term or its abbreviation "LFSR".
- FIG. 1 is a diagram of a first type of prior art LFSR.
- This LFSR which does not include all of the features mentioned in the introduction, comprises registers (e.g. RG1 to RG5), weighting operators OP1 to OP5 which are constituted, for example, by multipliers which multiply by respective constant coefficients k1 to k5, and a combining operator OC.
- the bit flow paths which are represented by single lines are constituted, in fact, by paths for parallel bit flow, and are therefore each constituted by a plurality of parallel lines.
- the registers and the operators are parallel-operating registers and operators, i.e. each of them acts on a plurality of bits at a time.
- the combining operator OC which is represented diagrammatically as a single adder is not physically constituted in this particular form.
- a parallel operator such as OC takes the form of a pyramid of elementary triad operators (i.e. operators having two inputs and one output), as shown in FIG. 2.
- registers RG1 to RGN contain samples SN to S1.
- each digital sample passes from one register to the next register and is simultaneously weighted by the operator OP connected to the output of the register it is leaving; the weighted samples are then simultaneously transmitted to the combining operator OC.
- the combining operator OC (assumed to be constituted by the FIG. 2 conventional parallel adder) thus provides a digital sample: ##EQU2## which is stored in the register RG1.
- Such an LFSR therefore provides the desired function which consists in providing digital samples represented by linear combinations of earlier samples.
- an LFSR of this type is not suitable for being described as an assembly of N similar cells.
- Each cell constitutes a parallel bit flow path comprising a series connection of a register such as RG1 to RGN, a weighting operator such as OP1 to OPN, and a combining operator such as OC1 to OCN.
- the registers and the weighting and the combining operators operate in parallel, i.e. the single lines shown connecting them to one another in the diagram of FIG. 3 are in fact constituted by M parallel lines where M is the number of bits in each of the digital samples contained in the registers RG1 to RGN.
- the FIG. 3 LFSR includes a multiplexer MX enabling the input to the register RG1 to be connected either to an input E to the LFSR circuit or else to the output from the combining operator OC1.
- the multiplexer MX in the FIG. 3 LFSR connects the input E thereof to the register RG1 so as to provide access to this circuit for digital samples S1 to SN which are initially applied to the input E and which, at the end of the initialization stage, occupy respective ones of the registers RGN to RG1.
- the multiplexer MX is then switched to connect the output from the combining operator OC1 to the input to the register RG1, thereby enabling new digital samples to be generated by circulating the initial samples S1 to SN and by the processing provided by the various operators.
- the digital samples stored in the registers RG1 to RGN are simultaneously transmitted to the respective following registers and also to the respective weighting operators OP1 to OPN in which they are multiplied by respective constant coefficients k1 to kN.
- weighted digital samples are all simultaneously available at the top inputs to the respective operators OC1 to OCN.
- FIG. 3 LFSR has the advantage of modular structure describable as an assembly of N similar cells, it nevertheless retains the drawback of leading to cycle times which depend on the number N of cells.
- This LFSR satisfies all of the features specified at the beginning of the present description and represents the closest prior art to the invention.
- FIG. 4 LFSR is described, for example, at page 43 (FIG. 10) of the January 1982 number of the journal "Computer”, in an article by H.T. Kung (Carnegie-Mellon University).
- bit flow paths and the operators in the FIG. 4 LFSR are parallel in structure.
- each cell (such as C1 to CN) of the FIG. 4 circuit instead of comprising a single register (such as RG1 to RGN), comprises a P-bit upstream register (such as RGE1 to RGEN) together with a Q-bit downstream register such as RGS1 to RGSN).
- initialization is performed by alternately injecting via the multiplexer MX a useful digital sample such as S1 to SN and a null sample, i.e. a sample in which all the bits are equal to zero.
- each digital sample follows an elementary path which corresponds to the distance between two registers.
- the FIG. 4 LFSR thus has the advantage of a modular structure and also of generating (after its initialization stage) each of the digital samples in a time which is independent of the number N of digital samples being used.
- this prior LFSR suffers from two drawbacks: the first is that it requires an initialization stage of 2N cycles for N useful samples, and the second is that under stationary conditions it provides a new useful digital sample only on every other cycle since every in-between sample produced is constituted by a null sample.
- the aim of the present invention is to provide a systolic LFSR which requires an initialization stage of only N cycles for N useful digital samples, and which only produces useful digital samples.
- the LFSR circuit of the present invention for processing digital samples each comprising M significant bits together with an optional addition of X sign extension bits (where X may be 0), and including upstream registers each containing P bits and downstream registers each containing Q bits is essentially characterized in that the upstream and downstream registers in each cell are serial shift registers and in that the sum P+Q of their lengths is equal to the total length M+X of each of the digital samples.
- FIGS. 1 to 4 show prior art as described above
- FIG. 5 shows the physical structure of an LFSR circuit in accordance with the invention.
- FIG. 6 shows, in addition to said physical structure, the change as a function time of the contents of the shift registers of such an LFSR, thus showing the operation thereof.
- the linear feedback shift register (LFSR) circuit in accordance with the invention and shown in FIG. 5 comprises N similar cells (with N being taken to be equal to 3 in FIG. 5) referenced C1, C2, and C3.
- Each cell constitutes a bit flow path symbolized by an arrow in cell C1, and comprises in series between a main input such as EP1, EP2, or EP3, and a main output such as SP1, SP2, or SP3 of said cell: a P-bit upstream register such as RGE1, RGE2, or RGE3; a weighting operator such as OP1, OP2, or O3; a combining operator such as OC1, OC2n or OC3; and a Q-bit downstream register such as RGS1, RGS2, or RGS3.
- P is equal to 4 and Q is equal to 1.
- the bit flow path constituted by each cell is a serial bit path, i.e. the bits flow therealong one behind the other along a single line.
- the upstream and downstream registers are serial shift registers, i.e. the bits stored therein constitute a single sequence between the inlet and the outlet to each of these registers.
- the LFSR circuit shown in FIG. 5 is intended to provide, at successive instants, respective digital samples Sj, each of which is representative of a linear combination of prior digital samples Sj-N to Sj-1.
- the circuit may provide at least one digital sample coming from a combination of the N initial samples (i.e. three samples in the present example) as provided to the circuit at the beginning of its operation.
- the weighting operators are typically multipliers, operating, for example, by multiplying the digital sample by constant coefficients such as k1 to kN.
- weighting operator rather than the term “multiplier” is that in known manner these operators may operate on mathematical sets other than the set of real numbers for which multiplication is traditionally defined, for example they may operate on a Galois body.
- the combining operators OC1 to OCN symbolized by triad operators having two inputs and one output are typically adders.
- these combining operators may operate on sets other than the set of real number, for example on a Galois body. They may also, in known manner, include a memory for storing the carry resulting from addition.
- the output from the upstream register (RGE1, . . . , RGEN) of each cell constitutes a secondary output (SS1, . . . , SSN) from the cell, whereas one of the two inputs to the combining operator (OC1, . . . , OCN) of each cell constitutes a secondary input (ES1, . . . , ESN) to the cell.
- the secondary inputs and outputs of each cell other than the last are respectively connected to the main input and output of the following cell.
- the secondary output SS3 of the last cell is connected to nothing and the secondary input ES3 thereof is connected to permanently receive the value 0.
- the main output SP1 from the first cell C1 is connected to the main input EP1 thereof via the serial multiplexer MX as in the LFSR of FIG. 4, except insofar as the bit flow path in the FIG. 5 LFSR is a serial path and not a parallel path.
- the weighting operators are operators operating in series-parallel mode since all of the bits of each weighting coefficient k1, k2, . . . , kN apply to all of the bits in each digital sample S1, S2, . . . , SN, and since the bits of each weighted digital sample are produced one after the other in serial mode.
- the combining operators OC1, . . . , OCN retain a purely serial structure regardless of the number of bits in the coefficients k1, . . . , kN.
- FIG. 5 LFSR constituting a specific embodiment of the invention is shown in FIG. 6.
- T represents time and the flow of time corresponds to moving down FIG. 6 from the top.
- Numbers 1.1 to 4.2 appear under the letter "T" and correspond to the numbers of successive calculation cycles and steps (with the first digit corresponding to the cycle number and the second digit corresponding to the step number within a cycle).
- FIG. 6 is also subdivided horizontally in a manner corresponding to the physical disposition of the circuit.
- Time instants 1.1 to 3.5 correspond to the initialization stage of the LFSR.
- the LFSR receives one of the three 5-bit samples referenced S1, S2, and S3 via the multiplexer MX.
- the sample S1 comprises bits S11, S12, S13, S14, and S15 which are provided successively during sets 1 to 5 of the first cycle.
- the upstream and downstream registers are assumed to contain zeros, or else to contain data which need not be taken into consideration for understanding the operation of the LFSR as explained with reference to FIG. 6.
- bit S11 is stored in the first of the four bistables in register RGE1 (i.e. in the extreme left-hand bistable in the drawing).
- bit S12 has taken the place of bit S11 which has been moved into the second bistable of RGE1.
- the multiplexer MX establishes communication between RGS1 and RGE1 and isolates RGE1 from the input E: the bit L11 is therefore stored in the first bistable of RGE1 at the beginning of the fourth cycle.
- An LFSR in accordance with the invention having completely systolic architecture reduces the initialization stage to a number of cycles equal to the number of digital samples and avoids the need for interleaving useful samples with null samples, thereby doubling the throughput of useful digital samples.
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Abstract
Description
Claims (1)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8608998 | 1986-06-23 | ||
FR8608998A FR2600440B1 (en) | 1986-06-23 | 1986-06-23 | LINEAR LOOP OFFSET REGISTER CIRCUIT WITH SYSTOLIC ARCHITECTURE |
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US4825397A true US4825397A (en) | 1989-04-25 |
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US07/064,482 Expired - Fee Related US4825397A (en) | 1986-06-23 | 1987-06-22 | Linear feedback shift register circuit, of systolic architecture |
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US (1) | US4825397A (en) |
FR (1) | FR2600440B1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5412665A (en) * | 1992-01-10 | 1995-05-02 | International Business Machines Corporation | Parallel operation linear feedback shift register |
US20050198090A1 (en) * | 2004-03-02 | 2005-09-08 | Altek Corporation | Shift register engine |
US20070047622A1 (en) * | 2005-08-30 | 2007-03-01 | Micron Technology, Inc. | Data generator having linear feedback shift registers for generating data pattern in forward and reverse orders |
US10031723B1 (en) * | 2016-03-08 | 2018-07-24 | Secturion Systems, Inc. | Systolic random number generator |
US11082544B2 (en) * | 2018-03-09 | 2021-08-03 | Microchip Technology Incorporated | Compact timestamp, encoders and decoders that implement the same, and related devices, systems and methods |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3665171A (en) * | 1970-12-14 | 1972-05-23 | Bell Telephone Labor Inc | Nonrecursive digital filter apparatus employing delayedadd configuration |
US3912917A (en) * | 1973-10-23 | 1975-10-14 | Ibm | Digital filter |
US4369499A (en) * | 1980-09-18 | 1983-01-18 | Codex Corporation | Linear phase digital filter |
US4546445A (en) * | 1982-09-30 | 1985-10-08 | Honeywell Inc. | Systolic computational array |
-
1986
- 1986-06-23 FR FR8608998A patent/FR2600440B1/en not_active Expired
-
1987
- 1987-06-22 US US07/064,482 patent/US4825397A/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3665171A (en) * | 1970-12-14 | 1972-05-23 | Bell Telephone Labor Inc | Nonrecursive digital filter apparatus employing delayedadd configuration |
US3912917A (en) * | 1973-10-23 | 1975-10-14 | Ibm | Digital filter |
US4369499A (en) * | 1980-09-18 | 1983-01-18 | Codex Corporation | Linear phase digital filter |
US4546445A (en) * | 1982-09-30 | 1985-10-08 | Honeywell Inc. | Systolic computational array |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5412665A (en) * | 1992-01-10 | 1995-05-02 | International Business Machines Corporation | Parallel operation linear feedback shift register |
US20050198090A1 (en) * | 2004-03-02 | 2005-09-08 | Altek Corporation | Shift register engine |
US20070047622A1 (en) * | 2005-08-30 | 2007-03-01 | Micron Technology, Inc. | Data generator having linear feedback shift registers for generating data pattern in forward and reverse orders |
US7668893B2 (en) | 2005-08-30 | 2010-02-23 | Micron Technology, Inc. | Data generator having linear feedback shift registers for generating data pattern in forward and reverse orders |
US10031723B1 (en) * | 2016-03-08 | 2018-07-24 | Secturion Systems, Inc. | Systolic random number generator |
US10387120B2 (en) | 2016-03-08 | 2019-08-20 | Secturion Systems, Inc. | Systolic random number generator |
US11609743B2 (en) | 2016-03-08 | 2023-03-21 | Secturion Systems, Inc. | Systolic random number generator |
US11082544B2 (en) * | 2018-03-09 | 2021-08-03 | Microchip Technology Incorporated | Compact timestamp, encoders and decoders that implement the same, and related devices, systems and methods |
US11671520B2 (en) | 2018-03-09 | 2023-06-06 | Microchip Technology Incorporated | Compact timestamp, encoders and decoders that implement the same, and related devices, systems and methods |
Also Published As
Publication number | Publication date |
---|---|
FR2600440B1 (en) | 1988-09-09 |
FR2600440A1 (en) | 1987-12-24 |
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