GB2149538A

GB2149538A - Digital multiplier

Info

Publication number: GB2149538A
Application number: GB08427953A
Authority: GB
Inventors: Kerns Harrington Powers
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1981-05-11
Filing date: 1984-11-05
Publication date: 1985-06-12
Also published as: FR2506102A1; SE8202741L; KR840000134A; IT1151396B; PT74839B; ZA823237B; GB2100092A; GB2100092B; PT74839A; ES8308465A1; FI821562A0; JPS581378A; FR2506102B1; DE3217681C2; DE3217681A1; AU8327682A; IT8221180A0; ES511906A0; GB8427953D0; NL8201914A

Abstract

To multiply a number X, by a number p divided by an integral power of 2, p being stored in register 1332, the number X is stored in a plurality of registers 1324-6-8, 1330 in a position each right shifted by one place with respect to the preceding register, the register outputs being selectively added or not in dependence upon the binary representation of p, to generate the product. <IMAGE>

Description

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GB 2 149 538 A

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SPECIFICATION Digital multiplier

5 This invention is divided from our application no. 8213424 ("the parent application") which discloses inter alia, a system for transcoding between video signals sampled at different rates related by the ratio M/2r, where M and r are integers having no 10 common factor. This results in recurrent blocks of samples having integer numbers of input samples and new, output, samples, with the new samples occupying progressively shifting time positions between successive pairs of input samples. The new 15 samples can thereby be derived using a running variable and appropriate weighting.

As described in the parent application, the transcoding algorithm involves multiplication in the form (p/2r)X where X is the value of a particular in-20 put sample and p is a running variable derivable for that particular sample from a read-only memory or by calculation in a logic circuit.

According to the present invention, a digital multiplier for performing such multiplication of a first 25 number which is the quotient of an integer (p) divided by an integral power (r) of two, and a second number (X) having n bits, comprises a first n-bit register coupled to receive said second number;

30 a second register having n+1 bits, said second register being coupled to said first for receiving said second number in the n least significant stages of said second register for effectively dividing the value of said second number by two to 35 form a third number;

a third register having n+2 bits coupled to said first register for receiving said third number in the n + 1 least significant stages of said second register for effectively dividing the value of said third num-40 ber by two to form a fourth number;

a fourth register coupled for receiving the numerator of said first number, said fourth register having at least two stages for representing at least a portion of the value of said numerator in the 45 form of one of two preassigned states which may be assumed by said stages,

summing means; and coupling means coupled to said first and second stages of said fourth register, to said second and 50 third registers and to said summing means for enabling said summing means for controllably forming an output signal from the values of one of said third, said fourth and the sum of said third and said fourth numbers.

55 Such a multiplier is illustrated by the sole figure of the accompanying drawing which illustrates in block diagram form a digital arrangement for dividing an input signal X by a number of the form 2r and multiplying the result by a running variable 60 designated p. In Figure 13, the running variable multiplier p is applied to an input terminal 1310 and multiplicand X is applied to an input terminal 1320. Multiplicand X is applied (in series or in parallel) to a register 1322 which as illustrated is 65 loaded with an 8-bit digital word 10000001, representing the value 129. The MSB of register 1322 represents a value 128. Division by two is accomplished by loading the contents of register 1322 into the last 8 stages of a 9-bit second register 1324. The MSB of register 1324 also represents the value 128, and is preloaded with the value zero. Consequently, the transfer of 10000001, from register 1322 to register 1324 represents a division two. The value stored in 9-bit register 1324 is transferred to the last 9 stages of 10-bit register 1326, the MSB of which is preloaded with the value 1 of 128. Consequently, the transfer of data from register 1324 to 1326 represents a further division-by-two. The data is further divided by successive transfer to 11-bit register 1328 and 12-bit register 1330. At the end of the transfers, registers 1324, 1326, 1328 and 1330 are loaded with X/2, X/4, X/8, and X/16 respectively. Noting that these components represent 8/16X, 4/16X, 2/16X and 1/16X respectively, it is apparent that any fractional value of X from 1/16 to 15/16 can be obtained as the sum of various combinations of the divided values stored on the registers. In the example illustrated, p has a value of 7 (digital 0111) and therefore the contents of registers 1326, 1328 and 1330 must be summed to produce a sum of 7/16X. The value of p is read into a register 1332. The contents of each stage of register 1332 is used to control the gating of registers 1324-1330 as represented by gates 1334-1340. A value of one in a stage of register 1332 allows the corresponding one of registers 1324-1330 to be gated to further summing circuits. Registers 1324 and 1326 are coupled to inputs of a summing circuit 1342, and the registers 1328 and 1330 are coupled to the inputs of a summing circuit 1344. The outputs of summing circuits 1342 and 1344 are coupled to the input of a further summing circuit 1346 where the final output signal (p/ 16X) is formed.

Claims

1. A digital multiplier for multiplying together first and second numbers, when the first number is the quotient of an integer divided by an integer power of two and the second number has n bits, the multiplier comprising:

a first n-bit register coupled to receive said second number;

a second register having n+1 bits, said second register being coupled to said first for receiving said second number in the n least significant stages of said second register for effectively dividing the value of said second number by two to form a third number;

a third register having n+2 bits coupled to said first register for receiving said third number in the n+1 least significant stages of said second register for effectively dividing the value of said third number by two to form a fourth number;

a fourth register coupled for receiving the numerator of said first number, said fourth register having at least two stages for representing at least a portion of the value of said numerator in the form of one of two preassigned states which may

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2 GB 2 149 538 A

2. A digital multiplier substantially as hereinbe-10 fore described with reference to the accompanying drawing.

Printed in the UK for HMSO, D8818935, 4/85, 7102.

Published by The Patent Office, 25 Southampton Buildings, London,

WC2A 1AY, from which copies may be obtained.

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be assumed by said stages,

summing means; and coupling means coupled to said first and second stages of said fourth register, to said second and 5 third registers and to said summing means for enabling said summing means for controllably forming an output signal from the values of one of said third, said fourth numbers.